US20010053101A1 - Semiconductor memory having segmented row repair - Google Patents
Semiconductor memory having segmented row repair Download PDFInfo
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- US20010053101A1 US20010053101A1 US09/928,404 US92840401A US2001053101A1 US 20010053101 A1 US20010053101 A1 US 20010053101A1 US 92840401 A US92840401 A US 92840401A US 2001053101 A1 US2001053101 A1 US 2001053101A1
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
Definitions
- the present invention relates generally to integrated circuit memory devices, and more particularly to a memory device having segmented row repair.
- RAM random access memory
- DRAMs dynamic random access memory
- SRAMs static random access memory
- the testing is typically performed by a memory controller or processor (or a designated processor in a multi-processor machine) which runs a testing program, often before a die containing the semiconductor device is packaged into a chip.
- Random access memories are usually subjected to data retention tests and/or data march tests.
- data retention tests every cell of the memory is written and checked after a pre-specified interval to determine if leakage current has occurred that has affected the stored logic state.
- a march test a sequence of read and/or write operations is applied to each cell, either in increasing or decreasing address order. Such testing ensures that hidden defects will not be first discovered during operational use, thereby rendering end-products unreliable.
- redundant circuitry on the semiconductor device that can be employed to replace malfunctioning circuits found during testing. During the initial testing of a memory device, defective elements are repaired by replacing them with non-defective elements referred to as redundant elements. By enabling such redundant circuitry, the device need not be discarded even if it fails a particular test.
- FIG. 1 illustrates in block diagram form a 256Mbit DRAM 20 .
- DRAM 20 includes eight memory banks or arrays 22 a - 22 h , labeled BANK ⁇ 0> to BANK ⁇ 7>.
- Each memory bank 22 a -h is a 32Mbit array map 24 as illustrated in FIG. 2.
- the architecture of array map 24 illustrated in FIG. 2 divides array map 24 into a plurality of 256K blocks 30 (only one labeled for clarity).
- array map 24 includes eight vertical strips 26 a - 26 h of the 256K blocks 30 across, labeled DQ ⁇ 0> to DQ ⁇ 7>, and is sixteen strips of the 256K blocks 30 high.
- Memory cells (not shown) in each 256K block 30 are arranged in a plurality of primary rows and redundant rows. For example, typically 512 primary rows and 4 redundant rows are provided.
- Sense amplifiers 32 are provided between each row of 256K blocks 30 for sensing data stored in the memory cells therein.
- Wordline drivers 34 are provided on each side of each vertical strip of 256K blocks 30 for firing a wordline in each 256K block 30 associated with a specified row address. Accordingly, there will be an associated wordline and wordline driver for each row of memory cells in a 256K block 30 .
- wordline driver 34 actually comprises a plurality of wordline drivers, one for each wordline.
- each wordline driver 34 will fire either a wordline associated with an odd row or an even row.
- FIG. 3 illustrates a single horizontal strip of 256K blocks 30 from FIG. 2.
- Wordline drivers 34 a , 34 c , 34 e , 34 g and 34 i will fire even row wordlines, while drivers 34 b , 34 d , 34 f and 34 h will fire odd row wordlines.
- wordline driver 34 a will fire even rows 40 in block 26 a
- wordline driver 34 c will fire even rows 40 in blocks 26 b and 26 c
- wordline driver 34 e will fire even rows 40 in blocks 26 d and 26 e
- wordline driver 34 g will fire even rows 40 in blocks 26 f and 26 g
- wordline driver 34 i will fire even rows 40 in block 26 h .
- wordline driver 34 b will fire odd rows 42 in blocks 26 a and 26 b
- wordline driver 34 d will fire odd rows 42 in blocks 26 c and 26 d
- wordline driver 34 f will fire odd rows 42 in blocks 26 e and 26 f
- wordline driver 34 h will fire odd rows 42 in blocks 26 g and 26 h.
- a memory cell is accessed by applying a specific row address to the wordline drivers 34 .
- a local wordline driver is driven by application of the address and a phase term provided from a global wordline driver (not shown) to activate the selected cell row via one of the row lines, while a column decoder (not shown) will activate the column select circuits to access specified memory cells on an open row. Accordingly, the selected row will be activated across all eight vertical strips 26 a - 26 h.
- memory devices typically employ redundant rows and columns of memory cells so that if a memory cell in a column or row of the primary memory array is defective, then an entire column or row of redundant memory cells can be substituted therefore.
- Substitution of one or more of the spare rows or columns is conventionally accomplished by opening a specific combination of fuses (not shown) or closing antifuses in one of several fuse banks (not shown) on the die.
- a selected combination of fuses are blown to provide an address equal to the address of the defective cell. For example, if the defective cell has an eight-bit binary address of 11011011, then the third and sixth fuses in a set of eight fuses within one of several fuse banks will be blown, thereby storing this address.
- a compare circuit (not shown) compares each incoming address to the blown fuse addresses stored in the fuse banks to determine whether the incoming address matches with one of the blown fuse addresses. If the compare circuit determines a match, then it outputs a match signal (typically one bit). In response thereto, the wordline drivers 34 of a redundant row will be activated to access the redundant row in substitution for the row with the defective memory cell.
- the present invention overcomes the problems associated with the prior art and provides a memory device having a segmented row repair architecture that provides the benefits of localized or single bit repair, thereby efficiently utilizing redundant rows of the memory device.
- FIG. 2 illustrates one bank of the memory device of FIG. 1;
- FIG. 4 illustrates a portion of a memory device in accordance with the present invention
- FIG. 5 illustrates a memory bank in accordance with the present invention
- FIG. 6 illustrates the segmentation of the rows in accordance with the present invention.
- FIG. 4 illustrates a portion of a memory device having segmented row repair in accordance with the present invention. Specifically, FIG. 4 illustrates the area between two vertical strips of the 256K blocks 30 where the wordline drivers 34 are located.
- the wordline drivers 34 for the segment of the row that includes a defective memory cell can be disabled, and one of the redundant wordline drivers 34 enabled, to replace the defective memory cell, as will be described further below.
- matching circuit 82 determines the address of the cell to be accessed matches a defective address, requiring substitution of a redundant element.
- Matching circuit 82 will output a high match signal RED 58 and accordingly signal RED* 56 will be low.
- the low input of signal RED* 56 to AND gates 50 a - 50 d will cause a low output from AND gates 50 a - 50 d , regardless of the state of the GPH signals 60 - 66 being input to AND gates 50 a - 50 d .
- the low outputs from AND gates 50 a - 50 d will effectively disable the wordline drivers 34 for the primary rows of the 256K blocks 30 .
- FIG. 5 illustrates how only a portion of a primary row can be selectively disable and replaced with a corresponding portion of a redundant row according to the present invention.
- FIG. 5 illustrates in block diagram form a 32 Mbit bank 124 in accordance with the present invention.
- matching circuit 82 includes a logic portion 84 .
- the logic portion 84 could be separate from matching circuit 82 .
- the matching signals RED 58 and RED* 56 run between each vertical strip 26 a - 26 h of the bank 124 and on the outer edge of strips 26 a and 26 h.
- Phase signals GPH 60 - 66 and RPH 70 - 76 run between each horizontal strip and on the outer edge of the horizontal strips (not shown in FIG. 5 for clarity).
- Segment ⁇ 0> includes the 256K blocks 30 DQ ⁇ 0> and DQ ⁇ 1>
- Segment ⁇ l> includes the 256K blocks 30 DQ ⁇ 2> and DQ ⁇ 3>
- Segment ⁇ 2> includes the 256K blocks 30 DQ ⁇ 4> and DQ ⁇ 5>
- Segment ⁇ 3> includes the 256K blocks 30 DQ ⁇ 6> and DQ ⁇ 7>.
- Segment ⁇ 0> includes the 256K blocks 30 DQ ⁇ 0> and DQ ⁇ 7>
- Segment ⁇ 1> includes the 256K blocks 30 DQ ⁇ 1> and DQ ⁇ 2>
- Segment ⁇ 2> includes the 256K blocks 30 DQ ⁇ 3> and DQ ⁇ 4>
- Segment ⁇ 3> includes the 256K blocks 30 DQ ⁇ 5> and DQ ⁇ 6>.
- the rows of a memory bank are segmented into four segments and segmented row repair is provided by selectively disabling a wordline driver for only one segment in which a defective memory cell is located and enabling a redundant wordline driver with a redundant term signal, thereby selecting a redundant row segment for only a specific portion of the entire row length.
- a typical processor based system which includes a memory device according to the present invention is illustrated generally at 200 in FIG. 7.
- a computer system is exemplary of a system having digital circuits which include memory devices. Most conventional computers include memory devices permitting storage of significant amounts of data. The data is accessed during operation of the computers. Other types of dedicated processing systems, e.g., radio systems, television systems, GPS receiver systems, telephones and telephone systems also contain memory devices which can utilize the present invention.
- a processor based system such as a computer system, for example, generally comprises a central processing unit (CPU) 210 , for example, a microprocessor, that communicates with one or more input/output (I/O) devices 240 over a bus 270 .
- the computer system 200 also includes random access memory (RAM) such as DRAM 260 , and, in the case of a computer system may include peripheral devices such as a floppy disk drive 220 and a compact disk (CD) ROM drive 230 which also communicate with CPU 210 over the bus 270 .
- RAM 260 is preferably constructed as an integrated circuit which includes circuitry to allow for segmented row repair as previously described with respect to FIGS. 4 - 6 . It may also be desirable to integrate the processor 210 and memory 260 on a single IC chip.
Abstract
Description
- 1. Field of the Invention
- The present invention relates generally to integrated circuit memory devices, and more particularly to a memory device having segmented row repair.
- 2. Description of the Related Art
- Memory tests on semiconductor devices, such as random access memory (RAM) integrated circuits, e.g., DRAMs, SRAMs and the like, are typically performed by the manufacturer during production and fabrication to locate defects and failures in such devices that can occur during the manufacturing process of the semiconductor devices. Defects may be caused by a number of factors, including particle defects such as broken or shorted out columns and rows, particle contamination, or bit defects. The testing is typically performed by a memory controller or processor (or a designated processor in a multi-processor machine) which runs a testing program, often before a die containing the semiconductor device is packaged into a chip.
- Random access memories are usually subjected to data retention tests and/or data march tests. In data retention tests, every cell of the memory is written and checked after a pre-specified interval to determine if leakage current has occurred that has affected the stored logic state. In a march test, a sequence of read and/or write operations is applied to each cell, either in increasing or decreasing address order. Such testing ensures that hidden defects will not be first discovered during operational use, thereby rendering end-products unreliable.
- Many semiconductor devices, particularly memory devices, include redundant circuitry on the semiconductor device that can be employed to replace malfunctioning circuits found during testing. During the initial testing of a memory device, defective elements are repaired by replacing them with non-defective elements referred to as redundant elements. By enabling such redundant circuitry, the device need not be discarded even if it fails a particular test.
- FIG. 1 illustrates in block diagram form a
256Mbit DRAM 20.DRAM 20 includes eight memory banks or arrays 22 a-22 h, labeled BANK<0> to BANK<7>. Each memory bank 22 a-h is a32Mbit array map 24 as illustrated in FIG. 2. The architecture ofarray map 24 illustrated in FIG. 2 dividesarray map 24 into a plurality of 256K blocks 30 (only one labeled for clarity). As shown,array map 24 includes eight vertical strips 26 a-26 h of the256K blocks 30 across, labeled DQ<0> to DQ<7>, and is sixteen strips of the256K blocks 30 high. Memory cells (not shown) in each256K block 30 are arranged in a plurality of primary rows and redundant rows. For example, typically 512 primary rows and 4 redundant rows are provided.Sense amplifiers 32 are provided between each row of256K blocks 30 for sensing data stored in the memory cells therein. Wordlinedrivers 34 are provided on each side of each vertical strip of256K blocks 30 for firing a wordline in each256K block 30 associated with a specified row address. Accordingly, there will be an associated wordline and wordline driver for each row of memory cells in a256K block 30. Thus, it should be understood thatwordline driver 34 actually comprises a plurality of wordline drivers, one for each wordline. - Within each
256K block 30, the rows are designated as either an even row or an odd row. Accordingly, eachwordline driver 34 will fire either a wordline associated with an odd row or an even row. FIG. 3 illustrates a single horizontal strip of256K blocks 30 from FIG. 2. Wordlinedrivers drivers driver 34 a will fire evenrows 40 inblock 26 a, wordlinedriver 34 c will fire evenrows 40 inblocks driver 34 e will fire evenrows 40 inblocks driver 34 g will fire evenrows 40 inblocks rows 40 inblock 26 h. Conversely, wordlinedriver 34 b will fireodd rows 42 inblocks driver 34 d will fireodd rows 42 inblocks driver 34 f will fireodd rows 42 inblocks driver 34 h will fireodd rows 42 inblocks - A memory cell is accessed by applying a specific row address to the
wordline drivers 34. A local wordline driver is driven by application of the address and a phase term provided from a global wordline driver (not shown) to activate the selected cell row via one of the row lines, while a column decoder (not shown) will activate the column select circuits to access specified memory cells on an open row. Accordingly, the selected row will be activated across all eight vertical strips 26 a-26 h. - As noted above, memory devices typically employ redundant rows and columns of memory cells so that if a memory cell in a column or row of the primary memory array is defective, then an entire column or row of redundant memory cells can be substituted therefore. Substitution of one or more of the spare rows or columns is conventionally accomplished by opening a specific combination of fuses (not shown) or closing antifuses in one of several fuse banks (not shown) on the die. A selected combination of fuses are blown to provide an address equal to the address of the defective cell. For example, if the defective cell has an eight-bit binary address of 11011011, then the third and sixth fuses in a set of eight fuses within one of several fuse banks will be blown, thereby storing this address. A compare circuit (not shown) compares each incoming address to the blown fuse addresses stored in the fuse banks to determine whether the incoming address matches with one of the blown fuse addresses. If the compare circuit determines a match, then it outputs a match signal (typically one bit). In response thereto, the
wordline drivers 34 of a redundant row will be activated to access the redundant row in substitution for the row with the defective memory cell. - There are drawbacks, however, with the redundant row substitution approach described above. The redundant rows of memory cells necessarily occupy space on the die. Therefore, it is desirable to obtain the maximum number of repairs using a minimum number of spare rows by utilizing a single bit repair method. This is not possible, however, when a complete redundant row must be substituted for a primary row that has only a single defective memory cell, as a substantial amount of non-defective memory cells will also necessarily be replaced by the redundant row. For example, if
vertical strip 26 d of FIG. 3 has a defective memory cell, when a redundant row is used to replace the row in which the defective memory cell is located, the entire redundant row will be utilized across all strips 26 a-26 h, even though there may be no defects in the corresponding row in the other seven strips 26 a-26 c and 26 e-26 h. - Thus, there exists a need for a memory device in which efficient use of a redundant circuit to replace a defective primary circuit is provided, thereby minimizing die space required for the redundant circuit.
- The present invention overcomes the problems associated with the prior art and provides a memory device having a segmented row repair architecture that provides the benefits of localized or single bit repair, thereby efficiently utilizing redundant rows of the memory device.
- In accordance with the present invention, the rows of a memory bank are segmented into four segments and segmented row repair is provided by selectively disabling a wordline driver for only one segment in which a defective memory cell is located and enabling a redundant wordline driver with a redundant term signal provided by the redundancy matching circuit, thereby selecting a redundant row segment for only a specific portion of the entire row length. By selectively disabling only the wordline driver associated with the defective memory cell and dividing the primary and redundant rows into four segments, localized or single bit repair can be performed, thereby efficiently utilizing the redundant rows of the memory device.
- These and other advantages and features of the invention will become more readily apparent from the following detailed description of the invention which is provided in connection with the accompanying drawings.
- FIG. 1 illustrates in block diagram form a conventional memory device;
- FIG. 2 illustrates one bank of the memory device of FIG. 1;
- FIG. 3 illustrates a portion of the memory bank from FIG. 2;
- FIG. 4 illustrates a portion of a memory device in accordance with the present invention;
- FIG. 5 illustrates a memory bank in accordance with the present invention;
- FIG. 6 illustrates the segmentation of the rows in accordance with the present invention; and
- FIG. 7 illustrates in block diagram form a processor system in which a memory device in accordance with the present invention can be used.
- The present invention will be described as set forth in the preferred embodiments illustrated in FIGS.4-7. Other embodiments may be utilized and structural or logical changes may be made without departing from the spirit or scope of the present invention. Like items are referred to by like reference numerals.
- In accordance with the present invention, segmented row repair is provided by selectively disabling a wordline driver for a row segment containing a defective memory cell and enabling a redundant wordline driver for a redundant row segment with a redundant term signal provided by the redundancy matching circuit, thereby substituting a redundant row segment for only a specific segment of the entire row length which contains a defective memory cell.
- FIG. 4 illustrates a portion of a memory device having segmented row repair in accordance with the present invention. Specifically, FIG. 4 illustrates the area between two vertical strips of the 256K blocks30 where the wordline
drivers 34 are located. In accordance with the present invention, the wordlinedrivers 34 for the segment of the row that includes a defective memory cell can be disabled, and one of theredundant wordline drivers 34 enabled, to replace the defective memory cell, as will be described further below. - A
global wordline driver 52 activates a desired row by providing an address term and four phase signals, as is known in the art. The use of the four phase signals reduces the number of address terms required for each256K block 30. Thus, for example, if there are 512 rows in the256K block 30, the number of address terms can be reduced to 128 by using the four phase signals (128×4=512). The four phase signals are global phase signal (GPH) <0> 60, GPH<1> 62, GPH<2> 64 and GPH<3> 66. Similar phase signals are also provided to activate the redundant row included in each256K block 30. Specifically, the signals for the redundant rows include redundant phase signal (RPH)<0> 70, RPH<1> 72, RPH<2> 74 and RPH<3> 76. In accordance with the present invention, a plurality of AND gates 50 a-50 h are provided. A first input of each AND gate 50 a-50 d is connected to one of the four global phase (GPH) signals 60-66 from theglobal driver 52, and a first input of each AND gate 50 e-50 h is connected to one of the four redundant phase (RPH) signals 70-76. Specifically, ANDgate 50 a has a first input connected to the signal GPH<1> 62, AND gate 50 b has a first input connected to the signal GPH<0>60, ANDgate 50 c has a first input connected to the signal GPH<3> 66, ANDgate 50 d has a first input connected to the signal GPH<2> 64, ANDgate 50 e has a first input connected to the signal RPH<1> 72, ANDgate 50 f has a first input connected to the signal RPH<0> 70, ANDgate 50 g has a first input connected to the signal RPH<3> 76, and ANDgate 50 h has a first input connected to the signal RPH<2> 74. The output from each AND gate 50 a-50 d is connected to the wordlinedrivers 34 for the primary rows of 256K blocks 30, while the output from each AND gate 50 e-50 h is connected to a redundant wordline drive 34 for the redundant rows of 256K blocks 30. Thus, the output from the AND gates 50 a-50 h, in conjunction with the address terms fromglobal driver 52 onbus line 80, will drive the desiredwordline driver 34 orredundant wordline driver 34 to activate a selected primary row (labeled WL<0:256>) or a redundant row (labeled RWL<0:1> and RWL<2:3>) in the 256K blocks 30. - The selective disabling of a wordline driver and enabling of a redundant wordline driver according to the present invention is as follows. In accordance with the present invention, a pair of complementary redundant matching signals,
RED 58 and RED* 56, are provided from a matchingcircuit 82.Signal RED 58 is input to a second input of each AND gate 50 e-50 h. Signal RED* 56 is input to a second input of each AND gate 50 a-50 d.Matching circuit 82 compares each incoming address to addresses of defective memory cells, typically designated by blown fuse addresses stored in fuse banks (not shown), as is known in the art and described with respect to FIGS. 1 and 2, to determine whether the incoming address matches with one of the blown fuse addresses, i.e., a defective memory cell. If matchingcircuit 82 determines there is not a match, i.e., the address for the desired memory cell does not match the address of a defective memory cell, it is not necessary to substitute one of the redundant wordlines and the appropriate primary wordline can be activated. The redundantmatch signal RED 58 output from matchingcircuit 82 will be low, and accordingly signal RED* 56 will be high. The low input ofsignal RED 58 to AND gates 50 e-50 h will cause a low output from AND gates 50 e-50 h, regardless of the state of the RPH signals 70-76 being input to AND gates 50 e-50 h. The low outputs from AND gates 50 e-50 h will effectively disable theredundant wordline drivers 34 by not driving theredundant wordline drivers 34. - Conversely, the high signal RED*56 output from matching
circuit 82 being input to the second input of AND gates 50 a-50 d will cause the output of one of the AND gates 50 a-50 d to be high, depending on the state of the GPH signals 60-66.Global driver 52 wil output a high signal on one phase of signals GPH 60-66, and a high signal on the corresponding signal RPH 70-76, depending on the address of the memory cell selected for access and an address specified bymatch circuit 82 vialine 83, respectively, and a low signal on the other three global and other three redundant phase signals. For example, if the address of the cell for access requires that phase <1> be high, then both GPH<1> 62 and, for example, RPH<1> 72 will be high, while the remaining phase signals will be low. It should be noted, however, that any one of the redundant phase signals RPH 70-76 could be high depending on which programmed fuse bank matched the incoming address. The high signal GPH<1> 62 and the high signal RED* 56 input to ANDgate 50 a will cause a high output from ANDgate 50 a, which, along with the address term onbus line 80, will activate theappropriate wordline driver 34 to drive its associated wordline of a primary row of the 256K blocks 30 associated with thatwordline driver 34. - Now suppose, for example, matching
circuit 82 determines the address of the cell to be accessed matches a defective address, requiring substitution of a redundant element.Matching circuit 82 will output a highmatch signal RED 58 and accordingly signal RED* 56 will be low. The low input of signal RED* 56 to AND gates 50 a-50 d will cause a low output from AND gates 50 a-50 d, regardless of the state of the GPH signals 60-66 being input to AND gates 50 a-50 d. The low outputs from AND gates 50 a-50 d will effectively disable the wordlinedrivers 34 for the primary rows of the 256K blocks 30. - Conversely, the
high signal RED 58 output from matchingcircuit 82 being input to the second input of AND gates 50 e-50 h will cause the output of one of the AND gates 50 e-50 d to be high, depending on the state of the RPH signals 70-76. As noted above,global driver 52 will output a high signal on one phase of signals GPH 60-66, and a high signal on the corresponding signal RPH 70-76, depending on the address of the memory cell selected for access and an address specified bymatch circuit 82 vialine 83, respectively, and a low signal on the other three global and other three redundant phase signals. For example, if the address of the cell for access requires that phase <1> be high, then both GPH<1> 62 and, for example, RPH<1> 72 will be high, while the remaining phase signals will be low. It should be noted, however, that any one of the redundant phase signals RPH 70-76 could be high depending on which programmed fuse bank matched the incoming address. The high signal RPH<1> 72 and thehigh signal RED 58 input to ANDgate 50 e will cause a high output from ANDgate 50 e, which, along with the address term online 80, will activate the appropriateredundant wordline driver 34 to drive its associated redundant wordline of a redundant row of its associated 256K blocks 30, such as for example RWL<0>. - Thus, by utilizing AND gates50 a-50 h in conjunction with the phase signals GPH 60-66 and RPH 70-76, and the redundant matching signals
RED 58 and RED* 56, it is possible to disable awordline driver 34 associated with a defective cell in only a portion of a primary row of 256K block and enable aredundant wordline driver 34 associated with a portion of a redundant row to replace the defective cell. - FIG. 5 illustrates how only a portion of a primary row can be selectively disable and replaced with a corresponding portion of a redundant row according to the present invention. FIG. 5 illustrates in block diagram form a 32 Mbit
bank 124 in accordance with the present invention. As shown in FIG. 5, matchingcircuit 82 includes alogic portion 84. Alternatively, thelogic portion 84 could be separate from matchingcircuit 82. The matching signalsRED 58 and RED* 56 run between each vertical strip 26 a-26 h of thebank 124 and on the outer edge ofstrips redundant wordline drivers 34 and AND gates 50 a-50 h, is also provided between each vertical strip 26 a-26 h and on the outer edges ofstrips gap cells 92, i.e., the area of intersection of the wordlinedrivers 34 andsense amplifiers 32 between each vertical strip 26 a-26 h and each horizontal strip.Logic 84 selectively controls the application of the match signalsRED 58 and RED* 56 to the vertical strip 26 a-26 h based on the address of the cell being accessed. - Suppose for example there is a
defective element 90 in an odd row of256K block 30 located in the first horizontal strip invertical strip 26 d. The incoming cell address will be compared with the defective cell addresses, and a match determined. Accordingly, the defective element must be replaced by a redundant element.Matching circuit 82 will provide a highmatch signal RED 58 and low match signal RED* 56 tologic 84.Logic 84, based on the cell address, will provide these signals only on the signal lines 56, 58 located betweenvertical strips primary wordline drivers 34 and enable theredundant wordline drivers 34, as described with respect to FIG. 4, for only the 256K blocks 30 invertical strips match signal RED 58, thereby enabling theworldine drivers 34 associated with the primary rows in the other vertical strips. - Accordingly, only a single segment will be replaced by redundant elements. The segmentation of the rows according to the present invention is illustrated in FIG. 6. As shown in FIG. 6, each row across a bank of memory is segmented into four segments, labeled Segment<0> to Segment<3>. For
odd rows 42, Segment<0> includes the 256K blocks 30 DQ<0> and DQ<1>, Segment<l> includes the 256K blocks 30 DQ<2> and DQ<3>, Segment<2> includes the 256K blocks 30 DQ<4> and DQ<5>, and Segment<3> includes the 256K blocks 30 DQ<6> and DQ<7>. For theeven rows 40, Segment<0> includes the 256K blocks 30 DQ<0> and DQ<7>, Segment<1> includes the 256K blocks 30 DQ<1> and DQ<2>, Segment<2> includes the 256K blocks 30 DQ<3> and DQ<4>, and Segment<3> includes the 256K blocks 30 DQ<5> and DQ<6>. - Thus, when only a single segment, such as for example Segment<1> from the above example which includes the odd rows in
vertical strip 26 d (DQ<3>) is disabled, the remaining segments of the redundant row can still be used to repair additional defective cells within the other 256K blocks 30 within this strip. It should be understood that more than one segment can be repaired within each row, i.e., thelogic 84 can provide a highmatch signal RED 58 to more than one segment if necessary. In the case of a cluster failure, in which several defective elements are located within an area, it is still possible to replace an entire row if necessary utilizing the redundant row across the same horizontal strip or to borrow an entire redundant row from other horizontal strips to replace an entire row, or only a portion of an entire row by selectively applying the high redundancymatch signal RED 58 to one or more segments. - Thus, in accordance with the present invention, the rows of a memory bank are segmented into four segments and segmented row repair is provided by selectively disabling a wordline driver for only one segment in which a defective memory cell is located and enabling a redundant wordline driver with a redundant term signal, thereby selecting a redundant row segment for only a specific portion of the entire row length. By selectively disabling only the wordline driver associated with the defective memory cell and dividing the primary and redundant rows into four segments, localized or single bit repair can be performed, thereby efficiently utilizing the redundant rows of the memory device.
- A typical processor based system which includes a memory device according to the present invention is illustrated generally at200 in FIG. 7. A computer system is exemplary of a system having digital circuits which include memory devices. Most conventional computers include memory devices permitting storage of significant amounts of data. The data is accessed during operation of the computers. Other types of dedicated processing systems, e.g., radio systems, television systems, GPS receiver systems, telephones and telephone systems also contain memory devices which can utilize the present invention.
- A processor based system, such as a computer system, for example, generally comprises a central processing unit (CPU)210, for example, a microprocessor, that communicates with one or more input/output (I/O) devices 240 over a
bus 270. Thecomputer system 200 also includes random access memory (RAM) such asDRAM 260, and, in the case of a computer system may include peripheral devices such as afloppy disk drive 220 and a compact disk (CD)ROM drive 230 which also communicate withCPU 210 over thebus 270.RAM 260 is preferably constructed as an integrated circuit which includes circuitry to allow for segmented row repair as previously described with respect to FIGS. 4-6. It may also be desirable to integrate theprocessor 210 andmemory 260 on a single IC chip. - It should be noted that while the preferred embodiment of the invention is described as applied to a 256 Mbit memory DRAM device having typical row addressable architecture, the invention is not so limited and may be applied to memory devices having other architectures or sizes as well. Additionally, while the invention has been described with reference to segmenting the rows into four segments, the invention is not so limited and any number of segments can be used.
- While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Additions, deletions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention. Accordingly, the invention is not to be considered as limited by the foregoing description but is only limited by the scope of the appended claims.
Claims (53)
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EP1292952B1 (en) | 2009-04-08 |
EP1292952B8 (en) | 2009-08-05 |
CN101471140A (en) | 2009-07-01 |
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WO2001097226A3 (en) | 2002-05-10 |
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CN100442434C (en) | 2008-12-10 |
WO2001097226A2 (en) | 2001-12-20 |
ATE428175T1 (en) | 2009-04-15 |
KR100595813B1 (en) | 2006-07-03 |
CN1636260A (en) | 2005-07-06 |
JP2004503897A (en) | 2004-02-05 |
KR20030009526A (en) | 2003-01-29 |
US6442084B2 (en) | 2002-08-27 |
ES2325056T3 (en) | 2009-08-25 |
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