US20010053170A1 - Semiconductor device test apparatus - Google Patents

Semiconductor device test apparatus Download PDF

Info

Publication number
US20010053170A1
US20010053170A1 US09/434,490 US43449099A US2001053170A1 US 20010053170 A1 US20010053170 A1 US 20010053170A1 US 43449099 A US43449099 A US 43449099A US 2001053170 A1 US2001053170 A1 US 2001053170A1
Authority
US
United States
Prior art keywords
semiconductor device
test apparatus
electrodes
measured
device test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/434,490
Other versions
US6407563B2 (en
Inventor
Mikio Ohtaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Assigned to OKI ELECTRIC INDUSTRY CO., LTD. reassignment OKI ELECTRIC INDUSTRY CO., LTD. INVALID RECORDING. SEE DOCUMENT RECORDED AT REEL 010754, FRAME 0183. (RE-RECORD TO CORRECT THE RECORDATION DATE) Assignors: OHTAKI, MIKIO
Assigned to OKI ELECTRIC INDUSTRY CO., LTD. reassignment OKI ELECTRIC INDUSTRY CO., LTD. (ASSIGNMENT OF ASSIGNOR'S INTEREST) RE-RECORD TO CORRECT THE RECORDATION DATE OF 11-4-99 TO 11-5-99 PREVIOUSLY RECORDED AT REEL 10387, FRAME 0317. Assignors: OHTAKI, MIKIO
Application filed by Individual filed Critical Individual
Priority to US09/904,663 priority Critical patent/US6879169B2/en
Publication of US20010053170A1 publication Critical patent/US20010053170A1/en
Publication of US6407563B2 publication Critical patent/US6407563B2/en
Application granted granted Critical
Priority to US10/279,988 priority patent/US7262610B2/en
Priority to US11/785,644 priority patent/US7639027B2/en
Assigned to OKI SEMICONDUCTOR CO., LTD. reassignment OKI SEMICONDUCTOR CO., LTD. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: OKI ELECTRIC INDUSTRY CO., LTD.
Assigned to Lapis Semiconductor Co., Ltd. reassignment Lapis Semiconductor Co., Ltd. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: OKI SEMICONDUCTOR CO., LTD
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2855Environmental, reliability or burn-in testing
    • G01R31/286External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01KMEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K1/00Details of thermometers not specially adapted for particular types of thermometer
    • G01K1/16Special arrangements for conducting heat from the object to the sensitive element

Definitions

  • the present invention relates to a semiconductor device test apparatus.
  • An IC socket which matches the shape of the device to be measured is employed to test a newly developed device in the prior art.
  • An IC socket, which comes into electrical contact with the device to be measured, fulfills a function as a means for electrical signal communication between a peripheral device and the device to be measured.
  • FIG. 29 is a sectional view of a device to be measured 1 and an IC socket 3 mounted at a circuit board 5 , illustrating the connections among them.
  • the IC socket 3 is provided with a plurality of contacts 3 a , and is soldered onto the circuit board 5 at the contacts 3 a .
  • the device to be measured 1 which is pressed down by a holding member 7 , is electrically connected with the contacts 3 a of the IC socket 3 .
  • FIG. 30 is a perspective of the device to be measured 1 , showing its surface on which electrodes are formed.
  • the device to be measured 1 is a CSP (chip-size package) device achieved through chip size packaging.
  • the device to be measured 1 is provided with a plurality of electrodes 1 a through which electrical signals are input and output and power is supplied.
  • the individual contacts 3 a provided at the IC socket 3 are positioned so that they come in contact with the corresponding electrodes 1 a.
  • FIG. 31 is a plan view of the circuit board 5 with the devices to be measured 1 and the IC sockets 3 mounted, viewed from above.
  • the circuit board 5 is allowed to engage in electrical signal communication with peripheral devices such as an IC tester and EL bum-in apparatus (not shown) via connection terminals 5 a and 5 b.
  • a functional test on a wafer-level device is implemented by adopting a method whereby probes are placed in contact with wafer pads constituting signal input/output electrodes and source electrodes of the device.
  • probes are normally constituted of materials with a high degree of hardness such as tungsten and beryllium copper.
  • FIG. 32 illustrates a probe card 13 provided with probes 11 .
  • a specific circuit that corresponds to the device to be measured is printed, and electrical signal communication with peripheral devices (not shown) is enabled via connection terminals 13 a and 13 b.
  • FIG. 33 The positional relationship between a probe card 13 and the wafer 15 which constitutes the device to be measured is illustrated in FIG. 33. Electrical signals provided by a peripheral device are input to the probe card 13 via the connection terminals 13 a and 13 b , travel through the circuit formed at the probe card 13 to reach the probe 11 . Then, the electrical signals are applied to the pads formed at the wafer 15 from the probe 11 . In addition, electrical signals output by the wafer 15 travel through the reverse route to reach a peripheral device. The structure described above enables a functional test on the wafer 15 .
  • the body size of IC sockets imposes a restriction upon the number of IC sockets that can be mounted at a circuit board. Such restriction on the number of IC sockets that can be mounted at the circuit board ultimately restricts the number of devices that can be tested in a single functional test. Thus, functional tests conducted on devices utilizing IC sockets in the prior art are not always efficient.
  • probes In order to achieve a higher degree of efficiency in functional tests conducted by employing probes, it is desirable to increase the number of probes mounted at a probe card so that many devices can be tested at once.
  • probes are secured to the probe card using a resin or the like in the prior art, which requires a large space for securing them. Thus, it is difficult to increase the number of probes without increasing the probe card size.
  • a semiconductor device test apparatus that is capable of testing one or a plurality of semiconductor devices each provided with a plurality of electrodes.
  • the semiconductor device test apparatus according to the present invention is characterized in that it is provided with a circuit board having a circuit that corresponds to the semiconductor device and a plurality of electrodes that correspond to individual electrodes at the semiconductor device and a connection plate that is provided with a plurality of conductive portions that electrically connect the individual electrodes at the semiconductor device and the individual electrodes at the circuit board on a one-to-one basis.
  • This structure allows the semiconductor device to be electrically connected to the circuit board via the connection plate.
  • the semiconductor device can be driven by inputting various types of electrical signals to the circuit board from peripheral devices, and various types of electrical signals output by the semiconductor device are communicated to the peripheral devices.
  • the connection plate having a plurality of conductive portions provided to electrically connect the individual electrodes at the semiconductor device and the individual electrodes at the circuit board, an extremely simple structure is realized for the apparatus.
  • the conductive portions are each formed at one of a plurality of through holes provided at the connection plate. Even when electrodes at the semiconductor device are arrayed over an extremely fine pitch, the semiconductor device can be tested with ease by reducing the electrode pitch at the circuit board and reducing the through hole pitch.
  • a conductive elastic body that electrically connects the individual conductive portions at the connection plate and the individual electrodes at the semiconductor device on a one-to-one basis is provided between the connection plate and the semiconductor device.
  • a positioning member that secures the semiconductor device may be provided.
  • This positioning member may be constituted of a plate member having a through portion formed that corresponds to the shape of the semiconductor device, for instance.
  • Such a configuration will allow the semiconductor device to be secured through an extremely simple structure. In addition, the space required to secure the semiconductor device can be reduced.
  • circuitboard, the connection plate and the positioning member may be provided as an integrated unit, or the circuitboard, the connection plate, the conductive elastic body and the positioning member may be provided as an integrated unit.
  • Such a structure eliminates the necessity for assembling the circuit board, the connection plate and the positioning member when testing the semiconductor device, to achieve a higher degree of efficiency in testing.
  • connection plate By using film to constitute the connection plate, an extremely thin connection plate is realized.
  • connection plate constituted of film can bend freely, more reliable electrical connection between the individual electrodes at the semiconductor device and the individual electrodes at the circuit board is assured.
  • a printed board may be used to constitute the connection plate.
  • the production cost can be reduced compared to the cost of production using film.
  • a semiconductor device test apparatus employed to test one or a plurality of semiconductor devices each having a plurality of electrodes, which is characterized In that it is provided with a probe holding member having a plurality of probes fitted therein so that the individual sharp ends of the plurality of probes corresponding to the individual electrodes at the semiconductor device on a one-to-one basis and the ends of the probes located on the other side of the sharp ends are exposed.
  • a chip or a wafer may be used as the semiconductor device to be tested.
  • FIG. 1 is a perspective illustrating the structure of the semiconductors device test apparatus in a first embodiment
  • FIG. 2 is a sectional view of the semiconductor device test apparatus in FIG. 1;
  • FIG. 3 is an enlargement of the sectional view of the semiconductor device test apparatus in FIG. 2;
  • FIG. 4 is a sectional view illustrating the structure of the semiconductor test apparatus in a second embodiment
  • FIG. 5 is an enlargement of the sectional view of the semiconductor device test apparatus in FIG. 4;
  • FIG. 6 is a sectional view illustrating the structure of the semiconductor test apparatus in a third embodiment
  • FIG. 7 is a perspective illustrating the structure of the semiconductor device test apparatus in a fourth embodiment
  • FIG. 8 is a sectional view of the semiconductor device test apparatus in FIG. 7;
  • FIG. 9 is an enlargement of the sectional view of the semiconductor device test apparatus in FIG. 8;
  • FIG. 10 is a sectional view illustrating the structure of the semiconductor test apparatus in the fifth embodiment.
  • FIG. 11 is an enlargement of the sectional view of the semiconductor device test apparatus in FIG. 10;
  • FIG. 12 is a sectional view illustrating the structure of the semiconductor test apparatus in the sixth embodiment.
  • FIG. 13 is a perspective illustrating the structure of the semiconductor device test apparatus in a seventh embodiment
  • FIG. 14 is a plan view of a wafer to be measured that may be tested by the semiconductor device test apparatus illustrated in FIG. 13;
  • FIG. 15 is a sectional view of a CSP device obtained from the wafer to be measured in FIG. 14;
  • FIG. 16 is a sectional view illustrating the semiconductor device test apparatus in FIG. 13 immediately before the wafer to be measured in FIG. 14 is fitted;
  • FIG. 17 is a sectional view illustrating the semiconductor device test apparatus in FIG. 13 with the wafer to be measured in FIG. 14 fitted;
  • FIG. 18 is an enlargement of the sectional view of the semiconductor device test apparatus in FIG. 17;
  • FIG. 19 is a perspective illustrating the structure of the semiconductor device test apparatus in an eighth embodiment
  • FIG. 20 is a plan view of a wafer to be measured that may be tested by the semiconductor device test apparatus illustrated in FIG. 19;
  • FIG. 21 is a sectional view of a CSP device obtained from the wafer to be measured in FIG. 20;
  • FIG. 22 is a sectional view illustrating the semiconductor device test apparatus in FIG. 19 immediately before the wafer to be measured in FIG. 20 is fitted;
  • FIG. 23 is a sectional view illustrating the semiconductor device test apparatus in FIG. 19 with the wafer to be measured in FIG. 20 fitted;
  • FIG. 24 is an enlargement of the sectional view of the semiconductor device test apparatus in FIG. 23;
  • FIG. 25 is a perspective illustrating the structure of the semiconductor device test apparatus in a ninth embodiment
  • FIG. 26 is an enlargement of the sectional view of the semiconductor device test apparatus in FIG. 25;
  • FIG. 27 is a plan view of an IC chip that may be tested by using the semiconductor device test apparatus in FIG. 25;
  • FIG. 28 is a sectional view illustrating a state in which the IC chip in FIG. 27 is in contact with the semiconductor device test apparatus illustrated in FIG. 25;
  • FIG. 29 is a sectional view illustrating the connections among a device to be measured, an IC socket and a circuit board in the prior art
  • FIG. 30 is a perspective of the device to be measured in FIG. 29, illustrating its surface where electrodes are formed;
  • FIG. 31 is a plan view of a circuit board with the devices to be measured and the IC sockets in FIG. 29 mounted;
  • FIG. 32 is a plan view of a probe card 13 provided with probes of the prior art
  • FIG. 33 is a sectional view illustrating a stale in which the wafer is in contact with the probes provided at the probe card illustrated in FIG. 32.
  • a semiconductor device test apparatus e 1 in the first embodiment of present invention adopts a structure that includes a circuit board 103 , a film 105 , a positioning plate 107 and a holding plate 109 .
  • the circuit board 103 which is connected to peripheral devices (not shown) via connection terminals 103 a and 103 b , enables input and output of various types of electrical signals and a source voltage.
  • the circuit board 103 may be constituted of, for instance, a multilayer substrate.
  • the film 105 , the positioning plate 107 and the holding plate 109 are respectively provided with reference holes 105 a , 107 a and 109 a at the four corners, and they are secured onto the circuit board 103 by pins 111 .
  • the positioning plate 107 is provided with a plurality of through holes 107 b constituting positioning members so that it can align devices to be measured 201 .
  • the through holes 107 b are formed in a shape that corresponds to the external shape of the devices to be measured 201 .
  • FIG. 2 is a sectional view illustrating the semiconductor device test apparatus e 1 in the first embodiment and a plurality of devices to be measured 201 fitted at the semiconductor device test apparatus e 1 for the purpose of various types of functional tests.
  • the devices to be measured 201 are each inserted at a through hole 107 b at the positioning plate 107 and are held against the film 105 by the holding plate 109 .
  • a buffer member 113 is provided between each device to be measured 201 and the holding plate 109 to ensure that the pressure from the holding plate 109 is distributed to the individual devices to be measured 201 evenly and correctly.
  • the film 105 is held against the circuit board 103 with the pressure applied by the holding plate 109 .
  • FIG. 3 is an enlargement of FIG. 2.
  • a plurality of electrodes 103 c are formed at positions that face opposite a plurality of electrodes 201 a at the device to be measured 201 .
  • Bumps 105 b are formed at the surface of the film 105 located toward the device to be measured 201 , at positions that face opposite the plurality of electrodes 201 a at the device to be measured 201 .
  • These bumps 105 b which are terminals capable of supplying source voltage and inputting/outputting various types of electrical signals, are each formed in a semi-spherical shape through electrolytic plating. They may be constituted of, for instance, copper, with their surfaces processed in a gold plating treatment. Alternatively, instead of the bumps, projections may be formed through etching.
  • Electrodes (lands) 105 c are formed at the surface of the film 105 located toward the circuit board 103 , at positions facing opposite the plurality of electrodes 103 c at the circuit board 103 .
  • the bumps 105 b and the electrodes 105 c formed at different surfaces of the film 105 are electrically connected via through holes 105 d.
  • the various types of electrical signals output by the devices to be measured 201 travel through the bumps 105 b and the electrodes 105 c formed at the film 105 , are taken into the circuit board 103 via the electrodes 103 c and are further sent out to the peripheral devices.
  • the semiconductor device test apparatus e 1 in the first embodiment which is provided with the positioning plate 107 capable of aligning a plurality of devices to be measured 201 in a batch, does not require an IC socket to be provided for each device to be measured 201 .
  • the expense of providing IC sockets is eliminated.
  • FIG. 4 is a sectional view illustrating a semiconductor device test apparatus e 2 in the second embodiment of the present invention and a plurality of devices to be measured 201 that are fitted at the semiconductor device test apparatus e 2 for the purpose of various types of functional tests.
  • the semiconductor device test apparatus e 2 in the second embodiment adopts a structure which is achieved by replacing the film 105 in the semiconductor device test apparatus e 1 in the first embodiment with a printed board 115 , as illustrated in FIG. 4.
  • the devices to be measured 201 are each inserted at a through hole 107 b at the positioning plate 107 and are held against the printed board 115 by the holding plate 109 .
  • a buffer member 113 is provided between each device to be measured 201 and the holding plate. 109 to ensure that the pressure from the holding plate 109 is distributed to the individual devices to be measured 201 evenly and correctly.
  • the printed board 115 is held against the circuit board 103 with the pressure applied by the holding plate 109 .
  • FIG. 5 is an enlargement of FIG. 4.
  • Bumps 115 b are formed at the surface of the printed board 115 located toward the device to be measured 201 , at positions that face opposite the plurality of electrodes 201 a at the device to be measured 201 .
  • These bumps 115 b which are terminals capable of supplying the source voltage and inputting/outputting various, types of electrical signals, are each formed in a semi-spherical shape through electrolytic plating. They may be constituted of, for instance, copper, with their surfaces processed in a gold plating treatment. Alternatively, instead of the bumps, projections may be formed through etching.
  • Electrodes (lands) 115 c are formed at the surface of the printed board 115 located toward the circuit board 103 , at positions facing opposite the plurality of electrodes 103 c at the circuit board 103 .
  • the bumps 115 b and the electrodes 115 c formed at different surfaces of the printed board 115 are electrically connected via through holes 115 d.
  • the various types of electrical signals output by the devices to be measured 201 travel through the bumps 115 b and the electrodes 115 c formed at the printed board 115 , are taken into the circuit board 103 via the electrodes 103 c and are further sent out to the peripheral devices.
  • the semiconductor device test apparatus e 2 in the second embodiment achieves advantages similar to those achieved by the semiconductor device test apparatus e 1 in the first embodiment.
  • the semiconductor device test apparatus e 2 in the second embodiment which is provided with the printed board 115 to electrically connect the devices to be measured 201 and the circuit board 103 achieves a reduction in cost relative to the semiconductor device test apparatus e 1 in the first embodiment provided with the film 105 .
  • a semiconductor device test apparatus e 3 in the third embodiment of the present invention assumes a structure that includes the circuit board 103 , the printed board 115 , the positioning plate 107 , the holding plate 109 and the buffer member 113 that constitute the semiconductor device test apparatus e 2 in the second embodiment, as illustrated in FIG. 6.
  • the circuit board 103 , the printed board 115 and the positioning plate 107 are integrated to constitute a first unit 121 , and the holding plate 109 and the buffer member 113 are integrated to constitute a second unit 122 .
  • the devices to be measured 201 are each housed inside a device-securing portion 121 a which is created by a through hole 107 b at the positioning plate 107 constituting the first unit 121 .
  • the devices to be measured 201 are pressed down by the second unit 122 to be electrically connected with the printed board 115 constituting the first unit 121 .
  • the printed board 115 is already electrically connected with the circuit board 103 , electrical signals output by the peripheral devices and the source voltage are provided to the devices to be measured 201 , and the electrical signals output by the devices to be measured 201 are communicated to the peripheral devices.
  • the semiconductor device test apparatus e 3 in the third embodiment achieves advantages similar to those achieved by the semiconductor device test apparatus e 2 in the second embodiment.
  • the semiconductor device test apparatus e 3 in the third embodiment is constituted of the first unit 121 achieved by integrating the circuit board 103 , the printed board 115 and the positioning plate 107 and the second unit 122 achieved by integrating the holding plate 109 and the buffer members 113 , it is not necessary to assemble the circuit board 103 , the printed board 115 , the positioning plate 107 , the holding plate 109 and the buffer members 113 to test the devices to be measured 201 and consequently, functional tests can be conducted on the devices to be measured by taking a procedure similar to that adopted when conducting functional tests using IC sockets in the prior art. Consequently, a higher degree of efficiency is achieved in functional tests and a reduction in the cost of the tests is achieved.
  • the printed board 115 may be replaced by the film 105 provided in the semiconductor device test apparatus e 1 in the first embodiment.
  • a semiconductor device test apparatus e 4 in the fourth embodiment of the present invention assumes a structure that includes the circuit board 103 , a film 106 , a rubber sheet 131 , the positioning plate, 107 and the holding plate 109 as illustrated in FIG. 7. Namely, the semiconductor device test apparatus e 4 in the fourth embodiment assumes a structure achieved by replacing the film 105 in the semiconductor device test apparatus e 1 in the first embodiment with the film 106 and by adding the rubber sheet 131 .
  • the film 106 and the rubber sheet 131 are respectively provided with reference holes 106 a and 131 a at the four corners and they are secured onto the circuit board 103 together with the positioning plate 107 and the holding plate 109 by the pins 111 .
  • FIG. 7 shows a device to be measured 202 .
  • the devices to be measured 202 are CSP devices, and in addition, they each constitute a BGA (ball grid array).
  • the positioning plate 107 is provided with a plurality of through holes 107 b constituting positioning portions to enable positioning of the devices to be measured 202 .
  • the through holes 107 b are shaped to conform with the external shape of the devices to be measured 202 .
  • FIG. 8 is a sectional view illustrating the semiconductor device test apparatus e 4 in the fourth embodiment and a plurality of devices to be measured 202 fitted at the semiconductor device test apparatus e 4 for the purpose of various types of functional tests.
  • the devices to be measured 202 are each inserted at a through hole 107 b at the positioning plate 107 and are held against the rubber sheet 131 by the holding plate 109 .
  • a buffer member 113 is provided between each device to be measured 202 and the holding plate 109 to ensure that the pressure from the holding plate 109 is distributed to the individual devices to be measured 202 evenly and correctly.
  • the rubber sheet 131 is held against the film 106 with the pressure applied by the holding plate 109 and the film 106 is held against the circuit board 103 .
  • FIG. 9 is an enlargement of FIG. 8.
  • the device to be measured 202 which is a BGA as explained earlier, is provided with the plurality of solder balls constituting electrodes 202 a.
  • a plurality of electrodes 103 c are formed at positions that face opposite a plurality of electrodes 202 a at the device to be measured 202 .
  • Electrodes 106 b are formed at the surface of the film 106 located toward the rubber sheet 131 .
  • electrodes 106 c are firmed at positions facing opposite the plurality of electrodes 103 c at the circuit board 103 .
  • the electrodes 106 b and the electrodes 106 c formed at different surfaces of the film 106 are electrically connected via through holes 106 d.
  • the rubber sheet 131 is provided with anisotropic conductive rubber portions 131 b at positions facing opposite the electrodes 106 b at the film 106 and the electrodes 202 a at the device to be measured 202 .
  • various types of electrical signals output by the peripheral devices and the source voltage are provided to the devices to be measured 202 to electrically drive the devices to be measured 202 .
  • the various types of electrical signals output by the devices to be measured 202 travel through the anisotropic conductive rubber portions 131 b embedded in the rubber sheet 131 and the electrodes 106 b and 106 c formed at the film 106 to be taken into the circuit board 103 via the electrodes 103 c and are further sent out to the peripheral devices.
  • the semiconductor device test apparatus e 4 in the fourth embodiment which is provided with the positioning plate 107 capable of aligning the plurality of devices to be measured 202 in a batch, does not require an IC socket to be provided for each device to be measured 202 .
  • the expense of providing IC sockets is eliminated.
  • a larger number of devices to be measured 202 can be mounted at the circuit board 103 so that even more devices to be measured can be tested in a single functional test.
  • the semiconductor device test apparatus e 4 in the fourth embodiment which is provided with the rubber sheet 131 that achieves elasticity and at the same time enables electrical connection only in the thicknesswise direction, the electrodes 202 a formed at the devices to be measured 202 do not become deformed.
  • the anisotropic conductive rubber portions 131 b provided at the rubber sheet 131 come in contact with the ball-shaped electrodes 202 a provided at the devices to be measured 202 over a larger area due to their elasticity.
  • the semiconductor device test apparatus e 4 in the fourth embodiment is employed, the individual devices to be measured 202 achieve reliable electrical connection with the peripheral devices to enable functional tests to be performed with a higher degree of accuracy.
  • FIG. 10 is a sectional view illustrating a semiconductor device test apparatus e 5 in the fifth embodiment of the present invention and a plurality of devices to be measured 202 that are fitted at the semiconductor device test apparatus e 5 for the purpose of various types of functional tests.
  • the semiconductor device test apparatus e 5 in the fifth embodiment adopts a structure which is achieved by replacing the film 106 in the semiconductor device test apparatus e 4 in the fourth embodiment with a printed board 116 , as illustrated in FIG. 10.
  • the devices to be measured 202 are each inserted at a through hole 107 b at the positioning plate 107 and are held against the rubber sheet 131 by the holding plate 109 .
  • a buffer member 113 is provided between each device to be measured 202 and the holding plate 109 to ensure that the pressure from the holding plate 109 is distributed to the individual devices to be measured 202 evenly and correctly.
  • the rubber sheet 131 is held against the printed board 116 with the pressure applied by the holding plate 109 and the printed board 116 is held against the circuit board 103 .
  • FIG. 11 is an enlargement of FIG. 10.
  • Electrodes 116 b are formed at the surface of the printed board 116 located toward the rubber sheet 131 .
  • electrodes 116 c are formed at positions facing opposite the plurality of electrodes 103 c at the circuit board 103 .
  • the electrodes 116 b and the electrodes 1 16 c formed at different surfaces of the printed board 116 are electrically connected via through holes 116 d.
  • the rubber sheet 131 is provided with anisotropic conductive rubber portions 131 b at positions facing opposite the electrodes 116 b at the printed board 116 and the electrodes 202 a at the device to be measured 202 .
  • the electrodes 103 c are electrically connected with the anisotropic conductive rubber portions 131 b embedded in the rubber sheet 131 via the electrodes 116 c and the electrodes 116 b formed at the printed board 111 .
  • the anisotropic conductive rubber portions 131 b are electrically connected with the electrodes 202 a formed at the devices to be measured 202 .
  • various types of electrical signals output by the peripheral devices and the source voltage are provided to the devices to be measured 202 to electrically drive the devices to be measured 202 .
  • the various types of electrical signals output by the devices to be measured 202 travel through the anisotropic conductive rubber portions 131 b embedded in the rubber sheet 131 and the electrodes 116 b and 116 c formed at the printed board 116 to be taken into the circuit board 103 via the electrodes 103 c and are further sent out to the peripheral devices.
  • the semiconductor device test apparatus e 5 in the fifth embodiment achieves advantages similar to those achieved by the semiconductor device test apparatus e 4 in the fourth embodiment.
  • a semiconductor device test apparatus e 6 in the sixth embodiment of the present invention assumes a structure that includes the circuit board 103 , the printed board 116 , the rubber sheet 131 , the positioning plate 107 , the holding plate 109 and the buffer members 113 that constitute the semiconductor device test apparatus e 5 in the fifth embodiment, as illustrated in FIG. 12.
  • the circuit board 103 , the printed board 116 , the rubber sheet 131 and the positioning plate 107 are integrated to constitute a first unit 141
  • the holding plate 109 and the buffer members 113 are integrated to constitute a second unit 142 .
  • the devices to be measured 202 are each housed inside a device-securing portion 141 a which is created by a through hole 107 b at the positioning plate 107 constituting the first unit 141 .
  • the devices to be measured 202 are pressed down by the second unit 142 to be electrically connected with the rubber sheet 131 constituting the first unit 141 .
  • the rubber sheet 131 is already electrically connected with the printed board 116 and the printed board 116 is already electrically connected with the circuit board 103 , consequently, the electrical signals output by the peripheral devices and the source voltage are provided to the devices to be measured 202 , and the electrical signals output by the devices to be measured 202 are communicated to the peripheral devices.
  • the semiconductor device test apparatus e 6 in the sixth embodiment achieves advantages similar to those achieved by the semiconductor device test apparatus e 5 in the fifth embodiment.
  • the semiconductor device test apparatus e 6 in the sixth embodiment is constituted of the first unit 141 achieved by integrating the circuit board 103 , the printed board 116 , the rubber sheet 131 and the positioning plate 107 and the second unit 142 achieved by integrating the holding plate 109 and the buffer members 113 , it is not necessary to assemble the circuit board 103 , the printed board 116 , the rubber sheet 131 , the positioning plate 107 , the holding plate 109 and the buffer members 113 to test the devices to be measured 202 and consequently, functional tests can be conducted on the devices to be measured 202 by taking a procedure similar to that adopted when conducting functional tests using IC sockets in the prior art. Consequently, a higher degree of efficiency is achieved in functional tests and a reduction in the cost of the tests is achieved.
  • the printed board 116 may be replaced by the film 106 provided in the semiconductor device test apparatus e 4 in the fourth embodiment.
  • a semiconductor device test apparatus e 7 in the seventh embodiment of the present invention assumes a structure that includes a circuit board 303 , a film 305 , a positioning plate 307 and a holding plate 309 .
  • the circuit board 303 is connected to peripheral devices (not shown) through connection terminals 303 a and 303 b to enable input and output of various types of electrical signals and a source voltage.
  • the circuit board 303 may be constituted of, for instance, a multilayer substrate.
  • the film 305 , the positioning plate 307 and the holding plate 309 are respectively provided with reference holes 305 a , 307 a and 309 a at the four corners, and are secured onto the circuit board 303 with pins 311 .
  • the positioning plate 307 is provided with a through hole 307 b constituting a positioning member to enable positioning of a wafer to be measured 401 .
  • the through hole 307 b is formed in a shape that conforms with the external shape of the wafer to be measured 401 .
  • a plurality of ventilating through holes 309 b are formed at the holding plate 309 . This makes it possible to expose the wafer to be measured 401 to the air that circulates through convection when, for instance, a burn-in is implemented on the wafer to be measured 401 . It is to be noted that for applications other than bum-in, the ventilating through holes 309 b may be omitted.
  • FIG. 15 is a sectional view of a CSP device 411 along line A-A′ in FIG. 14.
  • a plurality of electrodes 411 b are provided at the surface of a device body 411 a .
  • the electrodes 411 b are land type (LGA) electrodes with flat surfaces.
  • FIG. 16 is a sectional view illustrating the semiconductor device test apparatus e 7 in the seventh embodiment and the wafer to be measured 401 immediately before the wafer to be measured 401 is mounted at the semiconductor device test apparatus e 7 for the purpose of various types of functional tests.
  • a buffer member 313 is provided at the holding plate 309 at a position that faces opposite the wafer to be measured 401 .
  • the wafer to be measured 401 is mounted at the semiconductor device test apparatus e 7 in the seventh embodiment as illustrated in FIG. 17.
  • the wafer to be measured 401 is inserted at the through hole 307 b at the positioning plate 307 and is pressed against the film 305 by the holding plate 309 .
  • the pressure from the holding plate 309 is distributed evenly and correctly to the wafer to be measured 401 by the buffer member 313 provided at the holding plate 309 .
  • the film 305 is held onto the circuit board 303 by the pressure from the holding plate 309 .
  • FIG. 18 is an enlargement of FIG. 17.
  • a plurality of electrodes 303 c are formed at positions that face opposite the plurality of electrodes 411 b at the wafer to be measured 401 .
  • Bumps 305 b are formed at the surface of the film 305 located toward the wafer to be measured 401 , at positions that face opposite the plurality of electrodes 411 b at the wafer to be measured 401 .
  • These bumps 305 b which are terminals capable of supplying source voltage and inputting/outputting various types of electrical signals, are each formed in a semi-spherical shape through electrolytic plating. They may be constituted of, for instance, copper, with their surfaces processed in a gold plating treatment. Alternatively, instead of the bumps, projections may be formed through etching.
  • Electrodes (lands) 305 c are formed at the surface of the film 305 located toward the circuit board 303 , at positions facing opposite the plurality of electrodes 303 c at the circuit board 303 .
  • the bumps 305 b and the electrodes 305 c formed at different surfaces of the film 305 are electrically connected via through holes 305 d.
  • the various types of electrical signals output by the wafer to be measured 401 travel through the bumps 305 b and the electrodes 305 c formed at the film 305 , are taken into the circuit board 303 via the electrodes 303 c and are further sent out to the peripheral devices.
  • the semiconductor device test apparatus e 7 in the seventh embodiment enables various types of functional tests to be conducted at the wafer level without dividing the wafer into chips.
  • the necessity for providing IC sockets for individual chips is eliminated to eliminate the cost of IC sockets.
  • a semiconductor device test apparatus e 8 in the eighth embodiment of the present invention assumes a structure that includes the circuit board 303 , a film 306 , a rubber sheet 331 , the positioning plate 307 and the holding plate 309 as illustrated in FIG. 19.
  • the semiconductor device test apparatus e 8 in the eighth embodiment assumes a structure achieved by replacing the film 305 in the semiconductor device test apparatus e 7 in the seventh embodiment with the film 306 and adding the rubber sheet 331 .
  • the film 306 and the rubber sheet 331 are respectively provided with reference holes 306 a and 331 a at the four corners and they are secured onto the circuit board 303 together with the positioning plate 307 and the holding plate 309 by the pins 311 .
  • the positioning plate 307 is provided with a through hole 307 b constituting a positioning member to enable positioning of a wafer to be measured 402 .
  • the through hole 307 b is formed in a shape that conforms with the external shape of the wafer to be measured 402 .
  • the wafer to be measured 402 which is to undergo various types of functional tests conducted by using the semiconductor device test apparatus e 8 in the eighth embodiment is explained in reference to FIG. 20.
  • FIG. 21 is a sectional view of a CSP device 412 along line B-B′ in FIG. 20.
  • a plurality of electrodes 412 b are provided at the surface of a device body 412 a .
  • the electrodes 412 b are ball-type electrodes, and the CSP devices 412 are formed as BGAs.
  • FIG. 22 is a sectional view illustrating the semiconductor device test apparatus e 8 in the eighth embodiment and the wafer to be measured 402 immediately before the wafer to be measured 402 is mounted at the semiconductor device test apparatus e 8 for the purpose of various types of functional tests.
  • a buffer member 313 is provided at the holding plate 309 at a position that faces opposite the wafer to be measured 402 .
  • the wafer to be measured 402 is fitted at the semiconductor device test apparatus e 8 in the eighth embodiment as illustrated in FIG. 23.
  • the wafer to be measured 402 is inserted at the through hole 307 b at the positioning plate 307 and is held against the rubber sheet 331 by the holding plate 309 .
  • the pressure from the holding plate 309 is distributed evenly and correctly to the wafer to be measured 402 by the buffer member 313 provided at the holding plate 309 .
  • the rubber sheet 331 is held against the film 306 with the pressure applied by the holding plate 309 and the film 306 is held against the circuit board 303 .
  • the wafer to be measured 402 which is a BGA as explained earlier, is provided with a plurality of solder balls constituting electrodes 412 b.
  • a plurality of electrodes 303 c are formed at positions that face opposite a plurality of electrodes 412 b at the wafer to be measured 402 .
  • Electrodes 306 b are formed at the surface of the film 306 located toward the rubber sheet 331 .
  • electrodes 306 c are formed at positions facing opposite the plurality of electrodes 303 c at the circuit board 303 .
  • the electrodes 306 b and the electrodes 306 c formed at different surfaces of the film 306 are electrically connected via through holes 306 d.
  • the rubber sheet 331 is provided with anisotropic conductive rubber portions 331 b at positions facing opposite the electrodes 306 b at the film 306 and the electrodes 412 b at the wafer to be measured 402 .
  • various types of electrical signals output by the peripheral devices and the source voltage are provided to the wafer to be measured 402 to electrically drive the wafer to be measured 402 .
  • the various types of electrical signals output by the wafer to be measured 402 travel through the anisotropic conductive rubber portions 331 b embedded in the rubber sheet 331 and the electrodes 306 b and 306 c formed at the film 306 to be taken into the circuit board 303 via the electrodes 303 c and are further sent out to the peripheral devices.
  • the semiconductor device test apparatus e 8 in the eighth embodiment achieves advantages similar to those achieved by semiconductor device test apparatus e 7 in the seventh embodiment.
  • the semiconductor device test apparatus e 8 in the eighth embodiment which is provided with the rubber sheet 331 that achieves elasticity and at the same time enables electrical connection only in the thicknesswise direction, the electrodes 412 b formed at the wafer to be measured 402 do not become deformed.
  • the anisotropic conductive rubber portions 331 b provided at the rubber sheet 331 come in contact with the ball-shaped electrodes 412 b provided at the wafer to be measured 402 over a larger area due to their elasticity.
  • the semiconductor device test apparatus e 8 in the eighth embodiment is employed, the wafer to be measured 402 achieve reliable electrical connection with the peripheral devices to enable functional tests to be performed at a higher degree of accuracy.
  • a semiconductor device test apparatus e 9 in the ninth embodiment of the present invention adopts a structure that includes a circuit board 503 , probes 511 , a probe sheet 521 and a rubber sheet 531 , as illustrated in FIG. 25.
  • the circuit board 503 is connected to peripheral devices (not shown) to allow input and output of various types of electrical signals and a source voltage.
  • the probes 511 are constituted of tungsten or beryllium copper.
  • contact portions 511 a of the probes 511 where they come in contact with the rubber sheet 531 are clad with gold plate to prevent oxidation and to assure good contact. It is to be noted that the gold-plating treatment is not restricted to be implemented on the contact portions 511 a only, and may be implemented over the entire surfaces of the probes 511 .
  • the probe sheet 521 may be constituted of a rubber sheet having a heat resistant property or a membrane sheet formed from glass fiber/polyimide.
  • the probes 511 are embedded in the probe sheet 521 , and are each provided with notches 511 b as illustrated in FIG. 26 to ensure that they do not slip out of the probe sheet 521 .
  • the rubber sheet 531 is provided with anisotropic conductive rubber portions 531 a to electrically connect a plurality of electrodes 503 a formed at the circuit board 503 and the contact portions 511 a at the plurality of probes 511 .
  • FIG. 27 An IC chip 601 formed in one partitioned area of the wafer to be measured is illustrated in FIG. 27.
  • the IC chip 601 is provided with a plurality of pads 601 a .
  • the pads 601 a will be constituted of aluminum.
  • the entire area of the IC chip 601 where the pads 601 a are not present is protected from the outside atmosphere by a resist film 601 b.
  • the individual probes 511 are placed in contact with the corresponding pads 601 a as illustrated in FIG. 28. As described above, since no resist film 601 b is formed at the pads 601 a , the pads 601 a and the probes 511 become electrically connected.
  • various types of electrical signals output by the IC chip 601 travel through the probes 511 and the anisotropic conductive rubber portions 531 a provided at the rubber sheet 531 to be taken into the circuit board 503 via the electrodes 503 a and they are then sent out to the peripheral devices.
  • the semiconductor device test apparatus e 9 in the ninth embodiment provided with the probes 511 , which are constituted of tungsten or beryllium copper and are placed in contact with the object of testing, durability against contact is achieved that is comparable to that of a probe card 13 in the prior art.
  • the semiconductor device test apparatus e 9 in the ninth embodiment may be employed in a product inspection process as well as in functional tests conducted during the semiconductor device development stage.
  • the semiconductor device test apparatus e 9 which assumes a structure in which the front ends of the probes 511 are placed in contact with the object of testing in a perpendicular attitude, is capable of supporting a finer pitch of the pads at the object of testing (eg. an electrode pitch of 0.5 mm or smaller).
  • a finer pitch of the pads at the object of testing eg. an electrode pitch of 0.5 mm or smaller.
  • the probes 511 may be embedded in the probe sheet 521 through an automated process to achieve a low production cost for mass production.
  • the semiconductor device test apparatus e 9 in the ninth embodiment may be combined with a wafer-level test/burn-in apparatus. This will make it possible to reduce the level of investment in the tester employed in tests on finished semiconductor device products, which ultimately leads to reductions in the test cost and the device cost.

Abstract

A semiconductor device test apparatus according to the present invention includes a circuit board 103 and a film 105. A plurality of electrodes 103 c are formed at the circuit board 103 at positions that face opposite a plurality of electrodes 201 a at a device to be measured 201, whereas bumps 105 b are formed at the surface of the film 105 located toward the device to be measured 201, at positions that face opposite the plurality of electrodes 201 a at the device to be measured 201 and electrodes 105 c are formed at the surface of the film 105 located toward the circuit board 103 at positions that face opposite the plurality of electrodes 103 c at the circuit board 103. The bumps 105 b formed at one surface of the film 105 and the electrode 105 c formed at another surface of the film 105 are electrically connected with each other via through holes 105 d to support semiconductor devices having electrodes provided at a fine pitch and to improve durability.

Description

    BACKGROUND OF THE INVENTION
  • The present invention relates to a semiconductor device test apparatus. [0001]
  • An IC socket which matches the shape of the device to be measured is employed to test a newly developed device in the prior art. An IC socket, which comes into electrical contact with the device to be measured, fulfills a function as a means for electrical signal communication between a peripheral device and the device to be measured. [0002]
  • Now, the IC socket, the device to be measured and the connection between the IC socket and the device to be measured are explained in reference to FIGS. 29, 30 and [0003] 31.
  • FIG. 29 is a sectional view of a device to be measured [0004] 1 and an IC socket 3 mounted at a circuit board 5, illustrating the connections among them. The IC socket 3 is provided with a plurality of contacts 3 a, and is soldered onto the circuit board 5 at the contacts 3 a. The device to be measured 1, which is pressed down by a holding member 7, is electrically connected with the contacts 3 a of the IC socket 3.
  • FIG. 30 is a perspective of the device to be measured [0005] 1, showing its surface on which electrodes are formed. The device to be measured 1 is a CSP (chip-size package) device achieved through chip size packaging. The device to be measured 1 is provided with a plurality of electrodes 1 a through which electrical signals are input and output and power is supplied. The individual contacts 3 a provided at the IC socket 3 are positioned so that they come in contact with the corresponding electrodes 1 a.
  • FIG. 31 is a plan view of the [0006] circuit board 5 with the devices to be measured 1 and the IC sockets 3 mounted, viewed from above. The circuit board 5 is allowed to engage in electrical signal communication with peripheral devices such as an IC tester and EL bum-in apparatus (not shown) via connection terminals 5 a and 5 b.
  • With the devices to be measured [0007] 1, the IC socket 3 and the circuit board 5 configured as described above, electrical signals input to the circuit board 5 from peripheral devices via the connection terminals 5 a and 5 b and a source voltage travel through the contacts 3 a of the IC socket 3 to be supplied to the devices to be measured 1 through the electrodes la. In addition, electrical signals output by the devices to be measured 1 travel through the reverse route to reach the peripheral devices. Such electrical connection enable functional tests on the devices 1 to be measured.
  • Apart from functional tests achieved by employing IC sockets as described above, a functional test on a wafer-level device, in particular, is implemented by adopting a method whereby probes are placed in contact with wafer pads constituting signal input/output electrodes and source electrodes of the device. [0008]
  • Since the wafer and the probes are placed in contact a great number of times in such functional tests employing probes, the contact durability of the probe is a critical concern. If the contact durability of the probes is poor, the cost of the functional test is bound to increase, raising the price of the device itself. For this reason, probes are normally constituted of materials with a high degree of hardness such as tungsten and beryllium copper. [0009]
  • FIG. 32 illustrates a [0010] probe card 13 provided with probes 11. At the probe card 13, a specific circuit that corresponds to the device to be measured is printed, and electrical signal communication with peripheral devices (not shown) is enabled via connection terminals 13 a and 13 b.
  • The positional relationship between a [0011] probe card 13 and the wafer 15 which constitutes the device to be measured is illustrated in FIG. 33. Electrical signals provided by a peripheral device are input to the probe card 13 via the connection terminals 13 a and 13 b, travel through the circuit formed at the probe card 13 to reach the probe 11. Then, the electrical signals are applied to the pads formed at the wafer 15 from the probe 11. In addition, electrical signals output by the wafer 15 travel through the reverse route to reach a peripheral device. The structure described above enables a functional test on the wafer 15.
  • However, the following problems are yet to be addressed in functional tests conducted by utilizing IC sockets and functional tests conducted by utilizing probes. [0012]
  • The smallest pitch for contacts at an IC socket is currently 0.65 mm. At the same time, the package size has been reduced in recent years, with the CSP being a typical example, and as a result, the electrode pitch at the device has been switched from 1.27 mm to 0.8 mm or 0.5 mm. This reduction in the electrode pitch at the device necessitates a reduction in the pitch of the contacts at the IC socket. [0013]
  • However, in order to reduce the contact pitch at an IC socket to 0.65 mm or smaller, the IC socket machining accuracy must be improved. This will inevitably raise the production cost of the IC socket, and may result in a large increase in the device price. [0014]
  • In addition, the body size of IC sockets imposes a restriction upon the number of IC sockets that can be mounted at a circuit board. Such restriction on the number of IC sockets that can be mounted at the circuit board ultimately restricts the number of devices that can be tested in a single functional test. Thus, functional tests conducted on devices utilizing IC sockets in the prior art are not always efficient. [0015]
  • In order to achieve a higher degree of efficiency in functional tests conducted by employing probes, it is desirable to increase the number of probes mounted at a probe card so that many devices can be tested at once. However, probes are secured to the probe card using a resin or the like in the prior art, which requires a large space for securing them. Thus, it is difficult to increase the number of probes without increasing the probe card size. [0016]
  • Furthermore, as higher integration of devices becomes more common, the pitch of the device pads with which probes come in contact is becoming narrower. This reduction in the pad pitch necessitates a reduction in the pitch of probes mounted at the probe card. However, it is difficult to reduce the probe pitch in the structure adopted in the prior art. [0017]
  • SUMMARY OF THE INVENTION
  • An object of the present invention, which has been completed by addressing the problems of the prior art discussed above, is to provide a semiconductor device test apparatus that can be employed to test semiconductor devices with electrodes provided at a fine pitch and also achieves a high degree of durability. Another object of the present invention is to provide a semiconductor device test apparatus that is capable of batch testing a great number of semiconductor devices. [0018]
  • In order to achieve the objects described above, according to the present invention, a semiconductor device test apparatus that is capable of testing one or a plurality of semiconductor devices each provided with a plurality of electrodes. The semiconductor device test apparatus according to the present invention is characterized in that it is provided with a circuit board having a circuit that corresponds to the semiconductor device and a plurality of electrodes that correspond to individual electrodes at the semiconductor device and a connection plate that is provided with a plurality of conductive portions that electrically connect the individual electrodes at the semiconductor device and the individual electrodes at the circuit board on a one-to-one basis. This structure allows the semiconductor device to be electrically connected to the circuit board via the connection plate. The semiconductor device can be driven by inputting various types of electrical signals to the circuit board from peripheral devices, and various types of electrical signals output by the semiconductor device are communicated to the peripheral devices. In addition, by providing the connection plate having a plurality of conductive portions provided to electrically connect the individual electrodes at the semiconductor device and the individual electrodes at the circuit board, an extremely simple structure is realized for the apparatus. [0019]
  • The conductive portions are each formed at one of a plurality of through holes provided at the connection plate. Even when electrodes at the semiconductor device are arrayed over an extremely fine pitch, the semiconductor device can be tested with ease by reducing the electrode pitch at the circuit board and reducing the through hole pitch. [0020]
  • A conductive elastic body that electrically connects the individual conductive portions at the connection plate and the individual electrodes at the semiconductor device on a one-to-one basis is provided between the connection plate and the semiconductor device. By adopting this structure, the pressure applied by the conductive portions at the connection plate to the individual electrodes at the semiconductor device when they are electrically connected with each other is reduced. The structure may be effectively adopted when, for instance, the electrodes at the semiconductor device are ball-type electrodes. [0021]
  • Furthermore, a positioning member that secures the semiconductor device may be provided. This positioning member may be constituted of a plate member having a through portion formed that corresponds to the shape of the semiconductor device, for instance. Such a configuration will allow the semiconductor device to be secured through an extremely simple structure. In addition, the space required to secure the semiconductor device can be reduced. [0022]
  • Moreover, the circuitboard, the connection plate and the positioning member may be provided as an integrated unit, or the circuitboard, the connection plate, the conductive elastic body and the positioning member may be provided as an integrated unit. Such a structure eliminates the necessity for assembling the circuit board, the connection plate and the positioning member when testing the semiconductor device, to achieve a higher degree of efficiency in testing. [0023]
  • By providing a holding member that presses the semiconductor device toward the connection plate, the position of the semiconductor device becomes fixed and more reliable electrical connection is achieved for the semiconductor device and the circuit board. [0024]
  • It is desirable to provide a buffer member at the location where the holding member is in contact with the semiconductor device. By providing such a buffer member, the pressure applied from the holding member is distributed evenly and correctly at the semiconductor device. [0025]
  • By using film to constitute the connection plate, an extremely thin connection plate is realized. In addition, since the connection plate constituted of film can bend freely, more reliable electrical connection between the individual electrodes at the semiconductor device and the individual electrodes at the circuit board is assured. [0026]
  • Alternatively, a printed board may be used to constitute the connection plate. By adopting such a printed board, the production cost can be reduced compared to the cost of production using film. [0027]
  • In addition, according to the present invention, a semiconductor device test apparatus employed to test one or a plurality of semiconductor devices each having a plurality of electrodes, which is characterized In that it is provided with a probe holding member having a plurality of probes fitted therein so that the individual sharp ends of the plurality of probes corresponding to the individual electrodes at the semiconductor device on a one-to-one basis and the ends of the probes located on the other side of the sharp ends are exposed. By adopting this structure, it becomes possible to mount a plurality of probes while requiring only a small area, so that finer pitches for electrodes at the semiconductor device can be supported. [0028]
  • By forming notched portions in an area located inside the probe holding member, the individual probes can be held by the probe holding member with a high degree of reliability. [0029]
  • In addition, by providing a plurality of conductive elastic portions, each corresponding to one of the probes, the sharp ends of the probes can be placed in contact with the semiconductor device with a high degree of reliability. [0030]
  • It is desirable to form a gold-clad film, at least in areas where the individual probes come into contact with the conductive elastic portions. This gold-clad film will prevent the formation of an oxide film to assure good electrical continuity between the probes and the conductive elastic portions to allow the flow of a very weak current. [0031]
  • Furthermore, according to the present invention, a chip or a wafer may be used as the semiconductor device to be tested.[0032]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other features of the invention and the concomitant advantages will be better understood and appreciated by persons skilled in the field to which the invention pertains in view o the following description given in conjunction with the accompanying drawings which illustrate preferred embodiments. [0033]
  • FIG. 1 is a perspective illustrating the structure of the semiconductors device test apparatus in a first embodiment; [0034]
  • FIG. 2 is a sectional view of the semiconductor device test apparatus in FIG. 1; [0035]
  • FIG. 3 is an enlargement of the sectional view of the semiconductor device test apparatus in FIG. 2; [0036]
  • FIG. 4 is a sectional view illustrating the structure of the semiconductor test apparatus in a second embodiment; [0037]
  • FIG. 5 is an enlargement of the sectional view of the semiconductor device test apparatus in FIG. 4; [0038]
  • FIG. 6 is a sectional view illustrating the structure of the semiconductor test apparatus in a third embodiment; [0039]
  • FIG. 7 is a perspective illustrating the structure of the semiconductor device test apparatus in a fourth embodiment; [0040]
  • FIG. 8 is a sectional view of the semiconductor device test apparatus in FIG. 7; [0041]
  • FIG. 9 is an enlargement of the sectional view of the semiconductor device test apparatus in FIG. 8; [0042]
  • FIG. 10 is a sectional view illustrating the structure of the semiconductor test apparatus in the fifth embodiment; [0043]
  • FIG. 11 is an enlargement of the sectional view of the semiconductor device test apparatus in FIG. 10; [0044]
  • FIG. 12 is a sectional view illustrating the structure of the semiconductor test apparatus in the sixth embodiment; [0045]
  • FIG. 13 is a perspective illustrating the structure of the semiconductor device test apparatus in a seventh embodiment; [0046]
  • FIG. 14 is a plan view of a wafer to be measured that may be tested by the semiconductor device test apparatus illustrated in FIG. 13; [0047]
  • FIG. 15 is a sectional view of a CSP device obtained from the wafer to be measured in FIG. 14; [0048]
  • FIG. 16 is a sectional view illustrating the semiconductor device test apparatus in FIG. 13 immediately before the wafer to be measured in FIG. 14 is fitted; [0049]
  • FIG. 17 is a sectional view illustrating the semiconductor device test apparatus in FIG. 13 with the wafer to be measured in FIG. 14 fitted; [0050]
  • FIG. 18 is an enlargement of the sectional view of the semiconductor device test apparatus in FIG. 17; [0051]
  • FIG. 19 is a perspective illustrating the structure of the semiconductor device test apparatus in an eighth embodiment; [0052]
  • FIG. 20 is a plan view of a wafer to be measured that may be tested by the semiconductor device test apparatus illustrated in FIG. 19; [0053]
  • FIG. 21 is a sectional view of a CSP device obtained from the wafer to be measured in FIG. 20; [0054]
  • FIG. 22 is a sectional view illustrating the semiconductor device test apparatus in FIG. 19 immediately before the wafer to be measured in FIG. 20 is fitted; [0055]
  • FIG. 23 is a sectional view illustrating the semiconductor device test apparatus in FIG. 19 with the wafer to be measured in FIG. 20 fitted; [0056]
  • FIG. 24 is an enlargement of the sectional view of the semiconductor device test apparatus in FIG. 23; [0057]
  • FIG. 25 is a perspective illustrating the structure of the semiconductor device test apparatus in a ninth embodiment; [0058]
  • FIG. 26 is an enlargement of the sectional view of the semiconductor device test apparatus in FIG. 25; [0059]
  • FIG. 27 is a plan view of an IC chip that may be tested by using the semiconductor device test apparatus in FIG. 25; [0060]
  • FIG. 28 is a sectional view illustrating a state in which the IC chip in FIG. 27 is in contact with the semiconductor device test apparatus illustrated in FIG. 25; [0061]
  • FIG. 29 is a sectional view illustrating the connections among a device to be measured, an IC socket and a circuit board in the prior art; [0062]
  • FIG. 30 is a perspective of the device to be measured in FIG. 29, illustrating its surface where electrodes are formed; [0063]
  • FIG. 31 is a plan view of a circuit board with the devices to be measured and the IC sockets in FIG. 29 mounted; [0064]
  • FIG. 32 is a plan view of a [0065] probe card 13 provided with probes of the prior art;
  • FIG. 33 is a sectional view illustrating a stale in which the wafer is in contact with the probes provided at the probe card illustrated in FIG. 32.[0066]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The following is a detailed explanation of the preferred embodiments of the semiconductor device test apparatus according to the present invention, given in reference to the attached drawings. It is to be noted that in the following explanation and the attached drawings, the same reference numbers are assigned to components having practically identical functions and structural features to preclude the necessity for repeating the explanation thereof. [0067]
  • (First Embodiment) [0068]
  • As illustrated in FIG. 1, a semiconductor device test apparatus e[0069] 1 in the first embodiment of present invention adopts a structure that includes a circuit board 103, a film 105, a positioning plate 107 and a holding plate 109.
  • The [0070] circuit board 103, which is connected to peripheral devices (not shown) via connection terminals 103 a and 103 b, enables input and output of various types of electrical signals and a source voltage. The circuit board 103 may be constituted of, for instance, a multilayer substrate.
  • The [0071] film 105, the positioning plate 107 and the holding plate 109 are respectively provided with reference holes 105 a, 107 a and 109 a at the four corners, and they are secured onto the circuit board 103 by pins 111.
  • The [0072] positioning plate 107 is provided with a plurality of through holes 107 b constituting positioning members so that it can align devices to be measured 201. The through holes 107 b are formed in a shape that corresponds to the external shape of the devices to be measured 201.
  • FIG. 2 is a sectional view illustrating the semiconductor device test apparatus e[0073] 1 in the first embodiment and a plurality of devices to be measured 201 fitted at the semiconductor device test apparatus e1 for the purpose of various types of functional tests. The devices to be measured 201 are each inserted at a through hole 107 b at the positioning plate 107 and are held against the film 105 by the holding plate 109. In addition, a buffer member 113 is provided between each device to be measured 201 and the holding plate 109 to ensure that the pressure from the holding plate 109 is distributed to the individual devices to be measured 201 evenly and correctly. Furthermore, the film 105 is held against the circuit board 103 with the pressure applied by the holding plate 109.
  • Now, the connections among the devices to be measured [0074] 201, the film 105 and the circuit board 103 are explained in reference to FIG. 3 which is an enlargement of FIG. 2.
  • At the [0075] circuit board 103, a plurality of electrodes 103 c are formed at positions that face opposite a plurality of electrodes 201 a at the device to be measured 201.
  • Bumps [0076] 105 b are formed at the surface of the film 105 located toward the device to be measured 201, at positions that face opposite the plurality of electrodes 201 a at the device to be measured 201. These bumps 105 b, which are terminals capable of supplying source voltage and inputting/outputting various types of electrical signals, are each formed in a semi-spherical shape through electrolytic plating. They may be constituted of, for instance, copper, with their surfaces processed in a gold plating treatment. Alternatively, instead of the bumps, projections may be formed through etching.
  • Electrodes (lands) [0077] 105 c are formed at the surface of the film 105 located toward the circuit board 103, at positions facing opposite the plurality of electrodes 103 c at the circuit board 103. The bumps 105 b and the electrodes 105 c formed at different surfaces of the film 105 are electrically connected via through holes 105 d.
  • When conducting a functional test on the devices to be measured [0078] 201, various types of electrical signals output by peripheral devices (not shown) and the source voltage are input to the circuit board 103 via the connection terminals 103 a and 103 b, travel through the wiring circuit formed at the circuit board 103 and reach the electrodes 103 c. As illustrated in FIGS. 2 and 3, the electrodes 103 c are electrically connected with the electrodes 201 a formed at the devices to be measured 201 via the electrodes 105 c and the bumps 105 b formed at the film 105. Consequently, various types of electrical signals output by the peripheral devices and the source voltage are provided to the devices to be measured 201 to electrically drive the devices to be measured 201. In addition, the various types of electrical signals output by the devices to be measured 201 travel through the bumps 105 b and the electrodes 105 c formed at the film 105, are taken into the circuit board 103 via the electrodes 103 c and are further sent out to the peripheral devices.
  • When the semiconductor device test apparatus e[0079] 1 in the first embodiment structured as described above, which does not include any contacts formed through machining as an IC sockets 3 in the prior art is adopted, a reduction in the pitch of the plurality of electrodes 201 a formed at each device to be measured 201 can be supported. For instance, even when the pitch of the electrodes 201 a is equal to or less than 0.5 mm, functional tests can be conducted on the devices to be measured 201.
  • In addition, the semiconductor device test apparatus e[0080] 1 in the first embodiment, which is provided with the positioning plate 107 capable of aligning a plurality of devices to be measured 201 in a batch, does not require an IC socket to be provided for each device to be measured 201. Thus, the expense of providing IC sockets is eliminated. In addition, by using the area on the circuit board 103 which is occupied by the body portions of the IC sockets in the prior art; a larger number of devices to be measured 201 can be mounted at the circuit board 103 so that even more devices to be measured can be tested in a single functional test.
  • (Second Embodiment) [0081]
  • FIG. 4 is a sectional view illustrating a semiconductor device test apparatus e[0082] 2 in the second embodiment of the present invention and a plurality of devices to be measured 201 that are fitted at the semiconductor device test apparatus e2 for the purpose of various types of functional tests. The semiconductor device test apparatus e2 in the second embodiment adopts a structure which is achieved by replacing the film 105 in the semiconductor device test apparatus e1 in the first embodiment with a printed board 115, as illustrated in FIG. 4.
  • The devices to be measured [0083] 201 are each inserted at a through hole 107 b at the positioning plate 107 and are held against the printed board 115 by the holding plate 109. In addition, a buffer member 113 is provided between each device to be measured 201 and the holding plate. 109 to ensure that the pressure from the holding plate 109 is distributed to the individual devices to be measured 201 evenly and correctly. Furthermore, the printed board 115 is held against the circuit board 103 with the pressure applied by the holding plate 109.
  • Now, the connections among a device to be measured [0084] 201, the printed board 115 and the circuit board 103 are explained in reference to FIG. 5 which is an enlargement of FIG. 4.
  • [0085] Bumps 115 b are formed at the surface of the printed board 115 located toward the device to be measured 201, at positions that face opposite the plurality of electrodes 201 a at the device to be measured 201. These bumps 115 b, which are terminals capable of supplying the source voltage and inputting/outputting various, types of electrical signals, are each formed in a semi-spherical shape through electrolytic plating. They may be constituted of, for instance, copper, with their surfaces processed in a gold plating treatment. Alternatively, instead of the bumps, projections may be formed through etching.
  • Electrodes (lands) [0086] 115 c are formed at the surface of the printed board 115 located toward the circuit board 103, at positions facing opposite the plurality of electrodes 103 c at the circuit board 103. The bumps 115 b and the electrodes 115 c formed at different surfaces of the printed board 115 are electrically connected via through holes 115 d.
  • When conducting a functional test on the devices to be measured [0087] 201, various types of electrical signals output by peripheral devices (not shown) and the source voltage are input to the circuit board 103 via the connection terminals 103 a and 103 b, travel through the wiring circuit formed at the circuit board 103 and reach the electrodes 103 c. As illustrated in FIGS. 4 and 5, the electrodes 103 c are electrically connected with the electrodes 201 a formed at the devices to be measured 201 via the electrodes 115 c and the bumps 115 b formed at the printed board 115. Consequently, various types of electrical signals output by the peripheral devices and the source voltage are provided to the devices to be measured 201 to electrically drive the devices to be measured 201. In addition, the various types of electrical signals output by the devices to be measured 201 travel through the bumps 115 b and the electrodes 115 c formed at the printed board 115, are taken into the circuit board 103 via the electrodes 103 c and are further sent out to the peripheral devices.
  • As explained above, the semiconductor device test apparatus e[0088] 2 in the second embodiment achieves advantages similar to those achieved by the semiconductor device test apparatus e1 in the first embodiment.
  • In addition, the semiconductor device test apparatus e[0089] 2 in the second embodiment which is provided with the printed board 115 to electrically connect the devices to be measured 201 and the circuit board 103 achieves a reduction in cost relative to the semiconductor device test apparatus e1 in the first embodiment provided with the film 105.
  • (Third Embodiment) [0090]
  • A semiconductor device test apparatus e[0091] 3 in the third embodiment of the present invention assumes a structure that includes the circuit board 103, the printed board 115, the positioning plate 107, the holding plate 109 and the buffer member 113 that constitute the semiconductor device test apparatus e2 in the second embodiment, as illustrated in FIG. 6.
  • However, in the semiconductor device test apparatus e[0092] 3 in the third embodiment, the circuit board 103, the printed board 115 and the positioning plate 107 are integrated to constitute a first unit 121, and the holding plate 109 and the buffer member 113 are integrated to constitute a second unit 122.
  • When conducting a functional test on the devices to be measured [0093] 201, the devices to be measured 201 are each housed inside a device-securing portion 121 a which is created by a through hole 107 b at the positioning plate 107 constituting the first unit 121. The devices to be measured 201 are pressed down by the second unit 122 to be electrically connected with the printed board 115 constituting the first unit 121. In addition, since the printed board 115 is already electrically connected with the circuit board 103, electrical signals output by the peripheral devices and the source voltage are provided to the devices to be measured 201, and the electrical signals output by the devices to be measured 201 are communicated to the peripheral devices.
  • As explained above, the semiconductor device test apparatus e[0094] 3 in the third embodiment achieves advantages similar to those achieved by the semiconductor device test apparatus e2 in the second embodiment.
  • In addition, since the semiconductor device test apparatus e[0095] 3 in the third embodiment is constituted of the first unit 121 achieved by integrating the circuit board 103, the printed board 115 and the positioning plate 107 and the second unit 122 achieved by integrating the holding plate 109 and the buffer members 113, it is not necessary to assemble the circuit board 103, the printed board 115, the positioning plate 107, the holding plate 109 and the buffer members 113 to test the devices to be measured 201 and consequently, functional tests can be conducted on the devices to be measured by taking a procedure similar to that adopted when conducting functional tests using IC sockets in the prior art. Consequently, a higher degree of efficiency is achieved in functional tests and a reduction in the cost of the tests is achieved.
  • It is to be noted that in the semiconductor device test apparatus e[0096] 3 in the third embodiment, the printed board 115 may be replaced by the film 105 provided in the semiconductor device test apparatus e1 in the first embodiment.
  • (Fourth Embodiment) [0097]
  • A semiconductor device test apparatus e[0098] 4 in the fourth embodiment of the present invention assumes a structure that includes the circuit board 103, a film 106, a rubber sheet 131, the positioning plate, 107 and the holding plate 109 as illustrated in FIG. 7. Namely, the semiconductor device test apparatus e4 in the fourth embodiment assumes a structure achieved by replacing the film 105 in the semiconductor device test apparatus e1 in the first embodiment with the film 106 and by adding the rubber sheet 131.
  • The [0099] film 106 and the rubber sheet 131 are respectively provided with reference holes 106 a and 131 a at the four corners and they are secured onto the circuit board 103 together with the positioning plate 107 and the holding plate 109 by the pins 111.
  • It is to be noted that FIG. 7 shows a device to be measured [0100] 202. Like the devices to be measured 201 described earlier, the devices to be measured 202 are CSP devices, and in addition, they each constitute a BGA (ball grid array). The positioning plate 107 is provided with a plurality of through holes 107 b constituting positioning portions to enable positioning of the devices to be measured 202. The through holes 107 b are shaped to conform with the external shape of the devices to be measured 202.
  • FIG. 8 is a sectional view illustrating the semiconductor device test apparatus e[0101] 4 in the fourth embodiment and a plurality of devices to be measured 202 fitted at the semiconductor device test apparatus e4 for the purpose of various types of functional tests. The devices to be measured 202 are each inserted at a through hole 107 b at the positioning plate 107 and are held against the rubber sheet 131 by the holding plate 109. In addition, a buffer member 113 is provided between each device to be measured 202 and the holding plate 109 to ensure that the pressure from the holding plate 109 is distributed to the individual devices to be measured 202 evenly and correctly. Furthermore, the rubber sheet 131 is held against the film 106 with the pressure applied by the holding plate 109 and the film 106 is held against the circuit board 103.
  • Now, the connections among the device to be measured [0102] 202, the rubber sheet 131, the film 106 and the circuit board 103 are explained in reference to FIG. 9 which is an enlargement of FIG. 8.
  • The device to be measured [0103] 202 which is a BGA as explained earlier, is provided with the plurality of solder balls constituting electrodes 202 a.
  • At the [0104] circuit board 103, a plurality of electrodes 103 c are formed at positions that face opposite a plurality of electrodes 202 a at the device to be measured 202.
  • [0105] Electrodes 106 b are formed at the surface of the film 106 located toward the rubber sheet 131. At the surface of the film 106 located toward the circuit board 103, electrodes 106 c are firmed at positions facing opposite the plurality of electrodes 103 c at the circuit board 103. The electrodes 106 b and the electrodes 106 c formed at different surfaces of the film 106 are electrically connected via through holes 106 d.
  • The [0106] rubber sheet 131 is provided with anisotropic conductive rubber portions 131 b at positions facing opposite the electrodes 106 b at the film 106 and the electrodes 202 a at the device to be measured 202.
  • When conducting a functional test on the devices to be measured [0107] 202, various types of electrical signals output by peripheral devices (rot shown) and the source voltage are input to the circuit board 103 via the connection terminals 103 a and 103 b, travel through the wiring circuit formed at the circuit board 103 and reach the electrodes 103 c. As illustrated in FIGS. 8 and 9, the electrodes 103 c are electrically connected with the anisotropic conductive rubber portions 131 b embedded in the rubber sheet 131 via the electrodes 106 c and the bumps 106 b formed at the film 106. In addition, the anisotropic conductive rubber portions 131 b are electrically connected with the electrodes 202 a formed at the devices to be measured 202. Consequently, various types of electrical signals output by the peripheral devices and the source voltage are provided to the devices to be measured 202 to electrically drive the devices to be measured 202. The various types of electrical signals output by the devices to be measured 202 travel through the anisotropic conductive rubber portions 131 b embedded in the rubber sheet 131 and the electrodes 106 b and 106 c formed at the film 106 to be taken into the circuit board 103 via the electrodes 103 c and are further sent out to the peripheral devices.
  • When the semiconductor device test apparatus e[0108] 4 in the fourth embodiment structured as described above, which does not include any contacts formed through machining as in the IC sockets 3 in the prior art is adopted, a reduction in the pitch of the plurality of electrodes 202 a formed at each device to be measured 202 can be supported, as in the case of the semiconductor test apparatus e1 in the first embodiment. For instance, even when the pitch of the electrodes 202 a is equal to or less than 0.5 mm, functional tests can be conducted on the devices to be measured 202.
  • In addition, the semiconductor device test apparatus e[0109] 4 in the fourth embodiment, which is provided with the positioning plate 107 capable of aligning the plurality of devices to be measured 202 in a batch, does not require an IC socket to be provided for each device to be measured 202. Thus, the expense of providing IC sockets is eliminated. In addition, by using the area on the circuit board 103 which is occupied by the body portion of the IC sockets in the prior art, a larger number of devices to be measured 202 can be mounted at the circuit board 103 so that even more devices to be measured can be tested in a single functional test.
  • It is to be noted that it is necessary to take into consideration a possible deformation of the ball-shaped electrodes when conducting various types of functional tests on BGAs such as the devices to be measured [0110] 202. In the case of the semiconductor device test apparatus e4 in the fourth embodiment, which is provided with the rubber sheet 131 that achieves elasticity and at the same time enables electrical connection only in the thicknesswise direction, the electrodes 202 a formed at the devices to be measured 202 do not become deformed. The anisotropic conductive rubber portions 131 b provided at the rubber sheet 131 come in contact with the ball-shaped electrodes 202 a provided at the devices to be measured 202 over a larger area due to their elasticity. Thus, when the semiconductor device test apparatus e4 in the fourth embodiment is employed, the individual devices to be measured 202 achieve reliable electrical connection with the peripheral devices to enable functional tests to be performed with a higher degree of accuracy.
  • (Fifth Embodiment) [0111]
  • FIG. 10 is a sectional view illustrating a semiconductor device test apparatus e[0112] 5 in the fifth embodiment of the present invention and a plurality of devices to be measured 202 that are fitted at the semiconductor device test apparatus e5 for the purpose of various types of functional tests. The semiconductor device test apparatus e5 in the fifth embodiment adopts a structure which is achieved by replacing the film 106 in the semiconductor device test apparatus e4 in the fourth embodiment with a printed board 116, as illustrated in FIG. 10.
  • The devices to be measured [0113] 202 are each inserted at a through hole 107 b at the positioning plate 107 and are held against the rubber sheet 131 by the holding plate 109. In addition, a buffer member 113 is provided between each device to be measured 202 and the holding plate 109 to ensure that the pressure from the holding plate 109 is distributed to the individual devices to be measured 202 evenly and correctly. Furthermore, the rubber sheet 131 is held against the printed board 116 with the pressure applied by the holding plate 109 and the printed board 116 is held against the circuit board 103.
  • Now, the connections among the device to be measured [0114] 202, the rubber sheet 131, the printed board 116 and the circuit board 103 are explained in reference to FIG. 11 which is an enlargement of FIG. 10.
  • Electrodes [0115] 116 b are formed at the surface of the printed board 116 located toward the rubber sheet 131. At the surface of the printed board 116 located toward the circuit board 103, electrodes 116 c are formed at positions facing opposite the plurality of electrodes 103 c at the circuit board 103. The electrodes 116 b and the electrodes 1 16 c formed at different surfaces of the printed board 116 are electrically connected via through holes 116 d.
  • The [0116] rubber sheet 131 is provided with anisotropic conductive rubber portions 131 b at positions facing opposite the electrodes 116 b at the printed board 116 and the electrodes 202 a at the device to be measured 202.
  • When conducting a functional test on the devices to be measured [0117] 202, various types of electrical signals output by peripheral devices (not shown) and the source voltage are input to the circuit board 103 via the connection terminals 103 a and 103 b, travel through the wiring circuit formed at the circuit board 103 and reach the electrodes 103 c. As illustrated in FIGS. 10 and 11, the electrodes 103 c are electrically connected with the anisotropic conductive rubber portions 131 b embedded in the rubber sheet 131 via the electrodes 116 c and the electrodes 116 b formed at the printed board 111. In addition, the anisotropic conductive rubber portions 131 b are electrically connected with the electrodes 202 a formed at the devices to be measured 202. Consequently, various types of electrical signals output by the peripheral devices and the source voltage are provided to the devices to be measured 202 to electrically drive the devices to be measured 202. In addition, the various types of electrical signals output by the devices to be measured 202 travel through the anisotropic conductive rubber portions 131 b embedded in the rubber sheet 131 and the electrodes 116 b and 116 c formed at the printed board 116 to be taken into the circuit board 103 via the electrodes 103 c and are further sent out to the peripheral devices.
  • As explained above, the semiconductor device test apparatus e[0118] 5 in the fifth embodiment achieves advantages similar to those achieved by the semiconductor device test apparatus e4 in the fourth embodiment.
  • In addition, with the semiconductor device test apparatus e[0119] 5 in the fifth embodiment which is provided with the printed board 116 to achieve electrical connection between the devices to be measured 202 and the circuit board 103, a reduction in the production cost is achieved compared to the semiconductor device test apparatus e4 in the fourth embodiment provided with the film 106.
  • (Sixth Embodiment) [0120]
  • A semiconductor device test apparatus e[0121] 6 in the sixth embodiment of the present invention assumes a structure that includes the circuit board 103, the printed board 116, the rubber sheet 131, the positioning plate 107, the holding plate 109 and the buffer members 113 that constitute the semiconductor device test apparatus e5 in the fifth embodiment, as illustrated in FIG. 12.
  • However, in the semiconductor device test apparatus e[0122] 6 in the sixth embodiment, the circuit board 103, the printed board 116, the rubber sheet 131 and the positioning plate 107 are integrated to constitute a first unit 141, and the holding plate 109 and the buffer members 113 are integrated to constitute a second unit 142.
  • When conducting a functional test on the devices to be measured [0123] 202, the devices to be measured 202 are each housed inside a device-securing portion 141 a which is created by a through hole 107 b at the positioning plate 107 constituting the first unit 141. The devices to be measured 202 are pressed down by the second unit 142 to be electrically connected with the rubber sheet 131 constituting the first unit 141. In addition, since the rubber sheet 131 is already electrically connected with the printed board 116 and the printed board 116 is already electrically connected with the circuit board 103, consequently, the electrical signals output by the peripheral devices and the source voltage are provided to the devices to be measured 202, and the electrical signals output by the devices to be measured 202 are communicated to the peripheral devices.
  • As explained above, the semiconductor device test apparatus e[0124] 6 in the sixth embodiment achieves advantages similar to those achieved by the semiconductor device test apparatus e5 in the fifth embodiment.
  • In addition, since the semiconductor device test apparatus e[0125] 6 in the sixth embodiment is constituted of the first unit 141 achieved by integrating the circuit board 103, the printed board 116, the rubber sheet 131 and the positioning plate 107 and the second unit 142 achieved by integrating the holding plate 109 and the buffer members 113, it is not necessary to assemble the circuit board 103, the printed board 116, the rubber sheet 131, the positioning plate 107, the holding plate 109 and the buffer members 113 to test the devices to be measured 202 and consequently, functional tests can be conducted on the devices to be measured 202 by taking a procedure similar to that adopted when conducting functional tests using IC sockets in the prior art. Consequently, a higher degree of efficiency is achieved in functional tests and a reduction in the cost of the tests is achieved.
  • It is to be noted that in the semiconductor device test apparatus e[0126] 6 in the sixth embodiment, the printed board 116 may be replaced by the film 106 provided in the semiconductor device test apparatus e4 in the fourth embodiment.
  • (Seventh Embodiment) [0127]
  • As illustrated in FIG. 13, a semiconductor device test apparatus e[0128] 7 in the seventh embodiment of the present invention assumes a structure that includes a circuit board 303, a film 305, a positioning plate 307 and a holding plate 309.
  • The [0129] circuit board 303 is connected to peripheral devices (not shown) through connection terminals 303 a and 303 b to enable input and output of various types of electrical signals and a source voltage. The circuit board 303 may be constituted of, for instance, a multilayer substrate.
  • The [0130] film 305, the positioning plate 307 and the holding plate 309 are respectively provided with reference holes 305 a, 307 a and 309 a at the four corners, and are secured onto the circuit board 303 with pins 311.
  • The [0131] positioning plate 307 is provided with a through hole 307 b constituting a positioning member to enable positioning of a wafer to be measured 401. The through hole 307 b is formed in a shape that conforms with the external shape of the wafer to be measured 401.
  • A plurality of ventilating through [0132] holes 309 b are formed at the holding plate 309. This makes it possible to expose the wafer to be measured 401 to the air that circulates through convection when, for instance, a burn-in is implemented on the wafer to be measured 401. It is to be noted that for applications other than bum-in, the ventilating through holes 309 b may be omitted.
  • Now, the wafer to be measured [0133] 401, which is to undergo various types of functional tests conducted by using the semiconductor device test apparatus e7 in the seventh embodiment is explained in reference to FIG. 14.
  • The wafer to be measured [0134] 401 is resin-coated and is ultimately divided into a plurality of CSP devices 411. FIG. 15 is a sectional view of a CSP device 411 along line A-A′ in FIG. 14. A plurality of electrodes 411 b are provided at the surface of a device body 411 a. The electrodes 411 b are land type (LGA) electrodes with flat surfaces.
  • FIG. 16 is a sectional view illustrating the semiconductor device test apparatus e[0135] 7 in the seventh embodiment and the wafer to be measured 401 immediately before the wafer to be measured 401 is mounted at the semiconductor device test apparatus e7 for the purpose of various types of functional tests. A buffer member 313 is provided at the holding plate 309 at a position that faces opposite the wafer to be measured 401. In addition, it is desirable to pre-assemble the circuit board 303, the film 305 and the positioning plate 307 to achieve an integrated assembly, as illustrated in FIG. 16.
  • Then, the wafer to be measured [0136] 401 is mounted at the semiconductor device test apparatus e7 in the seventh embodiment as illustrated in FIG. 17. The wafer to be measured 401 is inserted at the through hole 307 b at the positioning plate 307 and is pressed against the film 305 by the holding plate 309. The pressure from the holding plate 309 is distributed evenly and correctly to the wafer to be measured 401 by the buffer member 313 provided at the holding plate 309. In addition, the film 305 is held onto the circuit board 303 by the pressure from the holding plate 309.
  • Now, the connections among the wafer to be measured [0137] 401, the film 305 and the circuit board 303 are explained in reference to FIG. 18 which is an enlargement of FIG. 17.
  • At the [0138] circuit board 303, a plurality of electrodes 303 c are formed at positions that face opposite the plurality of electrodes 411 b at the wafer to be measured 401.
  • [0139] Bumps 305 b are formed at the surface of the film 305 located toward the wafer to be measured 401, at positions that face opposite the plurality of electrodes 411 b at the wafer to be measured 401. These bumps 305 b, which are terminals capable of supplying source voltage and inputting/outputting various types of electrical signals, are each formed in a semi-spherical shape through electrolytic plating. They may be constituted of, for instance, copper, with their surfaces processed in a gold plating treatment. Alternatively, instead of the bumps, projections may be formed through etching.
  • Electrodes (lands) [0140] 305 c are formed at the surface of the film 305 located toward the circuit board 303, at positions facing opposite the plurality of electrodes 303 c at the circuit board 303. The bumps 305 b and the electrodes 305 c formed at different surfaces of the film 305 are electrically connected via through holes 305 d.
  • When conducting a functional test on the wafer to be measured [0141] 401, various types of electrical signals output by peripheral devices (not shown) and the source voltage are input to the circuit board 303 via the connection terminals 303 a and 303 b, travel through the wiring circuit formed at the circuit board 303 and reach the electrodes 303 c. As illustrated in FIGS. 17 and 18, the electrodes 303 c are electrically connected with the electrodes 411 b formed at the wafer to be measured 401 via the electrodes 305 c and the bumps 305 b formed at the film 305. Consequently, various types of electrical signals output by the peripheral devices and the source voltage are provided to the wafer to be measured 401 to electrically drive the wafer to be measured 401. In addition, the various types of electrical signals output by the wafer to be measured 401 travel through the bumps 305 b and the electrodes 305 c formed at the film 305, are taken into the circuit board 303 via the electrodes 303 c and are further sent out to the peripheral devices.
  • When the semiconductor device test apparatus e[0142] 7 in the seventh embodiment structured as described above, which does not include any contacts formed through machining as in the IC sockets 3 in the prior art is adopted, a reduction in the pitch of the plurality of electrodes 411 b formed at the wafer to be measured 401 can be supported. For instance, even when the pitch of the electrodes 411 b is equal to or less than 0.5 mm, functional tests can be conducted on the wafer to be measured 401.
  • In addition, the semiconductor device test apparatus e[0143] 7 in the seventh embodiment enables various types of functional tests to be conducted at the wafer level without dividing the wafer into chips. Thus, the necessity for providing IC sockets for individual chips is eliminated to eliminate the cost of IC sockets.
  • Furthermore, by fitting the semiconductor device test apparatus e[0144] 7 in the seventh embodiment, which supports resin-coated CSP level wafers, at a test/monitor burn-in apparatus in the prior art, it becomes possible to conduct batch tests/burn-ins.
  • It is to be noted that while the [0145] film 305 is provided in the semiconductor device test apparatus e7 in the seventh embodiment, a printed board may be utilized instead.
  • (Eighth Embodiment) [0146]
  • A semiconductor device test apparatus e[0147] 8 in the eighth embodiment of the present invention assumes a structure that includes the circuit board 303, a film 306, a rubber sheet 331, the positioning plate 307 and the holding plate 309 as illustrated in FIG. 19. In other words, the semiconductor device test apparatus e8 in the eighth embodiment assumes a structure achieved by replacing the film 305 in the semiconductor device test apparatus e7 in the seventh embodiment with the film 306 and adding the rubber sheet 331.
  • The [0148] film 306 and the rubber sheet 331 are respectively provided with reference holes 306 a and 331 a at the four corners and they are secured onto the circuit board 303 together with the positioning plate 307 and the holding plate 309 by the pins 311.
  • The [0149] positioning plate 307 is provided with a through hole 307 b constituting a positioning member to enable positioning of a wafer to be measured 402. The through hole 307 b is formed in a shape that conforms with the external shape of the wafer to be measured 402.
  • Now, the wafer to be measured [0150] 402, which is to undergo various types of functional tests conducted by using the semiconductor device test apparatus e8 in the eighth embodiment is explained in reference to FIG. 20.
  • The wafer to be [0151] measure 402 is resin-coated and is ultimately divided into a plurality of CSP devices 412, as in the case of the wafer to be measured 401 in the previous embodiment. FIG. 21 is a sectional view of a CSP device 412 along line B-B′ in FIG. 20. A plurality of electrodes 412 b are provided at the surface of a device body 412 a. The electrodes 412 b are ball-type electrodes, and the CSP devices 412 are formed as BGAs.
  • FIG. 22 is a sectional view illustrating the semiconductor device test apparatus e[0152] 8 in the eighth embodiment and the wafer to be measured 402 immediately before the wafer to be measured 402 is mounted at the semiconductor device test apparatus e8 for the purpose of various types of functional tests. A buffer member 313 is provided at the holding plate 309 at a position that faces opposite the wafer to be measured 402. In addition, it is desirable to pre-assemble the circuit board 303, the film 306, the rubber sheet 331 and the positioning plate 307 to achieve an integrated assembly, as illustrated in FIG. 22.
  • Then, the wafer to be measured [0153] 402 is fitted at the semiconductor device test apparatus e8 in the eighth embodiment as illustrated in FIG. 23. The wafer to be measured 402 is inserted at the through hole 307 b at the positioning plate 307 and is held against the rubber sheet 331 by the holding plate 309. The pressure from the holding plate 309 is distributed evenly and correctly to the wafer to be measured 402 by the buffer member 313 provided at the holding plate 309. Furthermore, the rubber sheet 331 is held against the film 306 with the pressure applied by the holding plate 309 and the film 306 is held against the circuit board 303.
  • Now, the connections among the wafer to be measured [0154] 402, the rubber sheet 331, the film 306 and the circuit board 303 are explained in reference to FIG. 24 which is an enlargement of FIG. 23.
  • The wafer to be measured [0155] 402, which is a BGA as explained earlier, is provided with a plurality of solder balls constituting electrodes 412 b.
  • At the [0156] circuit board 303, a plurality of electrodes 303 c are formed at positions that face opposite a plurality of electrodes 412 b at the wafer to be measured 402.
  • [0157] Electrodes 306 b are formed at the surface of the film 306 located toward the rubber sheet 331. At the surface of the film 306 located toward the circuit board 303, electrodes 306 c are formed at positions facing opposite the plurality of electrodes 303 c at the circuit board 303. The electrodes 306 b and the electrodes 306 c formed at different surfaces of the film 306 are electrically connected via through holes 306 d.
  • The [0158] rubber sheet 331 is provided with anisotropic conductive rubber portions 331 b at positions facing opposite the electrodes 306 b at the film 306 and the electrodes 412 b at the wafer to be measured 402.
  • When conducting a functional test on the wafer to be measured [0159] 402, various types of electrical signals output by peripheral devices (not shown) and the source voltage are input to the circuit board 303 via the connection terminals 303 a and 303 b, travel through the wiring circuit formed at the circuit board 303 and reach the electrodes 303 c. As illustrated in FIGS. 23 and 24, the electrodes 303 c are electrically connected with the anisotropic conductive rubber portions 331 b embedded in the rubber sheet 331 via the electrodes 306 c and the electrodes 306 b formed at the film 306. In addition, the anisotropic conductive rubber portions 331 b are electrically connected with the electrodes 412 b formed at the wafer to be measured 402. Consequently, various types of electrical signals output by the peripheral devices and the source voltage are provided to the wafer to be measured 402 to electrically drive the wafer to be measured 402. The various types of electrical signals output by the wafer to be measured 402 travel through the anisotropic conductive rubber portions 331 b embedded in the rubber sheet 331 and the electrodes 306 b and 306 c formed at the film 306 to be taken into the circuit board 303 via the electrodes 303 c and are further sent out to the peripheral devices.
  • As explained above, the semiconductor device test apparatus e[0160] 8 in the eighth embodiment achieves advantages similar to those achieved by semiconductor device test apparatus e7 in the seventh embodiment.
  • It is to be noted that it is necessary to take into consideration a possible deformation of the ball-shaped electrodes when conducting various types of functional tests on BGAs such as the wafer to be measured [0161] 402. In the case of the semiconductor device test apparatus e8 in the eighth embodiment, which is provided with the rubber sheet 331 that achieves elasticity and at the same time enables electrical connection only in the thicknesswise direction, the electrodes 412 b formed at the wafer to be measured 402 do not become deformed. The anisotropic conductive rubber portions 331 b provided at the rubber sheet 331 come in contact with the ball-shaped electrodes 412 b provided at the wafer to be measured 402 over a larger area due to their elasticity. Thus, when the semiconductor device test apparatus e8 in the eighth embodiment is employed, the wafer to be measured 402 achieve reliable electrical connection with the peripheral devices to enable functional tests to be performed at a higher degree of accuracy.
  • It is to be noted that while the [0162] film 306 is provided at the semiconductor device test apparatus e8 in the eighth embodiment, a printed board may be utilized, instead.
  • (Ninth Embodiment) [0163]
  • A semiconductor device test apparatus e[0164] 9 in the ninth embodiment of the present invention adopts a structure that includes a circuit board 503, probes 511, a probe sheet 521 and a rubber sheet 531, as illustrated in FIG. 25.
  • The [0165] circuit board 503 is connected to peripheral devices (not shown) to allow input and output of various types of electrical signals and a source voltage.
  • The [0166] probes 511 are constituted of tungsten or beryllium copper. In addition, contact portions 511 a of the probes 511 where they come in contact with the rubber sheet 531 are clad with gold plate to prevent oxidation and to assure good contact. It is to be noted that the gold-plating treatment is not restricted to be implemented on the contact portions 511 a only, and may be implemented over the entire surfaces of the probes 511.
  • The [0167] probe sheet 521 may be constituted of a rubber sheet having a heat resistant property or a membrane sheet formed from glass fiber/polyimide. In addition, the probes 511 are embedded in the probe sheet 521, and are each provided with notches 511 b as illustrated in FIG. 26 to ensure that they do not slip out of the probe sheet 521.
  • The [0168] rubber sheet 531 is provided with anisotropic conductive rubber portions 531 a to electrically connect a plurality of electrodes 503 a formed at the circuit board 503 and the contact portions 511 a at the plurality of probes 511.
  • Now, a wafer to be measured upon which various types of functional tests may be conducted employing the semiconductor device test apparatus e[0169] 9 in the ninth embodiment is explained. As an example to facilitate the explanation, an IC chip 601 formed in one partitioned area of the wafer to be measured is illustrated in FIG. 27. The IC chip 601 is provided with a plurality of pads 601 a. Normally, the pads 601 a will be constituted of aluminum. In addition, the entire area of the IC chip 601 where the pads 601 a are not present (in particular, the area where the circuit is formed) is protected from the outside atmosphere by a resist film 601 b.
  • When conducting various types of functional tests on the [0170] IC chip 601 employing the semiconductor device test apparatus e9 in the ninth embodiment, the individual probes 511 are placed in contact with the corresponding pads 601 a as illustrated in FIG. 28. As described above, since no resist film 601 b is formed at the pads 601 a, the pads 601 a and the probes 511 become electrically connected.
  • When conducting a functional test on the [0171] IC chip 601, various types of electrical signals output by the peripheral devices (not shown) and the source voltage are input to the circuit board 503, travel through the wiring circuit formed at the circuit board 503 and reach the electrodes 503 a. During this process, the electrodes 503 a are electrically connected with the probes 511 via the anisotropic conductive rubber portions 531 a provided at the rubber sheet 531, as illustrated in FIG. 25. Consequently, the various types of electrical signals output by the peripheral devices and the source voltage are provided to the IC chip 601 via the probes 511 to electrically drive the IC chip 601. In addition, various types of electrical signals output by the IC chip 601 travel through the probes 511 and the anisotropic conductive rubber portions 531 a provided at the rubber sheet 531 to be taken into the circuit board 503 via the electrodes 503 a and they are then sent out to the peripheral devices.
  • In addition, even if slight level differences are formed at the individual pads due to, for instance, the laminated structure assumed by the [0172] IC chip 601, these stages are absorbed by the rubber sheet 531 and the probe sheet 521 so that the individual probes 511 come into contact with the pads 601 a formed at the IC chip 601 with a high degree of reliability. Furthermore, some margin is obtained in regard to the accuracy of the front end alignment for the individual probes 511 when manufacturing the semiconductor device test apparatus e9 in the ninth embodiment.
  • As explained above, in the semiconductor device test apparatus e[0173] 9 in the ninth embodiment provided with the probes 511, which are constituted of tungsten or beryllium copper and are placed in contact with the object of testing, durability against contact is achieved that is comparable to that of a probe card 13 in the prior art. Thus, the semiconductor device test apparatus e9 in the ninth embodiment may be employed in a product inspection process as well as in functional tests conducted during the semiconductor device development stage.
  • Furthermore, the semiconductor device test apparatus e[0174] 9, which assumes a structure in which the front ends of the probes 511 are placed in contact with the object of testing in a perpendicular attitude, is capable of supporting a finer pitch of the pads at the object of testing (eg. an electrode pitch of 0.5 mm or smaller). In addition, it is possible to place the probes 511 in contact with all the pads formed at the object of testing simultaneously. Also, the probes 511 may be embedded in the probe sheet 521 through an automated process to achieve a low production cost for mass production.
  • Moreover, the semiconductor device test apparatus e[0175] 9 in the ninth embodiment may be combined with a wafer-level test/burn-in apparatus. This will make it possible to reduce the level of investment in the tester employed in tests on finished semiconductor device products, which ultimately leads to reductions in the test cost and the device cost.
  • While the invention has been particularly shown and described with respect to preferred embodiments thereof by referring to the attached drawings, the present invention is not limited to these examples and it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit, scope and teaching of the invention. [0176]
  • As has been explained, according to the present invention, tests on semiconductor devices having electrodes provided at a fine pitch can be conducted with ease and at low cost. In addition, the durability of the semiconductor device test apparatus against repeated tests can be improved. Furthermore, since batch-testing of a great number of semiconductor devices is enabled, higher efficiency in testing is achieved. [0177]
  • The entire disclosure of Japanese Patent Application No. 11-66621 filed on Mar. 12, 1999 including specification, claims, drawings and summary is incorporated herein by reference in its entirety. [0178]

Claims (20)

What is claimed is:
1. A semiconductor device test apparatus employed to test one or a plurality of semiconductor devices each provided with a plurality of electrodes, comprising:
a circuit board provided with a circuit corresponding to said semiconductor device and a plurality of electrodes that correspond to individual electrodes at said semiconductor device; and
a connection plate that is provided with a plurality of conductive portions that electrically connect said electrodes at the semiconductor device and said electrodes at said circuit board on a one-to-one basis.
2. A semiconductor device test apparatus according to
claim 1
, wherein:
said conductive portions are formed at through holes provided at said connection plate.
3. A semiconductor device test apparatus according to
claim 1
, wherein:
conductive elastic bodies are provided between said connection plate and said semiconductor device to electrically connect said conductive portions at said connection plate and said electrodes at said semiconductor device on a one-to-one basis.
4. A semiconductor device test apparatus according to
claim 1
, further comprising:
a positioning member that secures said semiconductor device.
5. A semiconductor device test apparatus according to
claim 2
, further comprising:
a positioning member that secures said semiconductor device.
6. A semiconductor device test apparatus according to
claim 3
, further comprising:
a positioning member that secures said semiconductor device.
7. A semiconductor device test apparatus according to
claim 4
or
5
, wherein:
said circuit board, said connection plate and said positioning member are integrated.
8. A semiconductor device test apparatus according to
claim 6
, wherein:
said circuit board, said connection plate, said conductive elastic bodies and said positioning member are integrated.
9. A semiconductor device test apparatus according to
claim 1
, further comprising:
a holding member that presses said semiconductor device toward said connection plate.
10. A semiconductor device test apparatus according to
claim 9
, wherein:
said holding member is provided with a buffer member positioned so as to come in contact with said semiconductor device.
11. A semiconductor device test apparatus according to
claim 1
, wherein:
said connection plate is constituted of film.
12. A semiconductor device test apparatus according to
claim 1
, wherein:
said connection plate is constituted of a printed board.
13. A semiconductor device test apparatus according to
claim 1
, wherein:
said semiconductor device is a chip.
14. A semiconductor device test apparatus according to
claim 1
, wherein:
said semiconductor device is a wafer.
15. A semiconductor device test apparatus employed to test one or a plurality of semiconductor devices each having a plurality of electrodes, provided with;
a probe holding member with a plurality of probes fitted therein to expose sharp ends thereof and ends thereof on a side opposite from said sharp ends that correspond with individual electrodes at said semiconductor device on a one-to-one basis.
16. A semiconductor device test apparatus according to
claim 15
, wherein:
at each of said probes, a notched portion is formed in an area located inside said probe holding member.
17. A semiconductor device test apparatus according to
claim 15
, further provided with:
a plurality of conductive rubber portions that correspond to said probes on a one-to-one basis.
18. A semiconductor device test apparatus according to
claim 17
, wherein:
a gold-clad film is formed at said probes, at least, in areas where said probes come in contact with said conductive rubber portions.
19. A semiconductor device test apparatus according to
claim 15
, wherein:
said semiconductor device is a chip.
20. A semiconductor device test apparatus according to
claim 15
, wherein:
said semiconductor device is a wafer.
US09/434,490 1999-03-12 1999-11-05 Semiconductor device test apparatus Expired - Fee Related US6407563B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US09/904,663 US6879169B2 (en) 1999-03-12 2001-07-16 Method for manufacturing and batch testing semiconductor devices
US10/279,988 US7262610B2 (en) 1999-03-12 2002-10-25 Method for manufacturing and testing semiconductor devices on a resin-coated wafer
US11/785,644 US7639027B2 (en) 1999-03-12 2007-04-19 Method of testing circuit elements on a semiconductor wafer

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP11066621A JP2000258495A (en) 1999-03-12 1999-03-12 Semiconductor device testing device
JP11-066621 1999-03-12
JPJP11-66621 1999-03-12

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/904,663 Division US6879169B2 (en) 1999-03-12 2001-07-16 Method for manufacturing and batch testing semiconductor devices

Publications (2)

Publication Number Publication Date
US20010053170A1 true US20010053170A1 (en) 2001-12-20
US6407563B2 US6407563B2 (en) 2002-06-18

Family

ID=13321155

Family Applications (4)

Application Number Title Priority Date Filing Date
US09/434,490 Expired - Fee Related US6407563B2 (en) 1999-03-12 1999-11-05 Semiconductor device test apparatus
US09/904,663 Expired - Fee Related US6879169B2 (en) 1999-03-12 2001-07-16 Method for manufacturing and batch testing semiconductor devices
US10/279,988 Expired - Fee Related US7262610B2 (en) 1999-03-12 2002-10-25 Method for manufacturing and testing semiconductor devices on a resin-coated wafer
US11/785,644 Expired - Fee Related US7639027B2 (en) 1999-03-12 2007-04-19 Method of testing circuit elements on a semiconductor wafer

Family Applications After (3)

Application Number Title Priority Date Filing Date
US09/904,663 Expired - Fee Related US6879169B2 (en) 1999-03-12 2001-07-16 Method for manufacturing and batch testing semiconductor devices
US10/279,988 Expired - Fee Related US7262610B2 (en) 1999-03-12 2002-10-25 Method for manufacturing and testing semiconductor devices on a resin-coated wafer
US11/785,644 Expired - Fee Related US7639027B2 (en) 1999-03-12 2007-04-19 Method of testing circuit elements on a semiconductor wafer

Country Status (5)

Country Link
US (4) US6407563B2 (en)
JP (1) JP2000258495A (en)
KR (1) KR100741551B1 (en)
SG (2) SG146414A1 (en)
TW (1) TW449847B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060154497A1 (en) * 2005-01-11 2006-07-13 Takashi Amemiya Inspection contact structure and probe card
US20110043239A1 (en) * 2008-03-14 2011-02-24 Fujifilm Corporation Probe card
CN102866318A (en) * 2012-09-26 2013-01-09 贵州航天计量测试技术研究所 Test device for laminar packaging discrete device
CN102867760A (en) * 2011-07-08 2013-01-09 索尼公司 Test circuit, integrated circuit, and test circuit layout method
US20140140373A1 (en) * 2012-11-22 2014-05-22 C/O Samsung Electro-Mechanics Co., Ltd Apparatus and method of testing semiconductor module
US11231443B2 (en) * 2016-04-21 2022-01-25 Micro Friend Co., Ltd Semiconductor device test socket

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000258495A (en) * 1999-03-12 2000-09-22 Oki Electric Ind Co Ltd Semiconductor device testing device
US6462568B1 (en) * 2000-08-31 2002-10-08 Micron Technology, Inc. Conductive polymer contact system and test method for semiconductor components
JP2002257898A (en) * 2001-03-06 2002-09-11 Nec Corp Structure of probe for inspecting semiconductor device and method of making the same
US7303120B2 (en) * 2001-07-10 2007-12-04 American Express Travel Related Services Company, Inc. System for biometric security using a FOB
US7700379B2 (en) 2001-08-13 2010-04-20 Finisar Corporation Methods of conducting wafer level burn-in of electronic devices
JP2005500691A (en) * 2001-08-13 2005-01-06 ハネウェル・インターナショナル・インコーポレーテッド Providing optical control of semiconductor devices carried on a wafer
US8039277B2 (en) 2001-08-13 2011-10-18 Finisar Corporation Providing current control over wafer borne semiconductor devices using overlayer patterns
KR20030067401A (en) * 2002-02-08 2003-08-14 정운영 Test socket
US7300173B2 (en) * 2004-04-08 2007-11-27 Technology Assessment Group, Inc. Replacement illumination device for a miniature flashlight bulb
US7777430B2 (en) 2003-09-12 2010-08-17 Terralux, Inc. Light emitting diode replacement lamp
US8632215B2 (en) 2003-11-04 2014-01-21 Terralux, Inc. Light emitting diode replacement lamp
US7642791B2 (en) * 2003-11-07 2010-01-05 Intel Corporation Electronic component/interface interposer
US20050164505A1 (en) * 2004-01-26 2005-07-28 Renfro Tim A. Land grid array membrane
EP1806589A4 (en) 2004-10-29 2012-02-29 Jsr Corp Probe member for wafer inspection, probe card for wafer inspection and wafer inspection equipment
US7928591B2 (en) * 2005-02-11 2011-04-19 Wintec Industries, Inc. Apparatus and method for predetermined component placement to a target platform
US20070187844A1 (en) 2006-02-10 2007-08-16 Wintec Industries, Inc. Electronic assembly with detachable components
US7259581B2 (en) * 2005-02-14 2007-08-21 Micron Technology, Inc. Method for testing semiconductor components
JP2006292727A (en) * 2005-03-18 2006-10-26 Alps Electric Co Ltd Semiconductor transfer tray, burn-in board using the same, inspection apparatus for burn-in test, burn-in test method, and semiconductor manufacturing method
US20110223695A1 (en) * 2006-02-10 2011-09-15 Kong-Chen Chen Electronic assembly with detachable components
US20110222253A1 (en) * 2006-02-10 2011-09-15 Kong-Chen Chen Electronic assembly with detachable components
US20110222252A1 (en) * 2006-02-10 2011-09-15 Kong-Chen Chen Electronic assembly with detachable components
TW200745572A (en) * 2006-06-09 2007-12-16 Visera Technologies Co Ltd Manufacturing method of wafer-level testing circuit board, and the structure thereof
MY152599A (en) * 2007-02-14 2014-10-31 Eles Semiconductor Equipment S P A Test of electronic devices at package level using test boards without sockets
EP1959265A1 (en) * 2007-02-16 2008-08-20 Eles Semiconductor Equipment S.P.A. Testing integrated circuits on a wafer with a cartridge leaving exposed a surface thereof
JP2009244244A (en) * 2008-03-14 2009-10-22 Fujifilm Corp Probe card
JP2009224146A (en) * 2008-03-14 2009-10-01 Fujifilm Corp Laminated plate having anisotropic conductive member and method of manufacturing the same
US7863106B2 (en) * 2008-12-24 2011-01-04 International Business Machines Corporation Silicon interposer testing for three dimensional chip stack
JP2011013049A (en) * 2009-06-30 2011-01-20 Fujitsu Ltd Circuit test tool and circuit testing method
KR101104413B1 (en) * 2009-09-25 2012-01-16 세크론 주식회사 Connecting apparatus for testing a semiconductor device and test handler including the same
DE102013009309A1 (en) * 2013-06-04 2014-12-04 Johnson Electric Germany GmbH & Co. KG Electrical circuit arrangement with at least one flexible surface element
US9335367B2 (en) 2013-08-27 2016-05-10 International Business Machines Corporation Implementing low temperature wafer test
ITUB20155111A1 (en) * 2015-11-04 2017-05-04 St Microelectronics Srl SEMICONDUCTOR DEVICE AND ITS PROCEDURE
WO2017082510A1 (en) * 2015-11-12 2017-05-18 주식회사 오킨스전자 Test socket comprising conductive wire in conductive silicone rubber, and manufacturing method therefor
DE102015121066B4 (en) * 2015-12-03 2021-10-28 Infineon Technologies Ag SEMICONDUCTOR-SUBSTRATE-TO-SEMICONDUCTOR-SUBSTRATE PACKAGE AND METHOD FOR ITS MANUFACTURING
CN106556756B (en) * 2016-10-20 2019-06-21 北方电子研究院安徽有限公司 A kind of multidigit aging equipment of patch type capacitor and resistance
TWI639206B (en) 2018-01-16 2018-10-21 中美矽晶製品股份有限公司 Detecting system and method for dtecting through-hole electrodes of semiconductor device

Family Cites Families (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3689993A (en) * 1971-07-26 1972-09-12 Texas Instruments Inc Fabrication of semiconductor devices having low thermal inpedance bonds to heat sinks
US4633175A (en) * 1984-11-23 1986-12-30 Avx Corporation Testing method and apparatus for electronic components
DE68917231T2 (en) * 1988-05-18 1994-12-15 Canon Kk Probe card, method for measuring a part to be measured with the same and electrical circuit part.
JPH07114227B2 (en) * 1989-01-07 1995-12-06 三菱電機株式会社 Wafer test probe
JP2908818B2 (en) * 1989-09-18 1999-06-21 株式会社日立製作所 Method for manufacturing semiconductor device
JP3087294B2 (en) * 1989-09-29 2000-09-11 ジェイエスアール株式会社 Method for producing anisotropic conductive sheet
JPH03146884A (en) * 1989-11-02 1991-06-21 Mitsubishi Electric Corp Burn-in device
US5663654A (en) * 1990-08-29 1997-09-02 Micron Technology, Inc. Universal wafer carrier for wafer level die burn-in
US5206181A (en) * 1991-06-03 1993-04-27 Motorola, Inc. Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing
US5258648A (en) * 1991-06-27 1993-11-02 Motorola, Inc. Composite flip chip semiconductor device with an interposer having test contacts formed along its periphery
CA2073886A1 (en) * 1991-07-19 1993-01-20 Tatsuya Hashinaga Burn-in apparatus and method
US5541524A (en) * 1991-08-23 1996-07-30 Nchip, Inc. Burn-in technologies for unpackaged integrated circuits
JPH0555327A (en) 1991-08-26 1993-03-05 Toshiba Corp Screening method of semiconductor element
US5279975A (en) * 1992-02-07 1994-01-18 Micron Technology, Inc. Method of testing individual dies on semiconductor wafers prior to singulation
US5477160A (en) * 1992-08-12 1995-12-19 Fujitsu Limited Module test card
KR100248571B1 (en) * 1992-08-31 2000-03-15 히가시 데쓰로 Probe system
JP3007497B2 (en) 1992-11-11 2000-02-07 三菱電機株式会社 Semiconductor integrated circuit device, its manufacturing method, and its mounting method
JPH0792479B2 (en) * 1993-03-18 1995-10-09 東京エレクトロン株式会社 Parallelism adjustment method for probe device
US5395253A (en) * 1993-04-29 1995-03-07 Hughes Aircraft Company Membrane connector with stretch induced micro scrub
US5557215A (en) * 1993-05-12 1996-09-17 Tokyo Electron Limited Self-bias measuring method, apparatus thereof and electrostatic chucking apparatus
JPH07115113A (en) * 1993-08-25 1995-05-02 Nec Corp Semiconductor wafer testing device and testing method
KR0140034B1 (en) * 1993-12-16 1998-07-15 모리시다 요이치 Semiconductor wafer case, connection method and apparatus, and inspection method for semiconductor integrated circuit, probe card, and its manufacturing method
JP3108398B2 (en) 1993-12-21 2000-11-13 松下電器産業株式会社 Method of manufacturing probe card
JP3288840B2 (en) * 1994-02-28 2002-06-04 三菱電機株式会社 Semiconductor device and manufacturing method thereof
TW381328B (en) * 1994-03-07 2000-02-01 Ibm Dual substrate package assembly for being electrically coupled to a conducting member
JPH07288271A (en) 1994-04-19 1995-10-31 Aging Tesuta Kaihatsu Kyodo Kumiai Measuring electrode for integrated circuit
JP2978720B2 (en) * 1994-09-09 1999-11-15 東京エレクトロン株式会社 Probe device
US5567215A (en) * 1994-09-12 1996-10-22 The Babcock & Wilcox Company Enhanced heat exchanger flue gas treatment using steam injection
JPH08148533A (en) 1994-11-15 1996-06-07 Nec Corp Method and equipment for testing semiconductor wafer
US6046598A (en) * 1994-11-18 2000-04-04 Fujitsu Limited Test board and a test method using the same providing improved electrical connection
US5597767A (en) * 1995-01-06 1997-01-28 Texas Instruments Incorporated Separation of wafer into die with wafer-level processing
US5825192A (en) * 1995-07-14 1998-10-20 Tokyo Electron Limited Probe card device used in probing apparatus
JPH0933606A (en) 1995-07-20 1997-02-07 Shin Etsu Polymer Co Ltd Jig for inspection of semiconductor element
JPH10208A (en) 1996-06-15 1998-01-06 Dentasu:Kk Device for brushing denture
US5896038A (en) * 1996-11-08 1999-04-20 W. L. Gore & Associates, Inc. Method of wafer level burn-in
JPH10178145A (en) * 1996-12-19 1998-06-30 Texas Instr Japan Ltd Semiconductor device and its manufacturing method and insulation substrate for semiconductor device
JP3815835B2 (en) * 1997-02-18 2006-08-30 本田技研工業株式会社 Semiconductor device
JP2904193B2 (en) 1997-06-27 1999-06-14 日本電気株式会社 IC socket
JP3467394B2 (en) * 1997-10-31 2003-11-17 松下電器産業株式会社 Burn-in wafer cassette and probe card manufacturing method
JPH11163066A (en) * 1997-11-29 1999-06-18 Tokyo Electron Ltd Wafer tester
JP3420703B2 (en) * 1998-07-16 2003-06-30 株式会社東芝 Method for manufacturing semiconductor device
JP4084498B2 (en) * 1998-10-27 2008-04-30 松下電器産業株式会社 Inspection board
SG92685A1 (en) * 1999-03-10 2002-11-19 Towa Corp Method of coating semiconductor wafer with resin and mold used therefor
JP2000258495A (en) * 1999-03-12 2000-09-22 Oki Electric Ind Co Ltd Semiconductor device testing device
JP3565086B2 (en) * 1999-04-16 2004-09-15 富士通株式会社 Probe card and method for testing semiconductor device
US7247035B2 (en) * 2000-06-20 2007-07-24 Nanonexus, Inc. Enhanced stress metal spring contactor
US6250933B1 (en) * 2000-01-20 2001-06-26 Advantest Corp. Contact structure and production method thereof
JP3485525B2 (en) * 2000-07-06 2004-01-13 沖電気工業株式会社 Method for manufacturing semiconductor device
US6379982B1 (en) * 2000-08-17 2002-04-30 Micron Technology, Inc. Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing
JP2002093869A (en) * 2000-09-20 2002-03-29 Mitsubishi Electric Corp Burn-in method and burn-in apparatus
JP2002110751A (en) * 2000-10-03 2002-04-12 Hitachi Ltd Apparatus for inspecting semiconductor integrated circuit device, and its manufacturing method
US6440771B1 (en) * 2001-03-23 2002-08-27 Eaglestone Partners I, Llc Method for constructing a wafer interposer by using conductive columns
EP1806589A4 (en) * 2004-10-29 2012-02-29 Jsr Corp Probe member for wafer inspection, probe card for wafer inspection and wafer inspection equipment
TW200633314A (en) * 2004-11-12 2006-09-16 Jsr Corp Probe member for wafer inspection, probe card for wafer inspection and wafer inspection apparatus
US20090072844A1 (en) * 2005-05-19 2009-03-19 Jsr Corporation Wafer inspecting sheet-like probe and application thereof

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060154497A1 (en) * 2005-01-11 2006-07-13 Takashi Amemiya Inspection contact structure and probe card
US7267551B2 (en) 2005-01-11 2007-09-11 Tokyo Electron Limited Inspection contact structure and probe card
US20080211528A1 (en) * 2005-01-11 2008-09-04 Tokyo Electron Limited Inspection contact structure and probe card
US20080211523A1 (en) * 2005-01-11 2008-09-04 Tokyo Electron Limited Inspection contact structure and probe card
US7701234B2 (en) 2005-01-11 2010-04-20 Tokyo Electron Limited Inspection contact structure and probe card
US7719296B2 (en) 2005-01-11 2010-05-18 Tokyo Electron Limited Inspection contact structure and probe card
US20110043239A1 (en) * 2008-03-14 2011-02-24 Fujifilm Corporation Probe card
CN102867760A (en) * 2011-07-08 2013-01-09 索尼公司 Test circuit, integrated circuit, and test circuit layout method
CN102866318A (en) * 2012-09-26 2013-01-09 贵州航天计量测试技术研究所 Test device for laminar packaging discrete device
US20140140373A1 (en) * 2012-11-22 2014-05-22 C/O Samsung Electro-Mechanics Co., Ltd Apparatus and method of testing semiconductor module
US11231443B2 (en) * 2016-04-21 2022-01-25 Micro Friend Co., Ltd Semiconductor device test socket

Also Published As

Publication number Publication date
KR20000062792A (en) 2000-10-25
SG102568A1 (en) 2004-03-26
TW449847B (en) 2001-08-11
US7639027B2 (en) 2009-12-29
US6407563B2 (en) 2002-06-18
US7262610B2 (en) 2007-08-28
US20020030501A1 (en) 2002-03-14
JP2000258495A (en) 2000-09-22
US20070194802A1 (en) 2007-08-23
KR100741551B1 (en) 2007-07-20
SG146414A1 (en) 2008-10-30
US6879169B2 (en) 2005-04-12
US20030076128A1 (en) 2003-04-24

Similar Documents

Publication Publication Date Title
US7639027B2 (en) Method of testing circuit elements on a semiconductor wafer
KR100502119B1 (en) Contact structure and assembly mechanism thereof
US7385412B2 (en) Systems and methods for testing microfeature devices
US7141997B2 (en) Method for testing using a universal wafer carrier for wafer level die burn-in
EP1191588B1 (en) A spiral contactor and manufacturing method therefor
US7129730B2 (en) Probe card assembly
US7898276B2 (en) Probe card with stacked substrate
WO1997013392A2 (en) Button contact for surface mounting an ic device to a circuit board
EP0414378B1 (en) An adapter for integrated circuit elements and a method using the adapter for testing assembled elements
US6300781B1 (en) Reliable method and apparatus for interfacing between a ball grid array handler and a ball grid array testing system
US6974335B1 (en) Interchangeable multi-form factor module socket
US20030030462A1 (en) Tester for semiconductor device
US20070285115A1 (en) Universal wafer carrier for wafer level die burn-in
US20040135594A1 (en) Compliant interposer assembly for wafer test and "burn-in" operations
JP2737774B2 (en) Wafer tester
US6433565B1 (en) Test fixture for flip chip ball grid array circuits
KR20090073747A (en) Probe unit and probe card
JP4408748B2 (en) Manufacturing method of semiconductor device
US5880591A (en) System for circuit modules having a plurality of independently positionable probes
KR0169819B1 (en) Apparatus for fabricating known good die
JP2001015457A (en) Production of semiconductor device
JP2000331764A (en) Ic socket

Legal Events

Date Code Title Description
AS Assignment

Owner name: OKI ELECTRIC INDUSTRY CO., LTD., JAPAN

Free format text: INVALID RECORDING.;ASSIGNOR:OHTAKI, MIKIO;REEL/FRAME:010387/0317

Effective date: 19990826

AS Assignment

Owner name: OKI ELECTRIC INDUSTRY CO., LTD., JAPAN

Free format text: (ASSIGNMENT OF ASSIGNOR'S INTEREST) RE-RECORD TO CORRECT THE RECORDATION DATE OF 11-4-99 TO 11-5-99 PREVIOUSLY RECORDED AT REEL 10387, FRAME 0317.;ASSIGNOR:OHTAKI, MIKIO;REEL/FRAME:010754/0183

Effective date: 19990826

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: OKI SEMICONDUCTOR CO., LTD., JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:022343/0290

Effective date: 20081001

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
AS Assignment

Owner name: LAPIS SEMICONDUCTOR CO., LTD., JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:OKI SEMICONDUCTOR CO., LTD;REEL/FRAME:032495/0483

Effective date: 20111003

LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20140618