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Publication numberUS20010055834 A1
Publication typeApplication
Application numberUS 09/925,688
Publication dateDec 27, 2001
Filing dateAug 10, 2001
Priority dateJun 21, 2000
Also published asUS6455353
Publication number09925688, 925688, US 2001/0055834 A1, US 2001/055834 A1, US 20010055834 A1, US 20010055834A1, US 2001055834 A1, US 2001055834A1, US-A1-20010055834, US-A1-2001055834, US2001/0055834A1, US2001/055834A1, US20010055834 A1, US20010055834A1, US2001055834 A1, US2001055834A1
InventorsChun Lin
Original AssigneeAdvanced Semiconductor Engineering, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method of making semiconductor packages at wafer level
US 20010055834 A1
Abstract
A method of manufacturing chip scale packages at wafer level, comprising the steps of: a) providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines defining individual chips, and each chip having a plurality of electrodes; b) forming a dam enclosing the perimeter of the wafer; c) filling the area enclosed by the dam with molding compound to encapsulate the active surface of the wafer; d) removing the dam to expose the scribe lines covered by the dam on the active surface of the wafer; and e) dicing the wafer according to the exposed scribe lines as positioning reference marks.
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Claims(12)
What is claimed is:
1. A method of manufacturing chip scale packages at wafer level, comprising the steps of:
a) providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines defining individual chips, and each chip having a plurality of electrodes;
b) forming a dam enclosing the perimeter of the wafer;
c) filling the area enclosed by the dam with molding compound to encapsulate the active surface of the wafer;
d) removing the dam to expose the scribe lines covered by the dam on the active surface of the wafer; and
e) dicing the wafer to form individual chips according to the exposed scribe lines as positioning reference marks.
2. The method of manufacturing chip scale packages at wafer level as claimed in
claim 1
, wherein the dam is made from a high viscosity and thixotropy material.
3. The method of manufacturing chip scale packages at wafer level as claimed in
claim 1
, wherein the ratio of the width to height on the cross section of the dam is 3:1.
4. The method of manufacturing chip scale packages at wafer level as claimed in
claim 1
, further comprising a step of:
grinding the molding compound on the wafer to expose the electrodes out of the molding compound.
5. The method of manufacturing chip scale packages at wafer level as claimed in
claim 1
, further comprising a step of:
grinding the back side of the wafer to a thickness within a predetermined range.
6. The method of manufacturing chip scale packages at wafer level as claimed in
claim 1
, wherein the molding compound is filled by spin coating process to encapsulate the active surface of the wafer.
7. A method of manufacturing chip scale packages at wafer level, comprising the steps of:
a) providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines defining individual chips, and each chip having a plurality of electrodes;
b) forming a dam spaced a predetermined distance from the perimeter of the wafer to expose the scribe lines;
c) filling the area enclosed by the dam with molding compound to encapsulate the active surface of the wafer; and
d) dicing the wafer according to the exposed scribe lines as positioning reference marks.
8. The method of manufacturing chip scale packages at wafer level as claimed in
claim 7
, wherein the dam is made from a high viscosity and thixotropy material.
9. The method of manufacturing chip scale packages at wafer level as claimed in
claim 1
, wherein the ratio of the width to height on the cross section of the dam is 3:1.
10. The method of manufacturing chip scale packages at wafer level as claimed in
claim 7
, further comprising a step of:
grinding the molding compound on the wafer to expose the electrodes out of the molding compound.
11. The method of manufacturing chip scale packages at wafer level as claimed in
claim 7
, further comprising a step of:
grinding the back side of the wafer to a thickness within a predetermined range.
12. The method of manufacturing chip scale packages at wafer level as claimed in
claim 7
, wherein the molding compound is filled by spin coating process to encapsulate the active surface of the wafer.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to a chip scale package (CSP), and more particularly, to a method of manufacturing chip scale package at wafer level for accurately dividing the wafer into individual chips.

[0003] 2. Description of the Related Art

[0004] As electronic devices have become smaller and thinner, the velocity and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher package efficiency. Demand for miniaturization is the primary catalyst driving the usage of advanced packages such as chip scale packages (CSP). As compared to the ball grid array (BGA) package and thin small outline package (TSOP), the chip scale package significantly increases the packaging efficiency and has several advantages. For example, the CSP package is slightly larger than the chip, and typically, the CSP is about 20 percent larger than the chip itself. Another advantage of CSP is that the package facilitates test and burn-in before assembly as an alternative to known good die(KGD) testing. In addition, CSP can combine many of the benefits of surface mount technology (SMT), such as standardization, encapsulation, surface mount, and re-workability, with the benefits of flip chip technology, such as low inductance, high I/O count, and direct thermal path.

[0005] However, CSP has at least one disadvantage compared to conventional BGA and TSOP, namely, high cost per unit. However, this problem could be eliminated if chip-sized packages could be mass produced more easily. Therefore, there is a need in the semiconductor packaging industry for CSP using mass production techniques at the wafer-level, as is illustrated in U.S. Pat. No. 5,323,051, U.S. Pat. No. 5,925,936 and U.S. Pat. No. 6,004,867.

[0006] For the methods of making the chip scale package at the wafer level disclosed in U.S. Pat. No. 5,323,051 and the U.S. Pat. No. 5,925,936, the methods substantially comprise the steps of: a) encapsulating an active surface of a wafer; b) grinding the encapsulated wafer to expose the bumps on the active surface of the wafer and to obtain the predetermined thickness; and c) dicing the encapsulated wafer according to the exposed bump as positioning reference marks.

[0007] In the above mentioned patents, because the scribe lines is covered by molding compound on the wafer surface after encapsulating, the exposed bumps are utilized as the positioning reference marks for dicing the encapsulated wafer. But the exposed bumps of the individual chip or dice is too tiny to provide an obvious positioning reference mark which is easily detected by the positioning device of the dicing machine or apparatus. Hence, the positioning device of the dicing machine or apparatus is often positioned in error.

[0008] U.S. Pat. No. 6,004,867, entitled “Chip-size Package Assembled Using Mass Production Techniques At The Wafer-Level” issued on Dec. 21, 1999 to Kim et al., discloses a chip-size package technique at wafer level, wherein a substrate is attached to an active surface of a packaged wafer, the substrate includes grooves or index patterns corresponding to the scribe lines, and the grooves or index patterns in the substrate will be exposed by grinding such that the exposed grooves or index patterns are utilized as positioning reference marks for dicing the wafer. However, according to the process of Kim's 867 Patent, the wafer requires additional attachment of the substrate for dicing, which fails to fulfill the requirements of chip scale package.

[0009] Hence, a need exists for a semiconductor package that provides a method of making the chip scale package at the wafer level to retain obvious scribe lines after the wafer is encapsulated by molding compound such that the dicing machine can be easily and accurately positioned in dicing process of the chip scale package so as to overcome the above mentioned drawback.

SUMMARY OF THE INVENTION

[0010] It is a primary object of the present invention to provide a method of manufacturing chip scale package at the wafer level for mass production so as to reduce the cost of manufacturing chip scale package.

[0011] It is another object of the present invention to provide a method of manufacturing chip scale package at the wafer level to retain obvious scribe lines after the wafer is encapsulated by molding compound such that the dicing machine can be easily and accurately positioned in dicing process of the chip scale package.

[0012] In order to achieve the objects mentioned hereinabove, the method of manufacturing chip scale packages at wafer level according to an embodiment of the present invention comprises the step of:

[0013] a) providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines to defining individual chips, and each chip having a plurality of electrodes;

[0014] b) forming a dam enclosing the perimeter of the wafer;

[0015] c) filling the area enclosed by the dam with molding compound to encapsulate the active surface of the wafer;

[0016] d) removing the dam to expose the covered scribe lines on the active surface of the wafer; and

[0017] e) dicing the wafer according to the exposed scribe lines as positioning reference marks.

[0018] According to another embodiment of the present invention, the dam is form on the active surface of the wafer spaced a predetermined distance from the perimeter of the wafer to expose the scribe lines such that the scribe lines will be exposed without removing the dam.

[0019] Therefore, since the method of manufacturing chip scale packages at wafer level according to the present invention will expose the scribe lines during the manufacturing process, the wafer can be accurately diced according to the exposed scribe lines as positioning reference marks.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

[0021]FIG. 1a is a plan view showing a wafer according to the present invention.

[0022]FIG. 1b is a partially enlarged sectional view of the chip shown in FIG. 1a.

[0023]FIG. 2 is a schematic view showing the step of forming the dam enclosing the perimeter of the wafer according to a first embodiment of the present invention.

[0024]FIG. 3 is a schematic view showing the step of encapsulating the wafer with molding according to the first embodiment of the present invention.

[0025]FIG. 4 is a schematic view showing the wafer after the dam being removed according to the first embodiment of the present invention.

[0026]FIG. 5 is a schematic view showing the step of encapsulating the wafer with molding according to a second embodiment of the present invention.

[0027]FIG. 6 is a schematic view showing the wafer after the dam being removed according to the second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0028] The present invention relates to a method of mass-producing chip scale package at wafer level so as to reduce the cost of manufacturing chip scale package. Now the preferable embodiments according to the present invention will be described in detail while taken in conjunction with the accompanying drawings. In the accompanying drawings, like reference numbers refer to corresponding parts throughout.

[0029]FIG. 1a depicts a top plan view of a wafer 10 according to the present invention. The wafer 10 has a plurality of chips 11 and a plurality of scribe lines 13 located between the chips 11. FIG. 1b is a partially enlarged sectional view of the chip 11 shown in FIG. 1a, in which each of the chips 11 is provided with a plurality of bumps or electrodes 12 on the active surface thereof. The electrodes 12 are formed by electroplating on the electrode terminals of the chips 11, and the electrodes 12 is made of conductive metal material, such as solder or gold, which can be connected with a substrate by soldering.

[0030] Now referring to FIG. 2, the area for effective chips of the wafer 10 is enclosed by dash lines 15 and a dispenser 17 is used to dispense the dam material along the perimeter 21 of the wafer 10 to form a dam 23 surrounding the perimeter 21 of the wafer 10. The material of the dam 23 will be selected to provide substantial viscosity and thixotropic, such as high viscosity epoxy, so as to control the aspect ratio of the dam 23. The typical aspect ratio of the dam 23 is 3:1. Once the material of dam 23 is selected, the dispensing speed of the dispenser 17 can be optimum and the dispensing speed will have some influences on the dam's aspect ratio.

[0031] Referring to FIG. 3, after the dam 23 encloses the entire perimeter 21 of the wafer 10, another dispenser 19 will be provided to dispense the molding compound 41. The molding compound 41 has lower viscosity and contains less filler particles so as to fill the area enclosed by the dam 23 and cover the electrodes 12 to encapsulate the wafer 10. It will be appreciated by those skilled in this art that the molding compound 41 can be applied onto the active surface of the wafer 10 by other manners. For example, the spin coating method can be used to dispense the molding compound 41 on the rotating wafer 10 and the active surface of the wafer 10 will be uniformly encapsulated with the molding compound 41 by means of the centrifugal force of the rotation of the wafer 10.

[0032] It should be noted that, according to the embodiment of the present invention, after the molding compound 41 and the dam 23 are cured, a separating interface will form therebetween, and thus the dam 23 can be removed easily from the wafer 10 and the molding compound 41 can retain its integrity for encapsulating the wafer 10 (as shown in FIG. 4).

[0033] Referring to FIG. 4, after the dam 23 is removed, the scribe lines 13 covered by the dam 23 on the perimeter 21 of the wafer 10 will be exposed. Therefore, the cutting tools can accurately dice the wafer 10 to form individual chips 11 according to the exposed scribe lines 13 as positioning reference marks. It should be appreciated by those skilled in this art that before the wafer 10 is diced, the molding compound 41 and the back side surface of the wafer 10 shall be ground to expose the electrodes 12 and to make the thickness of the wafer 10 to be within a predetermined range.

[0034] Now referring to FIG. 5 and 6, they depict a manufacturing process according to the second embodiment of the present invention which is generally similar to the first embodiment of the present invention and where the similar parts are indicated by similar reference characters. The difference between the first and the second embodiments lies in that the aspect ratio of the dam 23 a of the second embodiment is smaller than that of the dam 23 of the first embodiment, i.e., the ratio of the width to height on the cross section of the dam 23 a is smaller than that on the dam 23. The width of the dam 23 a is smaller than that of the dam 23 while the height of the dam 23 and the height of the dam 23 a are the same (as shown in FIG. 5). Therefore, the dam 23 a will not fully cover the perimeter 21 of the wafer 10 and will encircle the wafer 10 with a distance spaced from the perimeter 21.

[0035] As shown in FIG. 6, the wafer 10 is further encapsulated by the molding compound 41 a. Since the dam 23 a is spaced from the perimeter 21 of the wafer 10, the scribe lines 13 will not be covered after encapsulated by molding compound 41 a, and thus the wafer 10 can be accurately diced to form individual chips 11 according to the scribe lines 13 as positioning reference marks.

[0036] Similarly, it also will be appreciated that the wafer of this embodiment still shall be ground to expose the electrodes 12 and to make the thickness of the wafer 10 to be within a predetermined range.

[0037] As described hereinabove, the present invention provides a method of manufacturing chip scale package at wafer level in which the scribe lines can still be keep visibly after the chip scale package at wafer level is encapsulated by the molding compound so as to accurately dice the wafer to form individual chips according to the scribe lines as positioning reference marks. Therefore, the method according to the present invention can be used to mass-produce chip scale package at wafer level to reduce the cost of manufacturing chip scale package.

[0038] Although the invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7489020Apr 27, 2006Feb 10, 2009Micron Technology, Inc.Semiconductor wafer assemblies
US7615119Apr 27, 2006Nov 10, 2009Micron Technology, Inc.Apparatus for spin coating semiconductor substrates
US7960829Aug 31, 2005Jun 14, 2011Micron Technology, Inc.Support structure for use in thinning semiconductor substrates and for supporting thinned semiconductor substrates
US7972904 *Apr 14, 2009Jul 5, 2011Powertech Technology Inc.Wafer level packaging method
Classifications
U.S. Classification438/106, 257/E21.502
International ClassificationH01L23/31, H01L21/56
Cooperative ClassificationH01L21/56, H01L23/3114, H01L2924/01079, H01L2224/274
European ClassificationH01L21/56, H01L23/31H1
Legal Events
DateCodeEventDescription
Mar 24, 2014FPAYFee payment
Year of fee payment: 12
Mar 24, 2010FPAYFee payment
Year of fee payment: 8
Mar 24, 2006FPAYFee payment
Year of fee payment: 4
Aug 10, 2001ASAssignment
Owner name: ADVANCED SEMICONDUCTOR ENGINEERING, INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LIN, CHUN HUNG;REEL/FRAME:012070/0420
Effective date: 20010725
Owner name: ADVANCED SEMICONDUCTOR ENGINEERING, INC. NO. 26, C
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LIN, CHUN HUNG /AR;REEL/FRAME:012070/0420