|Publication number||US20010056353 A1|
|Application number||US 08/851,574|
|Publication date||Dec 27, 2001|
|Filing date||May 2, 1997|
|Priority date||May 2, 1997|
|Also published as||US6310652|
|Publication number||08851574, 851574, US 2001/0056353 A1, US 2001/056353 A1, US 20010056353 A1, US 20010056353A1, US 2001056353 A1, US 2001056353A1, US-A1-20010056353, US-A1-2001056353, US2001/0056353A1, US2001/056353A1, US20010056353 A1, US20010056353A1, US2001056353 A1, US2001056353A1|
|Inventors||Stephen (Hsiao Yi) Li, Frank L. Laczko Sr., Jonathan Rowlands, Paul Look|
|Original Assignee||Gerald Laws|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (5), Classifications (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
 This invention relates in general to the field of electronic systems and more particularly to an improved modular audio data processing architecture and method of operation.
 Audio and video data compression for digital transmission of information will soon be used in large scale transmission systems for television and radio broadcasts as well as for encoding and playback of audio and video from such media as digital compact cassette and minidisc.
 The Motion Pictures Expert Group (MPEG) has promulgated the MPEG audio and video standards for compression and decompression algorithms to be used in the digital transmission and receipt of audio and video broadcasts in ISO-11172 (hereinafter the “MPEG Standard”). The MPEG Standard provides for the efficient compression of data according to an established psychoacoustic model to enable real time transmission, decompression and broadcast of CD-quality sound and video images. The MPEG standard has gained wide acceptance in satellite broadcasting, CD-ROM publishing, and DAB. The MPEG Standard is useful in a variety of products including digital compact cassette decoders and encoders, and minidisc decoders and encoders, for example. In addition, other audio standards, such as the Dolby AC-3 standard, involve the encoding and decoding of audio and video data transmitted in digital format.
 The AC-3 standard has been adopted for use on laser disc, digital video disk (DVD), the US ATV system, and some emerging digital cable systems. The two standards potentially have a large overlap of application areas.
 Both of the standards are capable of carrying up to five full channels plus one bass channel, referred to as “5.1 channels,” of audio data and incorporate a number of variants including sampling frequencies, bit rates, speaker configurations, and a variety of control features. However, the standards differ in their bit allocation algorithms, transform length, control feature sets, and syntax formats.
 Both of the compression standards are based on psycho-acoustics of the human perception system. The input digital audio signals are split into frequency subbands using an analysis filter bank. The subband filter outputs are then downsampled and quantized using dynamic bit allocation in such a way that the quantization noise is masked by the sound and remains imperceptible. These quantized and coded samples are then packed into audio frames that conform to the respective standard's formatting requirements. For a 5.1 channel system, high quality audio can be obtained for compression ratio in the range of 10:1.
 The transmission of compressed digital data uses a data stream that may be received and processed at rates up to 15 megabits per second or higher. Prior systems that have been used to implement the MPEG decompression operation and other digital compression and decompression operations have required expensive digital signal processors and extensive support memory. Other architectures have involved large amounts of dedicated circuitry that are not easily adapted to new digital data compression or decompression applications.
 An object of the present invention is provide an improved apparatus and methods of processing MPEG, AC-3 or other streams of data.
 Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.
 In general, and in a form of the present invention a data processing device for processing a stream of data is provided which can make fine grain adjustments in the transfer rate of the stream of stream of data so that a specified presentation time is synchronized with a reference time. The data stream is organized in frames of data and a processing unit within the processing device has a means for determining a presentation time associated with a frame of data. The processing unit also has means for determining a reference time. The processing unit compares the reference time to the presentation time and determines a time difference. If the time difference indicates that the presentation time is earlier than the reference time, then only a portion of the frame is transferred so that a following frame of data will more synchronized with a following reference time.
 In another form of the invention, if the time difference indicates that the presentation time is later that the reference time, then a portion of the frame is transmitted a second time so that a following frame of data will more synchronized with a following reference time.
 Other embodiments of the present invention will be evident from the description and drawings.
 Other features and advantages of the present invention will become apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:
FIG. 1 is a block diagram of a data processing device constructed in accordance with aspects of the present invention;
FIG. 2 is a more detailed block diagram of the data processing device of FIG. 1, illustrating interconnections of a Bit-stream Processing Unit and an Arithmetic Unit;
FIG. 3 is a block diagram of the Bit-stream Processing Unit of FIG. 2;
FIG. 4 is a block diagram of the Arithmetic Unit of FIG. 2;
FIG. 5 is a block diagram illustrating the architecture of the software which operates on the device of FIG. 1;
FIG. 6 is a block diagram illustrating an audio reproduction system which includes the data processing device of FIG. 1;
FIG. 7 is a block diagram of an integrated circuit which includes the data processing device of FIG. 1 in combination with other data processing devices, the integrated circuit being connected to various external devices;
FIG. 8 is a block diagram of a breakpoint circuit, according to the present invention;
FIG. 9 is a schematic diagram of a breakpoint circuit;
FIG. 10 illustrates a prior art stream of data which contains a presentation time stamp in a header associated with each frame of data;
FIG. 11A illustrates a situation in which a presentation time has fallen behind a reference time and only a partial frame of data is transmitted, according to an aspect of the present invention;
FIG. 11B illustrates a situation in which a presentation time is ahead of a reference time and a partial frame of data is transmitted a second time, according to an aspect of the present invention;
FIG. 12 is an illustration of a frame of data in a data buffer, showing various breakpoint addresses corresponding to FIGS. 9A-9B; and
FIG. 13 illustrates a means for comparing a presentation time to a reference time, according to an aspect of the present invention.
 Corresponding numerals and symbols in the different figures and tables refer to corresponding parts unless otherwise indicated.
 Aspects of the present invention include methods and apparatus for processing and decompressing an audio data stream. In the following description, specific information is set forth to provide a thorough understanding of the present invention. Well known circuits and devices are included in block diagram form in order not to complicate the description unnecessarily. Moreover, it will be apparent to one skilled in the art that specific details of these blocks are not required in order to practice the present invention.
 The present invention comprises a system that is operable to efficiently decode a stream of data that has been encoded and compressed using any of a number of encoding standards, such as those defined by the Moving Pictures Expert Group (MPEG-1 or MPEG-2), or the Digital Audio Compression Standard (AC-3), for example. In order to accomplish the real time processing of the data stream, the system of the present invention must be able to receive a bit stream that can be transmitted at variable bit rates up to 15 megabits per second and to identify and retrieve a particular audio data set that is time multiplexed with other data within the bit stream. The system must then decode the retrieved data and present conventional pulse code modulated (PCM) data to a digital to analog converter which will, in turn, produce conventional analog audio signals with fidelity comparable to other digital audio technologies. The system of the present invention must also monitor synchronization within the bit stream and synchronization between the decoded audio data and other data streams, for example, digitally encoded video images associated with the audio which must be presented simultaneously with decoded audio data. In addition, MPEG or AC-3 data streams can also contain ancillary data which may be used as system control information or to transmit associated data such as song titles or the like. The system of the present invention must recognize ancillary data and alert other systems to its presence.
 In order to appreciate the significance of aspects of the present invention, the architecture and general operation of a data processing device which meets the requirements of the preceding paragraph will now be described. Referring to FIG. 1, which is a block diagram of a data processing device 100 constructed in accordance with aspects of the present invention, the architecture of data processing device 100 is illustrated. The architectural hardware and software implementation reflect the two very different kinds of tasks to be performed by device 100: decoding and synthesis. In order to decode a steam of data, device 100 must unpack variable length encoded pieces of information from the stream of data. Additional decoding produces set of frequency coefficients. The second task is a synthesis filter bank that converts the frequency domain coefficients to PCM data. In addition, device 100 also needs to support dynamic range compression, downmixing, error detection and concealment, time synchronization, and other system resource allocation and management functions.
 The design of device 100 includes two autonomous processing units working together through shared memory supported by multiple I/O modules. The operation of each unit is data-driven. The synchronization is carried out by the Bit-stream Processing Unit (BPU) which acts as the master processor. Bit-stream Processing Unit (BPU) 110 has a RAM 111 for holding data and a ROM 112 for holding instructions which are processed by BPU 110. Likewise, Arithmetic Unit (AU) 120 has a RAM 121 for holding data and a ROM 122 for holding instructions which are processed by AU 120. Data input interface 130 receives a stream of data on input lines DIN which is to be processed by device 100. PCM output interface 140 outputs a stream of PCM data on output lines PCMOUT which has been produced by device 100. Inter-Integrated Circuit (I2C) Interface 150 provides a mechanism for passing control directives or data parameters on interface lines 151 between device 100 and other control or processing units, which are not shown, using a well known protocol. Bus switch 160 selectively connects address/data bus 161 to address/data bus 162 to allow BPU 110 to pass data to AU 120.
FIG. 2 is a more detailed block diagram of the data processing device of FIG. 1, illustrating interconnections of Bit-stream Processing Unit 110 and Arithmetic Unit 120. A BPU ROM 113 for holding data and coefficients and an AU ROM 123 for holding data and coefficients is also shown.
 A typical operation cycle is as follows: Coded data arrives at the Data Input Interface 130 asynchronous to device 100's system clock, which operates at 27 MHz. Data Input Interface 130 synchronizes the incoming data to the 27 MHz device clock and transfers the data to a buffer area 114 in BPU memory 111 through a direct memory access (DMA) operation. BPU 110 reads the compressed data from buffer 114, performs various decoding operations, and writes the unpacked frequency domain coefficients to AU RAM 121, a shared memory between BPU and AU. Arithmetic Unit 120 is then activated and performs subband synthesis filtering, which produces a stream of reconstructed PCM samples which are stored in output buffer area 124 of AU RAM 121. PCM Output Interface 140 receives PCM samples from output buffer 124 through a DMA transfer and then formats and outputs them to an external D/A converter. Additional functions performed by the BPU include control and status I/O, as well as overall system resource management.
FIG. 3 is a block diagram of the Bit-stream Processing Unit of FIG. 2. BPU 110 is a programmable processor with hardware acceleration and instructions customized for audio decoding. It is a 16-bit reduced instruction set computer (RISC) processor with a register-to-register operational unit 200 and an address generation unit 220 operating in parallel. Operational unit 200 includes a register file 201 an arithmetic/logic unit 202 which operates in parallel with a funnel shifter 203 on any two registers from register file 201, and an output multiplexer 204 which provides the results of each cycle to input mux 205 which is in turn connected to register file 201 so that a result can be stored into one of the registers.
 BPU 110 is capable of performing an ALU operation, a memory I/O, and a memory address update operation in one system clock cycle. Three addressing modes: direct, indirect, and registered are supported. Selective acceleration is provided for field extraction and buffer management to reduce control software overhead. Table 1 is a list of the instruction set.
TABLE 1 BPU Instruction Set Instruction Mnemonics Functional Description And Logical and Or Logical or cSat Conditional saturation Ash Arithmetic shift LSh Logical shift RoRC Rotate right with carry GBF Get bit-field Add Add AddC Add with carry cAdd Conditional add Xor Logical exclusive or Sub Subtract SubB Subtract with borrow SubR Subtract reversed Neg 2's complement cNeg Conditional 2's complement Bcc Conditional branch DBcc Decrement & conditional branch IOST IO reg to memory move IOLD Memory to IO reg move auOp AU operation - loosely coupled auEx AU execution - tightly coupled Sleep Power down unit
 BPU 110 has two pipeline stages: Instruction Fetch/Predecode which is performed in Micro Sequencer 230, and Decode/Execution which is performed in conjunction with instruction decoder 231. The decoding is split and merged with the Instruction Fetch and Execution respectively. This arrangement reduces one pipeline stage and thus branching overhead. Also, the shallow pipe operation enables the processor to have a very small register file (four general purpose registers, a dedicated bit-stream address pointer, and a control/status register) since memory can be accessed with only a single cycle delay.
FIG. 4 is a block diagram of the Arithmetic Unit of FIG. 2. Arithmetic unit 120 is a programmable fixed point math processor that performs the subband synthesis filtering. A complete description of subband synthesis filtering is provided in U.S. Pat. No. ______, (U.S. patent application Ser. No. 08/475,251 entitled Integrated Audio Decoder System And Method Of Operation or U.S. patent application Ser. No. 08/054,768 entitled Hardware Filter Circuit And Address Circuitry For MPEG Encoded Data, both assigned to the assignee of the present application), which is included herein by reference; in particular, FIGS. 7-9 and 11-31 and related descriptions.
 The AU 120 module receives frequency domain coefficients from the BPU by means of shared AU memory 121. After the BPU has written a block of coefficients into AU memory 121, the BPU activates the AU through a coprocessor instruction, auOp. BPU 110 is then free to continue decoding the audio input data. Synchronization of the two processors is achieved through interrupts, using interrupt circuitry 240 (shown in FIG. 3).
 AU 120 is a 24-bit RISC processor with a register-to-register operational unit 300 and an address generation unit 320 operating in parallel. Operational unit 300 includes a register file 301, a multiplier unit 302 which operates in conjunction with an adder 303 on any two registers from register file 301. The output of adder 303 is provided to input mux 305 which is in turn connected to register file 301 so that a result can be stored into one of the registers.
 A bit-width of 24 bits in the data path in the arithmetic unit was chosen so that the resulting PCM audio will be of superior quality after processing. The width was determined by comparing the results of fixed point simulations to the results of a similar simulation using double-precision floating point arithmetic. In addition, double-precision multiplies are performed selectively in critical areas within the subband synthesis filtering process.
FIG. 5 is a block diagram illustrating the architecture of the software which operates on data processing device 100. Each hardware component in device 100 has an associated software component, including the compressed bit-stream input, audio sample output, host command interface, and the audio algorithms themselves. These components are overseen by a kernel that provides real-time operation using interrupts and software multi-tasking.
 The software architecture block diagram is illustrated in FIG. 5. Each of the blocks corresponds to one system software task. These tasks run concurrently and communicate via global memory 111. They are scheduled according to priority, data availability, and synchronized to hardware using interrupts. The concurrent data-driven model reduces RAM storage by allowing the size of a unit of data processed to be chosen independently for each task.
 The software operates as follows. Data Input Interface 410 buffers input data and regulates flow between the external source and the internal decoding tasks. Transport Decoder 420 strips out packet information from the input data and emits a raw AC-3 or MPEG audio bit-stream, which is processed by Audio Decoder 430. PCM Output Interface 440 synchronizes the audio data output to a system-wide absolute time reference and, when necessary, attempts to conceal bit-stream errors. I2C Control Interface 450 accepts configuration commands from an external host and reports device status. Finally, Kernel 400 responds to hardware interrupts and schedules task execution.
FIG. 6 is a block diagram illustrating an audio reproduction system 500 which includes the data processing device of FIG. 1. Stream selector 510 selects a transport data stream from one or more sources, such as a cable network system 511, digital video disk 512, or satellite receiver 513, for example. A selected stream of data is then sent to transport decoder 520 which separates a stream of audio data from the transport data stream according to the transport protocol, such as MPEG or AC-3, for that stream. Transport decoder typically recognizes a number of transport data stream formats, such as direct satellite system (DSS), digital video disk (DVD), or digital audio broadcasting (DAB), for example. The selected audio data stream is then sent to data processing device 100 via input interface 130. Device 100 unpacks, decodes, and filters the audio data stream, as discussed previously, to form a stream of PCM data which is passed via PCM output interface 140 to D/A device 530. DIA device 530 then forms at least one channel of analog data which is sent to a speaker subsystem 540 a. Typically, A/D 530 forms two channels of analog data for stereo output into two speaker subsystems 540 a and 540 b. Processing device 100 is programmed to downmix an MPEG-2 or AC-3 system with more than two channels, such as 5.1 channels, to form only two channels of PCM data for output to stereo speaker subsystems 540 a and 540 b.
 Alternatively, processing device 100 can be programmed to provide up to six channels of PCM data for a 5.1 channel sound reproduction system if the selected audio data stream conforms to MPEG-2 or AC-3. In such a 5.1 channel system, D/A 530 would form six analog channels for six speaker subsystems 540 a-n. Each speaker subsystem 540 contains at least one speaker and may contain an amplification circuit (not shown) and an equalization circuit (not shown).
 The SPDIF (Sony/Philips Digital Interface Format) output of device 100 conforms to a subset of the Audio Engineering Society's AES3 standard for serial transmission of digital audio data. The SPDIF format is a subset of the minimum implementation of AES3. This stream of data can be provided to another system (not shown) for further processing or re-transmission.
 Referring now to FIG. 7 there may be seen a functional block diagram of a circuit 300 that forms a portion of an audio-visual system which includes aspects of the present invention. More particularly, there may be seen the overall functional architecture of a circuit including on-chip interconnections that is preferably implemented on a single chip as depicted by the dashed line portion of FIG. 7. As depicted inside the dashed line portion of FIG. 7, this circuit consists of a transport packet parser (TPP) block 610 that includes a bit-stream decoder or descrambler 612 and clock recovery circuitry 614, an ARM CPU block 620, a data ROM block 630, a data RAM block 640, an audio/video (A/V) core block 650 that includes an MPEG-2 audio decoder 654 and an MPEG-2 video decoder 652, an NTSC/PAL video encoder block 660, an on screen display (OSD) controller block 670 to mix graphics and video that includes a bit-blt hardware (HJW) accelerator 672, a communication coprocessor (CCP) block 680 that includes connections for two UART serial data interfaces, infra red (IR) and radio frequency (RF) inputs, SIRCS input and output, an I2C port and a Smart Card interface, a P1394 interface (I/F) block 690 for connection to an external 1394 device, an extension bus interface (I/F) block 700 to connect peripherals such as additional RS232 ports, display and control panels, external ROM, DRAM, or EEPROM memory, a modem and an extra peripheral, and a traffic controller (TC) block 710 that includes an SRAM/ARM interface (I/F) 712 and a DRAM I/F 714. There may also be seen an internal 32 bit address bus 320 that interconnects the blocks and seen an internal 32 bit data bus 730 that interconnects the blocks. External program and data memory expansion allows the circuit to support a wide range of audio/video systems, especially, as for example, but not limited to set-top boxes, from low end to high end.
 The consolidation of all these functions onto a single chip with a large number of communications ports allows for removal of excess circuitry and/or logic needed for control and/or communications when these functions are distributed among several chips and allows for simplification of the circuitry remaining after consolidation onto a single chip. Thus, audio decoder 354 is the same as data processing device 100 with suitable modifications of interfaces 130, 140, 150 and 170. This results in a simpler and cost-reduced single chip implementation of the functionality currently available only by combining many different chips and/or by using special chipsets.
 A novel aspect of data processing device 100 will now be discussed in detail, with reference to FIGS. 8 and 9. Input buffer 114 (FIG. 2) is managed by data input interface software module 400 (FIG. 5) using breakpoint interrupts, as illustrated in FIG. 8. PCM output buffer 124 is likewise managed by PCM output interface software 440 using breakpoint interrupts. Hardware interrupts are valuable for signaling events between software tasks in cases where the conditions that cause the event are dispersed throughout the system. Device 110 makes use of interrupts for bit-stream input buffer management. There are many special conditions associated with the input buffer read function, including:
 buffer empty
 buffer circular wraparound
 bit-stream demultiplex boundary
 known bit-stream error location
 Likewise, device 110 makes use of interrupts for PCM output buffer management. Several conditions are associated with the output buffer, including buffer empty and synchronization correction, which will be discussed in more detail with reference to FIG. 10. These conditions must be tested for each read by BPU 110 from the PCM output buffer 124. Due to the necessarily short execution time of the buffer read operation and the large number of different places it is performed, some centralized hardware assist is desirable. In device 110 this takes the form of a single hardware data breakpoint register for the output buffer read function, which generates a hardware interrupt whenever a target address in the output buffer is accessed. The mechanism allows the bit-stream syntax decode and buffer management functions to be largely decoupled, which improves run-time efficiency and software design, maintenance and testing. FIG. 8 illustrates the data breakpoint scheme for the output bit-stream buffer management.
 Each of the conditions which might cause a breakpoint interrupt are associated with a different address in the output buffer, and many conditions may be “active” simultaneously. Since the PCM output buffer is predominantly accessed in FIFO order, data breakpoint events will in general be triggered in order of increasing address. This allows a single breakpoint register to be used for multiple events, if it always contains the address of the next breakpoint. Software source tasks 801 a-n maintain a sorted queue of breakpoint events for this purpose.
 Still referring to FIG. 8, as discussed above, the output breakpoint interrupt can be used to manage the circular output buffer 124 in AU RAM 121. This could also be done using the table lookup addressing mode, but in that case the input buffer is restricted to a power of two size. Using the breakpoint interrupt handler to wrap the read pointer allows the size of the buffer to be optimized for the determined worst case buffer conditions. This is done by placing the ending address of buffer 124 in the breakpoint queue. Update task 802 will then place this address in breakpoint register 810 so that an interrupt will occur when the last word in input buffer 114 is accessed.
 Two additional data breakpoint registers, similar to register 810 in FIG. 8, are associated with reads and writes to bit-stream input buffer 114. These are used to signal the end of a DMA write transfer condition and to manage buffer read conditions, as listed above. In the case of the input buffer write function, there are again several possible sources of events, including buffer full and buffer circular wraparound. These can be managed using the same techniques as for buffer read.
FIG. 9 is a schematic of a breakpoint circuit, according to the present invention. Read breakpoint register 900 is connected to data bus 161 b so that it can be loaded with a read breakpoint address. Likewise, write breakpoint register 902 is connected to data bus 161 b so that it can be loaded with a write breakpoint address. Both registers are memory mapped in the address space of address bus 161 a. A comparator 901 is connected to the output of register 900 and to address bus 161 a and is operable to compare addresses placed on the address bus to the value of the read breakpoint address stored in register 900. When an address which is equal to the read breakpoint address is detected during a read transaction, this condition is stored in a bit in interrupt flag shadow register IFS. If interrupt enable signal IEO is true, then an interrupt request is formed and stored in status register R7. An interrupt request signal IRQ which is the “OR” of all enabled pending interrupts is formed by gate 904 and sent to interrupt logic 240, on FIG. 3. Status register R7 is described in more detail later.
 A comparator 903 operates in a similar manner with write breakpoint register 902. A separate bit in status register R7 is used to record a write breakpoint interrupt so that software executing on BPU 110 can respond to read and write breakpoint interrupts appropriately. BPU 110 checks status register R7 in response to an interrupt request in order to determine the source of the interrupt. This is done via bus 907 which is connected to ALU 202, in FIG. 3.
 Status register R7 can be read and written by BPU 110 just as any other register in register file 201. As discussed above, various bits in register R7 is also set by pending interrupt requests and by various status conditions. Table 2 defines the bits in R7.
TABLE 2 Status Register Bits BIT MNEM DESCRIPTION 0-5 IF interrupt pending flags 6-11 IE interrupt enable flags 12 ID interrupt disable flag 13 C carry 14 Z zero 15 N negative
 There are six sources of interrupts in BPU 110. These are vectored to a single master interrupt handler which examines the interrupt flags and branches to the appropriate handler. The six sources are:
 input buffer read breakpoint
 input buffer full—write breakpoint
 PCM output buffer empty (a read breakpoint similar to input read breakpoint)
 I2C interface
 arithmetic unit operation complete
 real-time failure
 Status register R7 contains all the interrupt control bits. A single global interrupt disable bit (ID) optionally prevents interrupts from being acknowledged. Individual interrupt enable (IEO-5) bits enable or disable each source if interrupts are enabled globally. Finally, individual interrupt flags (IFO-5) indicate whether an interrupt is pending for each source.
 The IF bits which appear in the status register are the logical “and” of the internal interrupt pending bit (the IF bit “shadow”—IFS) and the IE bit for the source. Additionally, a single bit I/O enable register (EN) globally enables and disables interrupts and DMA. This provides a way to protect critical sections of code against background operations with low overhead.
 When one or more interrupt requests occur during a cycle, the following events occur:
 1. if the IFS bit for a requesting interrupt is set, this indicates that an earlier interrupt of the same type has not yet been serviced. A real-time failure interrupt request is generated in this case.
 2. each requesting interrupt sources' IFS bit is set.
 3. if the ID bit is set or all requesting interrupts are disabled via an IE bit, or the EN bit is clear, no further action is taken.
 4. the PC is copied to an interrupt return address (RET) register which is a memory mapped register (not shown).
 5. the ID bit is set in the status register so that further interrupts are disabled.
 6. address 2 is loaded into the program counter register, which is located in index register file 221. This is the address of the master interrupt handler.
 It is the task of the interrupt handler to clear the IF bit for each serviced interrupt, and clear the ID bit on exit to re-enable interrupts. Pending interrupts whose IF bit is was not cleared by the handler will re-interrupt when the ID bit is cleared. By re-enabling interrupts during the delay slot of the return branch, nesting of interrupts can be prevented.
 The six IF bits appear in the least significant bits of the status register. These can be used to index a branch table to vector to a requesting interrupt's handler. Because the IF flags for all enabled interrupts appear in the index, this table also encodes the priority for when multiple interrupts occur simultaneously.
 When manipulating a copy of the status register, for example when clearing the interrupt disable bit, there is the possibility of erasing the interrupt flags of requests that occur between the status read and reload. To avoid this the IF bits are given a special interpretation when loading. If an IF bit in the load source is set to one, the corresponding IF bit of the status register is cleared. If the bit is zero then the IF bit is unchanged. Therefore when saving and restoring the status register in an interrupt routine, it is necessary to set all IF bits in the copy to zero before reloading it, unless that interrupt is explicitly required to be reset.
 When loading the status register to clear the IF bit for some source, an interrupt request for that source could occur simultaneously. In this case, the bit is not cleared, so the interrupt is not lost. This does not trigger a real-time failure interrupt request.
 There is no stack data processing device 100. Interrupts are handled by a one-level memory mapped interrupt return address register RET, not shown. Interrupt nesting is handled by copying the return address to a private memory location. Subroutines are handled by explicitly passing the return address in the register file. These methods are straightforward when the interrupt handler or subroutine is non-re-entrant.
 Another novel aspect of data processing device 100 will now be discussed in detail, with reference to FIG. 10, that illustrates a prior art stream of data according to the MPEG-1 standard that contains a presentation time stamp 961 in a header 960 associated with each frame of data 950(n). BPU 110 decodes each frame of data and locates the presentation time stamp for that frame of data. The presentation time stamp is stored in a memory mapped status register in I2C block 150 for later use after it has been decoded from a frame of data. A detailed description of a process for decoding presentation time stamps is provided in U.S. Pat. No. ______, (TI-08/475,251, or TI-08/054,768), which has been included herein by reference; in particular, FIG. 30 and related description. BPU 110 also separates audio data 961 from each frame 950(n) and sends it to AU 120 for synthesis.
 As discussed earlier with reference to FIG. 2, Arithmetic Unit 120 performs subband synthesis filtering, which produces a stream of reconstructed PCM samples which are stored in output buffer area 124 of AU RAM 121. PCM Output Interface 140 receives PCM samples from output buffer 124 through a DMA transfer and then formats and outputs them to an external D/A converter. AU 120 processes each frame of audio data 961 and forms a resultant frame of PCM data PCM(n), as illustrated in FIG. 11A. Two channels of data are generated, a left channel and a right channel, for stereo sound.
 The presentation time stamp PTS(n) associated with each frame of data specifies when that frame of data should be played with reference to a reference time 970(n). An MPEG compatible data stream provides data for 192 samples in each data frame, while AC-3 provides 256 samples per frame. The data rate for PCM data samples is 48 k samples/second/channel, or approximately 20.8 us/sample. Thus, each presentation time stamp relates to a time period of 4 ms for MPEG and 5.33 ms for AC-3.
 Referring again to FIG. 5, the context of reference time 970 depends on the source of the data stream. For example, if the source is a CD player 512 and the stream is a song, then reference time 970 relates to the elapsed time since the song was started and presentation time stamps PTS(n) specify how long after the start time of a song a particular frame of PCM samples is to be played. Likewise, if the source is a video disk or a DSS program received on satellite dish 513, then the reference time relates to the beginning of the video program and serves to keep the audio track and the video track in synchronization.
 Referring back to FIG. 11A, there is illustrated a situation in which presentation time PTS(n+1) has fallen behind a reference time 970(n+1) by a time difference 971. BPU 110 compares the current presentation time stamp with the current reference time when the first sample of a frame of PCM data is to be transferred to the PCM output interface. If the time difference is significant, then BPU 110 proceeds with a correction procedure and only a partial frame of data PCM(n+1) is transmitted, according to an aspect of the present invention. If the time difference is greater than a frame time (5.33 ms for AC-3), then an entire frame is skipped. However, if time difference 971 is less than a frame time, then it is advantageous to perform a finer grain correction by skipping only a portion of a frame. For example, if time difference 971 is approximately 120 us, then six PCM samples are skipped and only 250 samples from frame PCM(n+1) are transferred to PCM interface 140.
FIG. 11B illustrates a second situation in which a presentation time PTS(n+1) is ahead of a reference time 980(n+1). If the time difference 981 is greater than a frame time (5.33 ms for AC-3), then an entire frame is repeated. However, if time difference 981 is less than a frame time, then it is advantageous to perform a finer grain correction by repeating only a portion of a frame. For example, if time difference 981 is approximately 100 us, then five PCM samples from frame PCM(n+1) are transferred first and then repeated when the entire frame PCM(n+1) is transferred.
 In both cases, AU 120 synthesizes an entire frame of PCM data and places it in output buffer portion 124. PCM samples are then transferred to PCM interface 140 by means of an interrupt driven direct memory access transfer. BPU 110 performs synchronization correction by causing only a portion of a PCM frame to be transferred to PCM interface 140.
FIG. 12 is an illustration of a frame of data PCM(n+1) in data buffer 124, showing various breakpoint addresses BP1, BP2 and BP3 corresponding to FIGS. 9A-9B. A breakpoint register, which was discussed earlier with reference to FIGS. 8 and 9, is loaded with a breakpoint address to control the transfer of frame PCM(n+1). If the entire frame is to be transferred, address BP 1 is used. If only 250 samples are to be transferred for the example of FIG. 11A, then address BP2 is used. Likewise, if only five samples are to be transferred for the example of FIG. 11B, then address BP3 is used.
FIG. 13 illustrates a means for comparing a presentation time to a reference time, according to an aspect of the present invention. Presentation time stamp register 990 is a memory mapped register, enabled to load a presentation time from data bus 161 b when a preselected address is decoded by address decoder 995. Timer 992 is reset to 0 by a memory mapped cycle when a selected address is decoded by decoder 995 and signal 996 is asserted. This is done when an audio or an audio/video selection first begins to be output. Timer 992 free-runs after being reset and thereby provides a reference time which is referenced to the beginning of a song or a video program, for example.
 ALU 994 subtracts the value stored in PTS register 990 from the current value of timer 992 and forms a resultant time difference. This is done at approximately the same time as when the first PCM sample of each PCM frame of data is transferred from output buffer 124 to PCM interface 140, as discussed above.
 Fabrication of data processing device 100 involves multiple steps of implanting various amounts of impurities into a semiconductor substrate and diffusing the impurities to selected depths within the substrate to form transistor devices. Masks are formed to control the placement of the impurities. Multiple layers of conductive material and insulative material are deposited and etched to interconnect the various devices. These steps are performed in a clean room environment.
 A significant portion of the cost of producing the data processing device involves testing. While in wafer form, individual devices are biased to an operational state and probe tested for basic operational functionality. The wafer is then separated into individual devices which may be sold as bare die or packaged. After packaging, finished parts are biased into an operational state and tested for operational functionality.
 An alternative embodiment of the novel aspects of the present invention may use other means for forming a reference time, such as decoding a presentation time stamp from a stream of video data; using a time-of-day timer; using a free-running counter and adjusting the time difference values according to a start count value, etc.
 An alternative embodiment of the novel aspects of the present invention may include other circuitries which are combined with the circuitries disclosed herein in order to reduce the total gate count of the combined functions. Since those skilled in the art are aware of techniques for gate minimization, the details of such an embodiment will not be described herein.
 An advantage of the present invention is that fine grained synchronization adjustments can be made in an audio channel so that the audio channel is correctly synchronized with a companion video channel. Fine grained corrections are less likely to be noticeable by a human listener. Skipping or repeating an entire frame results in a time shift of 4 ms (MPEG) or 5.3 ms (AC-3) which may cause a “pop” or other artifact after the PCM stream is converted to analog. Skipping or repeating an entire frame can also undesirably cause input buffer underflow or overflow.
 Another advantage of the present invention is that a single breakpoint address circuit can perform the function of fine grained synchronization, as well as other output buffer management functions.
 As used herein, the terms “applied,” “connected,” and “connection” mean electrically connected, including where additional elements may be in the electrical connection path.
 While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various other embodiments of the invention will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications of the embodiments as fall within the true scope and spirit of the invention.
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|U.S. Classification||704/502, 704/E19.039|