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Publication numberUS20020000583 A1
Publication typeApplication
Application numberUS 09/909,191
Publication dateJan 3, 2002
Filing dateJul 19, 2001
Priority dateNov 9, 1995
Also published asCN1152173A, CN1155004C, US5953242, US6069813, US6115279, US6288925, US6396088
Publication number09909191, 909191, US 2002/0000583 A1, US 2002/000583 A1, US 20020000583 A1, US 20020000583A1, US 2002000583 A1, US 2002000583A1, US-A1-20020000583, US-A1-2002000583, US2002/0000583A1, US2002/000583A1, US20020000583 A1, US20020000583A1, US2002000583 A1, US2002000583A1
InventorsGoro Kitsukawa, Takesada Akiba, Hiroshi Otori, William McKee, Jeffrey Koelling, Troy Herndon
Original AssigneeGoro Kitsukawa, Takesada Akiba, Hiroshi Otori, Mckee William R., Koelling Jeffrey E., Herndon Troy H.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
System with meshed power and signal buses on cell array
US 20020000583 A1
Abstract
A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.
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Claims(67)
What is claimed is:
1. A semiconductor memory device comprising:
a semiconductor substrate having a main surface;
a memory array portion in said main surface, in which a plurality of memory cells are arranged in row direction and in column direction;
bit lines each extending in said column direction and each of said bit lines connected to said memory cells;
word lines each extending in said row direction and each of said word lines connected to said memory cells;
a first peripheral circuit portion having a plurality of MOSFETs and said first peripheral circuit arranged adjacent to said memory array portion;
an external terminal formed on said main surface of said semiconductor substrate, and a predetermined voltage is supplied to said external terminal from outside of said semiconductor memory device;
a plurality of first voltage supply lines each extending in said column direction and formed over said bit lines and word lines;
a plurality of second voltage supply lines each extending in said row direction and formed over said bit lines and word lines, and said second voltage supply lines formed by a conductive layer which is different from that of said first voltage lines,
wherein said first and second voltage supply lines are connected each other at the intersection of said first and second voltage supply lines,
wherein one of said first and second voltage supply lines is connected to said external terminal, and
wherein said predetermined voltage is supplied to said MOSFETs in said first peripheral circuit portion from said external terminal via said first and second voltage supply lines.
2. A semiconductor memory device according to claim 1,
wherein said first voltage supply lines are comprised of a first conductive layer and said second voltage supply lines are comprised of a second conductive layer, and said first conductive layer is over said second conductive layer and said first conductive layer has a predetermined thickness which is thicker than that of said second conductive layer.
3. A semiconductor memory device according to claim 1, further comprising:
a second peripheral circuit portion having a plurality of MOSFETs, said second peripheral circuit portion being adjacent to said memory array region in said row direction and being adjacent to said first peripheral circuit portion in said column direction; and
a third voltage supply line formed in said first peripheral circuit portion and extending in parallel with said bit lines and into said second peripheral circuit portion,
wherein said second voltage supply lines extend into said second peripheral circuit portion and connected to said third voltage supply line at the intersections between said second voltage supply lines and third voltage supply line.
4. A semiconductor memory device according to claim 3, wherein said third voltage supply line is comprised of said first conductive layer and said third voltage supply line is connected to said MOSFETs in said first peripheral circuit portion.
5. A semiconductor memory device according to claim 4, wherein said first voltage supply lines each has a predetermined width which is larger than that of said third voltage supply line.
6. A semiconductor memory device according to claim 5, further comprising:
an insulating layer formed between said first conductive layer and said second conductive layer, said insulating layer has a first through hole through which said first and second voltage supply lines are connected and a second through hole through which said second and third voltage supply lines are connected; wherein said first through hole has a predetermined diameter which is larger than that of said second through hole.
7. A semiconductor memory device according to claim 6, wherein said memory cell is comprised of a MOSFET and a capacitor element connected in series, and said capacitor element is formed over said MOSFET.
8. A semiconductor memory device according to claim 4, further comprising:
a sense amplifier circuit portion being adjacent to said memory array portion in said column direction and being adjacent to said first peripheral circuit portion in said row direction, wherein said MOSFETs in said first peripheral circuit portion constitute sense amplifier driver circuit.
9. A semiconductor memory device according to claim 8, wherein a plurality of signal wirings extending in row direction in said sense amplifier circuit portion, said signal wirings are comprised of said second conductive layer.
10. A semiconductor memory device according to claim 4, wherein sub-decoder circuit is formed in said second peripheral circuit portion, and said sub-decoder circuit has two input terminals and an output terminal, a main word line and sub-decoder control line are connected to said input terminals and said word line is connected to said output terminal.
11. A semiconductor memory device according to claim 10, wherein said main word line and said sub-decoder control signal are comprised of said second conductive layer.
12. A semiconductor memory device according to claim 11, wherein said second voltage supply line has a predetermined width which is larger than that of said main word line.
13. A semiconductor memory device according to claim 11, further comprising:
a fourth voltage supply line formed in said memory array portion and comprised of said second conductive layer, and said subdecoder control line extending in said row direction arranged in the center of said memory array portion and said fourth voltage supply line extending in said row direction, and said second and fourth voltage supply lines are arranged at the both sides of said sub-decoder control line.
14. A semiconductor memory device according to claim 13, wherein said fourth voltage supply line is connected to said first voltage supply line at the intersection of said fourth and first voltage supply lines.
15. A semiconductor memory device according to claim 1, further comprising:
row select lines formed in said memory array portion and comprised of said first conductive layer;
row decoder circuit selecting a predetermined row select line into row select lines, wherein said first voltage supply line has a predetermined width which is larger than that of said row select line.
16. A semiconductor memory device according to claim 15, further comprising:
signal lines which is different from said row select line, extending in said column direction in said memory array portion, said signal lines comprised of said first conductive layer.
17. A semiconductor memory device according to claim 16, further comprising:
a fifth voltage supply line comprised of said first conductive layer and being extending in said column direction.
18. A semiconductor memory device according to claim 17, wherein said signal lines extend at the center of said memory array portion in said column direction, and said first and fifth voltage supply lines are arranged at the both sides of said signal lines.
19. A semiconductor memory device, comprising:
a semiconductor substrate;
a subarray portion including a plurality of memory cells each being arranged at the intersection of bit line extending in a column direction and word line extending in a row direction;
a fit peripheral circuit portion being adjacent to said sub-array in said row direction;
a second peripheral circuit portion being adjacent to said sub-array in said row direction;
a third peripheral circuit portion at the intersection of said first and second peripheral circuit portions;
a plurality of first voltage supply lines each extending in said column direction and formed over said bit lines and word lines;
a plurality of second voltage supply lines each extending in said row direction and formed over said bit lines and word lines, and said second voltage supply lines formed by a conductive layer which is different from that of said first voltage lines, and said second voltage lines formed over said sub-array portion and said second peripheral circuit portion;
a third voltage supply line comprised of said first conductive layer and extending over said second and third peripheral circuit portion,
wherein said first and second voltage supply lines are connected each other at the intersection of said first and second voltage supply lines over said sub-array portion,
wherein said second and third voltage supply lines are connected each other at the intersection of said second and third voltage supply lines over said second peripheral circuit portion, and
wherein said first and second voltage supply lines each has predetermined width which is larger than that of said third voltage supply line.
20. A semiconductor memory device according to claim 19, wherein a plurality of MOSFETs are arranged in said third peripheral circuit portion, and said MOSFETs are connected to said third voltage supply line.
21. A semiconductor memory device according to claim 20, further comprising:
a plurality of signal wiring lines extending in said row direction and comprised of said second conductive layer.
22. A semiconductor memory device according to claim 21, further comprising:
an insulating film formed between said first and second conductive layers, said insulating layer has a first through hole through which said first and second voltage supply lines are connected and a second through hole through which said second and third voltage supply lines are connected, wherein said first through hole has a predetermined diameter which is larger than that of said second through hole.
23. A semiconductor memory device according to claim 6, wherein said memory cell is comprised of a MOSFET and a capacitor element connected in series, and said capacitor element is formed over said MOSFET.
24. A semiconductor memory device according to claim 21, wherein said first conductive layer is over said second conductive layer and said first conductive layer has a predetermined thickness which is thicker than that of said second conductive layer.
25. A semiconductor memory device according to claim 19, wherein sub-decoder circuit is formed n said second peripheral circuit portion, and said sub-decoder circuit has two input terminals and an output terminal, a word line and sub-decoder control line are connected to said input terminals and said word line is connected to said output terminal.
26. A semiconductor memory device according to claim 25, wherein said main word line and said sub-decoder control signal are comprised of said second conductive layer, and said second voltage supply line has a predetermined width which is larger than that of said main word line.
27. A semiconductor memory device according to claim 26, wherein said sub-decoder control line extending in said row direction arranged in the center of said sub-array portion and said second voltage supply lines are arranged at the both sides of said of said sub-decoder control line.
28. A semiconductor memory device including a plurality of memory cells formed on a semiconductor substrate, complementary first and second bit lines to which said memory cells are connected, a first and second MOSFET connected in series between said first and second bit lines and third MOSFET connected between said first and second bit lines, comprising:
an active region formed on the main surface of said semiconductor substrate, in order to form said first, second and third MOSFETs;
a first, a second and a third semiconductor region formed in said active region;
an insulating film formed between said first, second and third semiconductor region and said first and second bit lines, said insulating film having a first through hole for connecting said first semiconductor region to said first bit line, a second through hole for connecting said second semiconductor region to said second bit line and a third through hole formed over said third semiconductor region; and
a gate electrode arranged between said first and second semiconductor regions, between second and third semiconductor regions and between said third and first semiconductor regions,
wherein said first, second and third through holes constitute a triangle, and the triangle corresponding complementary bit lines and the triangle corresponding adjacent complementary bit lines are mirror symmetrical relationship.
29. A semiconductor memory device according to claim 28, wherein said active region has T-shape configuration.
30. A semiconductor memory device according to claim 29, wherein said gate electrode has T-shape configuration.
31. A semiconductor memory device according to claim 30, wherein a predetermined fixed voltage is supplied to said third semiconductor region.
32. A semiconductor memory device, comprising:
a first MOSFET and a second MOSFET which constitute a sense amplifier circuit, said first and second MOSFETs each having a first semiconductor region and a second semiconductor region as source and drain;
a first memory array portion and a second memory array portion at both sides of said first and second MOSFETs;
complementary a first and a second bit lines extending in said first memory array portion, and complementary a third and a fourth bit lines extending in said second memory array portion,
wherein said first, second, third and fourth bit lines are comprised of a conductive layer,
wherein said first bit line is connected to said first semiconductor region, and is connected to said third bit line via said gate electrode of said second MOSFET,
wherein said second bit line is connected to said gate electrode of said first MOSFET and said first semiconductor region of said second MOSFET, and said second bit line is integral with said fourth bit line.
33. A semiconductor memory device comprising:
a memory array having a main word line, first and second subword lines corresponding to said main word line, a plurality of data lines and a plurality of memory cells;
a first subdecoder having an output terminal coupled to said first subword line and a first input terminal coupled to said main word line;
a second subdecoder having an output terminal coupled to said second subword line and a first input terminal coupled to said main word line;
a first driver, coupled to a second input terminal of said first subdecoder, outputting selection level voltage to be supplied to said first subword line; and
a second driver, coupled to a second input terminal of said second subdecoder, outputting selection level voltage to be supplied to said second subword line,
wherein said memory array is formed in a first area,
wherein said first and second subdecoders are formed in a second area which is adjacent to said first area, and
wherein said first and second drivers are formed in a third area which is adjacent to said second area.
34. A semiconductor memory device according to claim 33, further comprising:
a plurality of sense amplifiers coupled to said plurality of data lines,
wherein said plurality of sense amplifiers are formed in a fourth area which is adjacent to said first and third areas.
35. A semiconductor memory device according to claim 34,
wherein said first and second, third and fourth areas are quadrilateral areas, and
wherein said third area is an intersection area which is indicated by extending said second and fourth areas.
36. A semiconductor memory device according to claim 35, further comprising,
a first line for delivering a first selection signal to be supplied to an input terminal of said first driver; and
a second line for delivering a second selection signal to be supplied to an input terminal of said second driver,
wherein first and second lines, said main word line and said first and second subword lines are extended to the same direction in said first area.
37. A semiconductor memory device according to claim 36,
wherein each of said first and second subdecoders has (a) a first MOSFET having a gate coupled to said first input terminal and a source-drain path provided between said second input terminal and said output terminal, (b) a second MOSFET having a gate coupled to said first input terminal and a source-drain path provided between said output terminal and a ground potential and (c) a third MOSFET having a source-drain path coupled to said source-drain path of said second MOSFET in parallel.
38. A semiconductor memory device according to claim 37,
wherein said first and second drivers are invertor circuits.
39. A semiconductor memory device according to claim 37,
wherein said first MOSFET is an p-type, and
wherein said second and third MOSFETs are n-type.
40. A semiconductor memory device according to claim 39, wherein a gate width of said third MOSFET is narrower than that of said second MOSFET.
41. A semiconductor memory device according to claim 40,
wherein a voltage level of a selected subword line is higher than a high level voltage of said data lines.
42. A semiconductor memory device comprising:
a memory array having a main word line, a plurality of subword lines corresponding to said main word line, a plurality of data lines and a plurality of memory cells each of which is arranged to correspond to an intersection of one of said data lines and one of said subword lines;
a plurality of subdecoder circuits each of which includes (a) p-type first MOSFET having a drain coupled to corresponding one of said subword lines and a gate coupled to said main word line, (b) an n-type second MOSFET having a source receiving a ground potential, a drain coupled to said drain of said first MOSFET and a gate coupled to said main word line and (c) a third MOSFET having a source-drain path coupled between said drain and source of said second MOSFET;
a plurality of signal lines each of which is coupled to a gate of corresponding said third MOSFET, wherein one of said signal lines is set to a selection level; and
a plurality of drivers each of which has an input terminal coupled to corresponding one of said signal lines and an output terminal coupled to a source of corresponding said first MOSFET,
wherein said memo array is formed in a first quadrilateral region,
wherein said decoder circuits are formed in a second quadrilateral region which is adjacent to said first quadrilateral region, and
wherein said drivers are formed in a third quadrilateral region which is adjacent to said second quadrilateral region.
43. A semiconductor memory deice according to claim 42,
wherein said third MOSFET is an n-type,
wherein said selection level is low level, and
wherein said drive circuits are invertor circuits.
44. A semiconductor memory device according to claim 43,
wherein a voltage level of a selected subword line is higher than a high level voltage of said data lines.
45. A semiconductor memory device according to claim 44, further comprising:
a plurality of sense amplifiers coupled to said data lines,
wherein said sense amplifiers are formed in a fourth quadrilateral region which is adjacent to said first and third quadrilateral regions.
46. A semiconductor memory device according to claim 45,
wherein a gate width of said third MOSFET is narrower than that of said second MOSFET.
47. A semiconductor device comprising:
an array of electronic circuits;
an electrical port located outside said array;
a first conductor electrically connected to said electrical port and disposed over said array;
a second conductor disposed over said array, wherein said second conductor crosses said first conductor at a cross point in said array;
a peripheral circuit located outside of said array, wherein said peripheral circuit is electrically connected to said second conductor, and;
means for electrically connecting said first and second conductors at said cross point,
wherein said peripheral circuit is electrically connected to said electrical port via said first and second conductor.
48. The apparatus of claim 47 further comprising:
a third conductor disposed outside of said array, wherein said third conductor crosses said second conductor at a second cross point outside of said array and,
means for electrically connecting said second and third conductors at said second cross point,
wherein said peripheral circuit is electrically connected to said second conductor via said third conductor.
49. The apparatus of claim 47 wherein said second conductor is formed in a separate layer from said first conductor.
50. The apparatus of claim 48 wherein said second conductor is formed in a separate layer from said third conductor.
51. The apparatus of claim 47 wherein said array is a memory array and said electronic circuits are memory cells.
52. The apparatus of claim 47 wherein said peripheral circuit is a sense amplifier driver.
53. The apparatus of claim 47 wherein said means for electrically connecting comprises a through-hole.
54. The apparatus of claim 47 wherein said electrical port is a power pad, said first and second conductors are power buses.
55. The apparatus of claim 52 further comprising:
a first signal bus disposed over said array;
a second signal bus disposed over said array, wherein said second signal bus crosses said first signal bus at a second cross point in said array; and
means for electrically connecting said first and second signal buses at said second cross point.
56. The apparatus of claim 51 wherein each of said memory cells comprises:
a memory storage circuit;
a subword line; and
a main word line;
wherein said main word line is arranged in a hierarchical structure with said subword line.
57. The apparatus of claims 56 further comprising a subdecoder circuit comprising three transistors.
58. The apparatus of claim 57 wherein said subdecoder circuit is connected to said peripheral circuit.
59. A method for supplying power and signals on an array-type semiconductor device comprising:
supplying power to a power source located outside said array;
forming a first power bus connected to said power source and disposed over said array;
forming a second power bus over said array, such that said second power bus crosses said first power bus at a cross point in said array;
electrically connecting a peripheral circuit located outside of said array to said second power bus; and
electrically connecting said first and second power buses at said cross point.
60. The method of claim 59 further comprising:
forming a third power bus outside said array such that said third power bus crosses said second power bus at a second cross point outside said array,
electrically connecting said third power bus to said second power bus outside said array; and
electrically connecting said peripheral circuit to said second power bus via said third power bus.
61. The method of claim 59 wherein said first power bus is formed in a third metal layer and said second power bus is formed in a second metal layer.
62. The apparatus of claim 59 wherein said first power bus is formed in a separate layer from said second power bus.
63. The method of claim 59 wherein said array is a memory array.
64. The method of claim 63 wherein said peripheral circuit is a sense amplifier driver.
65. The method of claim 59 wherein said electrically connecting said first and second power buses is accomplished using a through-hole.
66. The method of claim 59 further comprising:
forming a first signal bus over said array;
forming a second signal bus over said array, such that said second power bus crosses said first signal bus at a second cross point in said array; and
electrically connecting said first and second signal buses at said second cross point.
67. The method of claim 66 wherein said electrically connecting said first and second signal buses is accomplished using a through-hole.
Description
    CROSS REFERENCE
  • [0001]
    This application claims the benefit of U.S. Provisional Application No. 60/005,502, filed Nov. 9, 1995.
  • FIELD OF THE INVENTION
  • [0002]
    The invention relates generally to semiconductor circuit design and, more particularly, to a method and apparatus for interconnecting power and signal buses in an integrated circuit.
  • BACKGROUND OF THE INVENTION
  • [0003]
    As semiconductor technology develops, the number of transistors included in a single integrated circuit, or “chip,” is becoming larger and the design rule parameters therefore are becoming smaller. These two developments contribute to increased metal layer resistance and to difficulties associated with this increased resistance. Such difficulties include ground bounce, cross talk noise, and circuit delays. All of these difficulties slow down chip operation and may even corrupt data stored on the chip. Eliminating the impact of increased metal layer resistance is an important design challenge in most semiconductor designs, including designs for dynamic random access memory (DRAM) devices.
  • [0004]
    One solution to this problem has been the development of a meshed power bus system for the chip, as described in Yamada, A 64-Mb DRAM with Meshed Power Line, 26 IEEE Journal of Solid-State Circuits 11 (1991). A meshed power bus system is readily implemented in integrated circuits like DRAMs because of their large arrays of memory cells and the presence of distributed sense amplifier drivers. The meshed system supplies adequate power to the distributed sense amplifier drivers because the system has many power buses running in both horizontal and vertical directions across the arrays.
  • [0005]
    The Yamada meshed system may be implemented using a conventional complimentary metal oxide semiconductor (CMOS) technology, including first, second and third metal layers, each electrically isolated from each other, wherein the first metal layer represents the lowest metal layer, the third metal layer represents the upper-most metal layer, and the second metal layer lies between the first and third layers. The Yamada meshed system is constructed in the second and third metal layer and includes a positive supply voltage (VDD) mesh and a negative supply voltage (VSS) mesh, for the VDD power buses and the VSS power buses, respectively. Conventional designs have these meshes running over the memory array and connecting at the sense amplifiers. Connections are made using through-holes, located in the area of the sense amplifier circuits. However, the presence of VDD and VSS power buses in the sense amplifiers is unnecessary, since these circuits do not require either VDD or VSS power buses, except for well bias.
  • [0006]
    As a result, the sense amplifiers, due to their relatively small size and numerous associated signal and power buses, are adversely affected by the Yamada meshed system. The Yamada meshed system overcrowds the sense amplifiers with additional power and signal buses. In addition, the metal line width required for overlapping through-holes is larger than the minimum metal line width and therefore increases the width of the metal layers even further. As a result, the metal layer over the sense amplifiers becomes determinative of the size of the sense amplifier circuits. Accordingly, their size reduction must be realized by tightening the metal width, inevitably resulting in increased resistance and slower operation
  • [0007]
    In addition to the Yamada meshed system, other proposals have been made for conventional DRAM design Recently, a hierarchical word line scheme was proposed in K. Noda et Al., a Boosted Dual Word-line Decoding Scheme for 256 Mbit DRAM's, 1992 Symp. on VLSI Circuits Dig. of Tech. Papers, pp. 112-113 (1992). The Noda scheme includes main word lines, constructed in the second metal line layer, and subword lines constructed in a poly silicon layer. The Noda scheme describes two main word lines (one true, one bar) for every eight subword lines, and is thereby able to relax the main word line pitch to four times that of the subword line. However, this pitch would not support an improved meshed power and signal bus system.
  • [0008]
    Consequently, there is a need for a meshed power and signal bus system on an array-type integrated circuit that does not limit mesh through-hole connections to the area of the sense amplifiers, but provides for such connections at other locations on the array, thereby allowing for a relaxed metal width over the sense amplifiers and a reduction of the overall area of the chip with lower power bus resistance.
  • [0009]
    Furthermore, there is a need for a hierarchical word line scheme that supports an improved meshed power and signal bus system, that has a main word line pitch greater than four times that of the subword line pitch.
  • SUMMARY OF THE INVENTION
  • [0010]
    The present invention, accordingly, is a method and apparatus for providing a meshed power bus and signal bus system on an array-type integrated circuit that does not limit mesh through-hole connections to the area of the sense amplifiers, but provides for these connections at other locations on the array, thereby allowing for a relaxed metal width over the sense amplifiers, faster sense amplifier operation, and chip size reduction. The through-holes for the mesh system are located in the cell array instead of, or in addition to, being located in the area of the sense amplifier circuits. This utilizes the available space for through-holes in the array, and allows for more efficient use of power and signal buses in the sense amplifiers.
  • [0011]
    The invention includes an array of DRAM memory cells, arranged as a plurality of subarrays and selected by main address decoders. Each subarray is surrounded by a plurality of sense amplifiers circuits, subdecoder circuits, and VDD, VSS and signal buses connecting to and running across the subarray. The VDD buses run in both vertical and horizontal directions across the subarray, with all the vertical buses lying in the third metal layer and all the horizontal buses lying in the second metal layer, thereby creating a VDD mesh. The buses in each layer are connected to each other using through-holes located in the memory cell subarray as well as on the sense amplifier area. Likewise, a VSS mesh and/or a signal mesh is created using through-holes located on the memory cell subarray. Once connected, the buses extend to the appropriate circuits, such as sense amplifier drive circuits, and the metal layer and through-hole requirement over the sense amplifiers is significantly reduced.
  • [0012]
    The invention also includes a hierarchical word line scheme. To facilitate the combination of the above-mentioned meshed system and the hierarchical word line scheme, the Noda hierarchical word line scheme should also be improved to provide a greater pitch of main word lines to subword lines. In the improved hierarchical word line system, an intersection area, created between the sense amplifier and the subdecoder, includes subdecoder drivers as well as sense amplifier drivers. This combination provides high speed word line selection and high speed sense amplifier operation at the same time.
  • [0013]
    Once the sense amplifier size is no longer determined by the metal usage, as provided by the above-mentioned meshed system, an improved layout technique for the sense amplifier circuits may be necessary to match the fine memory cell size. This improved layout technique includes an alternating T-shaped gate region for a bit line equalization circuit and an H-shaped moat region with a metal-to-polysilicon-to-metal change structure for a latch circuit.
  • [0014]
    A technical advantage achieved with the invention is the ability to fully utilize the low resistance design of a meshed power system without having to increase the size of the peripheral circuits, for example, sense amplifiers, that are limited in size by their metal layers.
  • [0015]
    A further technical advantage achieved with the invention is that both signal and power buses may freely run in both horizontal and vertical directions.
  • [0016]
    A further technical advantage achieved with the invention is that the design for through-holes located in the array area or on a step difference compensation area do not have to be made to the minimum design widths like the through-holes located in the peripheral area, and therefore the yield is improved.
  • [0017]
    A further technical advantage achieved with the invention is that the improved hierarchical word line structures are smaller and faster than conventional hierarchical word line structures.
  • BRIEF DESCRIPTION OF THE DRAWING
  • [0018]
    [0018]FIG. 1 is a block diagram of a 256 Mbit DRAM embodying features of the present invention.
  • [0019]
    [0019]FIG. 2 is a block diagram of two subarrays and surrounding sense amplifiers and sudecoders of the DRAM of FIG. 1.
  • [0020]
    [0020]FIG. 3 is a block diagram of one subarray, two sense amplifiers, and a subdecoder, as shown in FIG. 2, and a meshed power and signal system running across the subarray.
  • [0021]
    [0021]FIG. 4 is a schematic diagram of a meshed power and signal system over the subarray of FIG. 3.
  • [0022]
    [0022]FIG. 5a is a cross sectional view of a memory cell of the subarray of FIG. 3 with a through-hole connecting two metal layers used in the meshed power system of FIG. 4.
  • [0023]
    [0023]FIG. 5b is a detailed schematic of a memory cell of the subarray of FIG. 3.
  • [0024]
    [0024]FIGS. 6a-6 c are layout diagrams of expanded sections of the meshed system of FIG. 4.
  • [0025]
    [0025]FIGS. 7a-b are schematic diagrams of circuits included in the intersection area, sense amplifier, subdecoder and memory array of FIG. 3.
  • [0026]
    [0026]FIG. 8 is a diagram of the subdecoder circuits of FIG. 7.
  • [0027]
    [0027]FIG. 9a is a schematic diagram of a prior art subdecoder circuit showing the Noda hierarchical word line implementation.
  • [0028]
    [0028]FIG. 9b is a schematic diagram of one subdecoder circuit showing a hierarchical word line implementation.
  • [0029]
    [0029]FIG. 9c is a schematic diagram of a preferred subdecoder circuit show a hierarchical word line implementation of the present invention.
  • [0030]
    [0030]FIG. 10a is a schematic diagram of the two sense amplifier circuits of FIG. 7a.
  • [0031]
    [0031]FIG. 10b is a layout diagram of the sense amplifier circuits of FIG. 10a.
  • [0032]
    [0032]FIG. 11a is a layout diagram of a circuit used in an equalizer section of a conventional sense amplifier.
  • [0033]
    [0033]FIG. 11b is a layout diagram of a circuit ed in the equalizer section of the sense amplifier circuit of FIG. 7a, an alternate T-shaped gate region of the present invention.
  • [0034]
    [0034]FIG. 12a is a layout diagram of a circuit used in the latch section of the sense amplifier circuit of FIG. 7a, utilizing the H-shaped moat region of FIG. 10b.
  • [0035]
    [0035]FIG. 12b is a simplified diagram of the H-shaped moat region of FIG. 12a.
  • [0036]
    [0036]FIG. 13a is a metal layout diagram of a section of a conventional sense amplifier.
  • [0037]
    [0037]FIGS. 13b-c are metal layout diagrams of an improved section of the sense amplifier of FIG. 7a, implementing a noise decreasing method of the present invention.
  • [0038]
    [0038]FIG. 14a is a first cross sectional view of a sense amplifier using a triple well structure.
  • [0039]
    [0039]FIG. 14b is a second cross sectional view of the sense amplifier of FIG. 2, using a triple well structure.
  • [0040]
    [0040]FIG. 14c is a cross sectional view of the subdecoder of FIG. 2 using a triple well structure.
  • [0041]
    [0041]FIG. 15a is a block diagram showing four fuses used for the sense amplifiers of FIG. 2 and two additional sense amplifiers.
  • [0042]
    [0042]FIG. 15b is a schematic diagram showing four fuses used for the sense amplifiers of FIG. 2 and two additional sense amplifiers.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0043]
    In FIG. 1 the reference numeral 10 refers to a memory device embodying features of the present invention. The device 10 is fabricated using a conventional CMOS technology, including first, second and third metal layers and a polysilicon layer. The device 10 also utilizes metal oxide semiconductor field effect transistors (MOSFETs), but other types of transistors may also be used, such as bipolar, and metal insulator semiconductors. Furthermore, while in a preferred embodiment of the invention, the device 10 is a 256 Mbit dynamic random access memory (DRAM), it should be understood that the present invention is not limited to use with a 256 Mbit DRAM, but may be used in conjunction with other devices having arrays, including a programmable array logic, a 1 Gbit DRAM and other memory devices.
  • [0044]
    The device 10 includes a set of array blocks of memory cells, such as an array block 12, a group of pads 14 a-14 f, and a group of main address decoders 16 a-16 l, wherein decoders 16 b, 16 e, 16 h and 16 k are row decoders and decoders 16 a, 16 c, 16 d, 16 f, 16 g, 16 i, 16 j and 16 l are column decoders. The array block 12 is selected by signals from the address pads 14 a-14 d. It should be understood that while more address and signal pads exist, they may be represented by address pads 14 a-14 d, which are decoded by main address decoders 16 a-16. The main address decoders 16 a-16 l represent a plurality of row and column decoders. The row decoders generate signals including main-word signals MWB and subdecoder control signals DXB, and the column decoders generate signals such as column select signals YS. These signals are controlled by different address signals from the address pads 14 a-14 d, as discussed in greater detail below.
  • [0045]
    Array block 12, which is representative of the 16 Mbit array blocks, is further divided into 256 subarrays, two of which are shown in FIG. 2, and are respectively designated by reference numerals 18 a and 18 b. Each subarray consists of 128K of memory cells (arranged as 512 rows by 256 columns).
  • [0046]
    Power is supplied to the device 10 through power pads 14 e and 14 f. The pad 14 e is the positive supply voltage (VDD) power pad and is connected to an external power supply (not shown). The pad 14 f is the negative supply voltage (VSS) power pad and is connected to an external ground (also not shown).
  • [0047]
    Ref to FIG. 2, the memory cells of the subarray 18 a are selected by signals from two groups of address subdecoders 20 a and 20 b. Likewise, the memory cells of the subarray 18 b are selected by signals from two groups of address subdecoders 20 c and 20 d. The memory cells of subarray 18 a are read by two groups of sense amplifiers 22 a and 22 b. Likewise, the memory cells of subarray 18 b are read by two groups of sense amplifiers 22 b and 22 c. The sense amplifiers 22 a-22 c intersect with the subdecoders 20 a-20 d, at intersection areas 24 a-24 f. In this way, intersection areas 24 a-24 f are created by the extension of sense amplifier areas 22 a-22 c and subdecoder areas 20 a-20 d.
  • [0048]
    Referring to FIG. 3, the pads 14 e and 14 f act as electrical ports to supply power to the entire device 10 through main VDD and VSS power buses 28 and 26, respectively. The main VDD and VSS power buses 28 and 26 supply power to the device 10 through a plurality of buses, located in different metal layers. The metal layers are layered onto a silicon substrate, in the order of: a first metal layer (M1), a second metal layer (M2), and a third metal layer (M3). Each of the metal layers M1, M2, M3 is electrically isolated from each other, but may be electrically interconnected at intersection points using through-holes. Each metal layer M1, M2, M3 also has associated therewith a thickness such that the thickness for M3 is greater than the thickness for M2, which is greater than the thickness for M1.
  • [0049]
    A first VDD bus 30, comprising a conductor constructed in the third metal layer M3, extends in a vertical path across the subarray 18 a. A first VSS bus 32, also a conductor constructed in M3, extends in a vertical path across the memory subarray 18 a, parallel with the bus 30. Similarly, a first signal bus 34 and a first column select YS bus 35, conductors constructed in M3, run vertically across the subarray 18 a parallel with power buses 30 and 32. A first subdecoder DXB bus 36, also a conductor constructed in M3, runs vertically across address subdecoder 20 a, outside of the subarray 8 a.
  • [0050]
    A second VDD bus 37 a, a second VSS bus 37 b and a second signal bus 37 c, conductors constructed in M3, run vertically across the subdecoder 20 a and the intersection areas 24 a and 24 b. The second VDD bus 37 a and the second VSS bus 37 b have a width that is less than a width of the first VDD bus 30 and the first VSS bus 32, respectively.
  • [0051]
    A third VDD bus 38 and a third VSS bus 40, along with a third signal bus 42 and a second DXB bus 44, are also conductors similar to those described above, except that they are constructed in the second metal layer M2, and extend in parallel, horizontal paths across the memory subarray 18 a. The third VDD bus 38 electrically connects with the second VDD bus 37 a within the subdecoder 20 a at their intersection point 45 over the peripheral circuit area 20 a and the first VDD bus 30 at their intersection point 46 within the memory subarray 18 a. Likewise, the third VSS bus 40 electrically connects with the second VSS bus 37 b at their intersection point 47 within the subdecoder 20 a and the first VSS bus 32 at their intersection point 48 within the memory subarray 18 a. Furthermore, the third signal bus 42 electrically connects with the second signal bus 37 c at their intersection point 49 within the subdecoder 20 a and the first signal bus 34 at their intersection point 50 within the memory subarray 18 a. Finally, the second DXB bus 44 electrically connects with the first DXB bus 36 at their intersection point 52 in the subdecoder circuit 20 a. Each of the intersection points is achieved using through-holes, as discussed in greater detail with reference to FIGS. 5a-6 c.
  • [0052]
    Associated with each bus is a line width, it being understood that a bus with a larger surface area (width and thickness) provides a lower resistance current path. The first VDD and VSS bus 30, 32 have a line width of 1.8 microns. The second VDD and VSS bus 37 a, 37 b have a line width of 0.7 microns. The third VDD and VSS bus 38, 40 have a line width of 1.8 microns. Likewise, the through-holes have associated therewith a diameter, it being understood that a through-hole with a larger surface area (diameter) provides a lower resistance current path. The through-holes located above the memory subarray 18 a have a diameter of 0.6 microns, while the through-holes located above the subdecoder circuit 20 a have a diameter of 0.8 microns.
  • [0053]
    VDD and VSS power is supplied through the external pads 14 e and 14 f the main power buses 28 and 26, respectively, as previously described in FIG. 3. The first VDD bus 30 is electrically connected to the main VDD power bus 28 thereby supplying VDD power to the first VDD bus, the second VDD bus 37 a, and the third VDD bus 38. The first VSS bus 32 is electrically connected to the main VSS power bus 26 thereby supplying VSS power to the first VSS bus, the second VSS bus 37 b, and the third VSS bus 40. In this manner, a VDD mesh 54 is created by the VDD buses 30, 37 a and 38 and a VSS mesh 56 is created by the VSS buses 32, 37 b and 40. As a result, each of the foregoing meshes have power buses running both vertically and horizontally across the subarray 18 a, the subdecoder 20 a and the intersection areas 24 a-24 b. Furthermore, the VDD and VSS meshes 54 and 56 significantly reduce the total power bus resistance from the power pads 14 e and 14 f to the subdecoder 20 a, the intersection areas 24 a-24 b and other circuits, even when the widths of the VDD and VSS buses 37 a and 37 b are narrow.
  • [0054]
    A first peripheral circuit (not shown) drives electrical signals to the first signal bus 34 and the column decoder 16 a (FIG. 1) drives electrical signals to the YS bus 35, which is used in sen amplifiers 22 a and 22 b. Likewise, main address decoder 16 b (FIG. 1) drives electrical signals to the second DXB bus 44, in a conventional manner. The first signal bus 34 electrically connects with the second signal bus 37 c and the third signal bus 42 thereby creating a signal mesh 58 across the subarray 18 a and the subdecoder 20 a. Likewise, the first DXB bus 36 electrically connects with the second DXB bus 44 thereby creating a subdecoder mesh 60 across the subdecoder 20 a. In this manner, the signal and subdecoder meshes 58 and 60 are able to connect the sense amplifiers 22 a-22 b, the subdecoder 20 a, and the intersection areas 24 a-24 b in many different combinations. Although not shown, there are many additional buses constructed in M2 and extending horizontally across the sense amplifier circuit areas 22 a and 22 b. Some of these buses are connected to other signal buses, such as the YS bus 35.
  • [0055]
    Referring to FIG. 4, the VDD, VSS, signal and subdecoder meshes 54, 56, 58 and 60 actually represent many vertical and horizontal lines for each mesh, thereby providing more buses for the surrounding circuits, and decreasing the resistance of each mesh. For example, the subarray 18 a has multiple VDD buses 38 a-38 d running in M2 and multiple VDD buses 30 a-30 d running in M3, all tied to the main VDD bus 28 (FIG. 3), thereby decreasing the overall resistance of the VDD mesh 54. Likewise, the subarray 18 a has multiple VSS buses 40 a-40 d running in M2 and multiple VSS buses 32 a-32 d running in M3, all tied to the main VSS bus 26 (FIG. 3), thereby decreasing the overall resistance of the VSS mesh 56.
  • [0056]
    In addition to the VDD, VSS, signal and subdecoder meshes 54, 56, 58 and 60, other buses run across the subarray 18 a. These other buses include multiple column factor (CF) buses 61 a-61 d running vertically in M3, for inputs to the column decoders 16 a, 16 c, 16 d, 16 f, 16 g, 16 i, 16 j and 16 l (FIG. 2), and multiple subdecoder buses (DXB1, DXB3, DXB5, DXB7) 44 a-44d running horizontally in M2, for connection to the subdecoder circuits 20 a and 20 b (FIG. 2) and to the first DXB bus 36. Furthermore, as shown in FIG. 4, power buses 30 a-30 d, 32 a-32 d, 38 a-38 d, 40 a-40 d are located near an outer edge of the subarray 18 a than the signal buses 61 a-61 d, 44 a-44 d. As a result, resistance of the power buses is reduced, while the resistance for the signal buses, all grouped toward the interior edge of the subarray 18 a, are relatively consistent with each other, thereby making signal propagation through the signal buses relatively consistent.
  • [0057]
    Referring to FIG. 5a, the electrical connections between the buses shown in FIG. 4 are made at intersection points located above memory cells. An intersection point 48 a denotes where the VSS bus 32 b crosses the VSS bus 40 b. An electrical connection is made between the VSS bus 32 b and the VSS bus 40 b using a through-hole 62, located above a memory cell circuit 64.
  • [0058]
    Referring to FIGS. 5a-5 b, the memory cell circuit 64 of the subarray 18 a comprises a conventional, one capacitor and one transistor type DRAM cell. For example, a capacitor 65 is formed between a plate 67 and a storage node 68. Likewise, a transistor 69 is formed with the source and drain connected to the storage node 68 and a bit line (BL1) bus 70, respectively, and the gate connected to a first subword line (SW) bus 72 a, having a width 74. To avoid any coupling noise caused by the power and signal buses, the cell structure of the preferred embodiment is a capacitor on bit line (COB) structure. This structure facilitates the sensitive nature of the BL1 bus 70 and enables operation without any detrimental effect by noise from the power and signal meshes 54, 56 and 58 located over the cell, due to the shielding affect of the plate 64.
  • [0059]
    Although the intersection point 48 a appears to be located directly over the memory cell circuit 64, this is not required, and is only for the benefit of explanation. Furthermore, the through-hole 62 and VSS buses 32 b and 40 b are not necessary for memory cell 64 and not all of the power and signal buses will be connected to other buses.
  • [0060]
    Referring to FIGS. 4 and 6a, a first section 76 gives an expanded view of the subarray 18 a, showing more signal lines located between the buses shown in FIG. 4. Section 76 has several signal and power buses of various widths running both vertically and horizontally across it. These buses include YS buses 35 a-35 d, having a width 80, the CF bus 61 a, having a width 82, and the VSS bus 32 b, having a width 84, running vertically in M3. Likewise, buses 86 a-86 d, having a width 88, the DXB1 bus 44 a, having a width 90 and the VSS bus 40 b, having a width 92, run horizontally in M2. The signal buses YS 35 a-35 d, CF 61 a, MWB 86 and DXB1 44 a run directly to their corresponding circuits, and therefore do not require a through-hole on the subarray 18 a to change directions. Only the VSS buses 32 b and 40 b have a through-hole 62 to electrically connect them. With this arrangement, the width of each bus, 80, 82, 84, 88, 90 and 92, is optimized for speed and power resistance effect. For example the widths 84 and 92 of the VSS buses 32 b and 40 b, the width 82 of the CF bus 61 a, and the width 90 of the DXB1 bus 44 a are wider than the widths 80 and 88 for high speed and low power resistance, and to accommodate the through-hole 62. Meanwhile, the width 80 of the YS buses 35 and the width 88 of the MWB buses 86, are made narrower than the widths 82, 84, 90, 92 to conserve metal space.
  • [0061]
    Likewise, referring to FIGS. 6b and 6 c, sections 94 and 96 are shown, having two and no through-holes, respectively. As a result, two YS buses and one CF bus (or two YS buses and one power bus) are created with every four sense amplifier circuits, while still meeting acceptable M3 width and space requirements. Likewise, two MWB buses and one DXB bus (or two MWB buses and one power bus) are placed with every sixteen sub-word-line SW buses, while still meeting acceptable M2 width and space requirements. In addition, the widths of all the power and signal buses may be optimized to accommodate the multiple buses used by each mesh for reducing effective resistance and for achieving high speed, keeping the essential advantage of high yield by having the relaxed metal pitch of hierarchical word-line configuration.
  • [0062]
    Referring again to FIG. 3, in addition to the power and signal meshes 54, 56, and 58 being constructed over the subarray 18 a, they are partially constructed over the subdecoder 20 a, along with the subdecoder mesh 60. Other circuits are modified to accommodate the metal space needed by the power and signal meshes 54, 56, 58 and 60,. The modified circuits are included in the sense amplifiers, the subdecoders and the intersection areas, as described below.
  • [0063]
    [0063]FIGS. 7a and 7 b illustrate the subarray 18 a comprising 32 representative memory cells including the memory cell 64 of FIGS. 5a-b. Furthermore, the subarray 18 a is shown in relation to the intersection area 24 a, the subdecoder 20 a, and the sense amplifier 22 a of FIG. 2.
  • [0064]
    In the preferred embodiment, the sense amplifier 22 a includes 128 sense amplifier circuits, such as sense amplifier circuits 98 a and 98 b. Both of the sense amplifier circuits 98 a-98 b are connected to a sense amplifier driver 100 a, which is located in the intersection area 24 a. The sense amplifier cit 98 a is connected to a column of memory cells 102 a, through the BL1 bus 70 (FIG. 5a) and a bit line (BL1B) bus 104 a, which are both constructed in M1, and run vertically across the array 18 a. Likewise, the sense amplifier circuit 98 b is connected to a column of memory cells 102 b, through a bit line (BL2) bus 104 b and a bit line (BL2B) bus 104 c, which are also constructed in M1, and run vertically across the array 18 a. Sense amplifier circuits 98 a-98 b are discussed in greater detail with reference to FIGS. 10a-10 b, below.
  • [0065]
    In addition to the sense amplifier driver 100 a, the intersection area 24 a includes a plurality of circuits (excluding sense amplifier driver 100 a and subdecoder drivers 110 a-110 d) which are referenced generally by the numeral 100 b. These Fruits 100 a-100 b are designed to employ the advantages of the low resistance of the VDD, VSS and signal meshes 54, 56 and 58, as supplied by the buses 37 a-37 c.
  • [0066]
    The subdecoder 20 a includes 256 subdecoder circuits, represented generally be subdecoder flit 106 a-106 d. The subdecoder circuit 106 a illustrates a hierarchical word line structure utilized in each of the remaining subdecoder circuits. The subdecoder circuit 106 a is connected to the DXB7 bus 44 d and the MWB bus 86 a, which is routed to the four subdecoder circuits 106 a-106 d through a connector bus 108, constructed in M1. The subdecoder circuit 106 a is also connected to a first subdecoder driver 110 a, located in the intersection area 24 a, along with the sense amplifier driver 100. Likewise subdecoder circuits 106 b-106 d are connected to subdecoder drivers 110 b-110 d, located in the intersection areas. The subdecoder 20 a is discussed with more detail below.
  • [0067]
    Referring to FIG. 8, two subdecoder drivers 110 a-110 d are located in intersection area 24 a, while the other two subdecoder drivers 110 b-110 c are located in the intersection area 24 b. The subdecoder driver 110 a comprises an inverter, which converts the DXB7 bus 44 d, to an inverted subdecoder (DX7) bus 114 d. Likewise, the subdecoder drivers 110 b-d convert the DXB1 44 a, DXB3 44 b and DXB5 44 c to inverted subdecoder buses DX1 114 a, DX3 114 b and DX5 114 c. In the preferred embodiment, each of the subdecoder drivers 110 a-110 d drive 64 subdecoder circuits, thereby driving all 256 of the subdecoder 20 a. Being located in the intersection areas 24 a-24 b, the subdecoder drivers 110 a-110 d are made of significant size, and are supplied an internally generated boosted voltage (VPP) so that the buses DX1 114 a, DX3 114 b, DX5 114 c and DX7 114 d can be driven to VPP.
  • [0068]
    The subdecoder circuits 106 a et seq. employ a hierarchical word line structure. As discussed earlier, the subdecoder circuits formed in the subdecoder area 20 a and 20 b are used to select certain memory cells in the subarray 18 a. This is accomplished by utilizing a plurality of subword lines, such as the line 72 a, constructed in the polysilicon (FG) layer (FIG. 5a). The MWB bus 86 a drives four subdecoder circuits 106 a-106 d of subdecoder are 20 a, which each drive a SW bus 72 a-72 d, extending into the subarray 18 a. Likewise, the MWB bus 86 a drives four additional subdecoder circuits 106 e-106 h of subdecoder area 20 b, which each drive a SW bus 72 e-72 h, extending into the subarray 18 a.
  • [0069]
    Referring to FIGS. 9a-9 b, a conventional subdecoder circuit 116 and an alternative subdecoder circuit 118 implement a hierarchical word line structure. The structures are hierarchical due to the placement of main word line buses, constructed in M2, over a subword line buses, constructed in FG. However, the subdecoder circuits 116, 118 do not facilitate the meshed system of the present invention.
  • [0070]
    Referring to FIG. 9a, the conventional subdecoder circuit 116, as used in the Noda hierarchical word line structure scheme, consists of three n-type metal oxide semiconductor (NMOS) transistors and produces an SW output. However, the subdecoder circuit 116 requires a non-inverted word line (MW) bus, which must also run across the array (not shown) along with a MWB bus. This effectively doubles the number of main word lines running in M2 across the array. As a result, two main word lines are used to drive eight subword lines, thereby creating a pitch of 4 subword lines to every main word line. This pitch, however, does not allow the extra metal space needed for the meshed system of the present invention.
  • [0071]
    Referring to FIG. 9b, the subdecoder circuit 118 consists of two NMOS transistors and two p-type metal oxide semiconductor (PMOS) transistors. The subdecoder driver does not require a non-inverted word line bus (MW) as in FIG. 9a. As a result, one main word line is used to drive eight subword lines, thereby creating a pitch of 8 subword lines to every main word line. But, since the subdecoder circuit consists of four transistors, it thereby consumes a lot of space, and to speed the circuit up, some of the transistors must be made very large.
  • [0072]
    Referring to FIG. 9c, the subdecoder circuit 106 a of the preferred embodiment comprises the advantages of the above two subdecoder drivers. The subdecoder circuit 106 a uses the MWB bus 86 a, the DXB7 bus 44 d, and the DX7 bus 114 d to produce the subword line SW bus 72 a, thereby allowing the subdecoder cut 106 a to be constructed with only three transistors 120 a-120 c. Since the DX7 bus 114 d runs only in the subdecoder 20 a, and does not have to run horizontally across the array, the main word line pitch across the subarray 18 a remains at eight subword lines for every main word line. As a result, there is sufficient metal space for the power, signal and subdecoder meshes 54, 56, 58 and 60, and the DXB bus 44 (FIG. 3) of the present invention.
  • [0073]
    In operation, the signals on the MWB bus 86 a and DXB7 bus 44 d, designated as MWB and DXB7, are negative logic signals, i.e. they are high in the standby mode, low in an enable mode. When the signals MWB and DXB7 are both low, an output signal on the subword line SW bus 72 a is driven to a selective high level. When only one of the signals MWB or DXB7 is high, the output signal on the subword line SW bus 72 a is driven to a non-selective low level. In the standby or precharge mode, i.e., when all of the MWB and DXB signals are high, all subword lines SW are set to low.
  • [0074]
    An advantage of the subdecoder circuit 106 a is that a subthreshold current in the row decoders and DXB drivers is primarily determined by NMOS transistors 120 a, 120 b. As a result, a low standby current is achieved during standby or precharge mode. This is because a gate with for the NMOS transistors 120 a, 120 b can be narrower than that of PMOS transistors, and NMOS transistor cutoff-transition characteristics are sharper than that of PMOS transistors.
  • [0075]
    Other advantages of the subdecoder circuit 106 a are that the subdecoder circuit 106 a provides eta metal space for the power, signal and subdecoder meshes 54, 56, 58 and 60, and the subdecoder circuit 106 a improves in speed performance. The speed of the subdecoder circuit 106 a is directly proportional to the ability of the DX7 bus 114 d to a transition from low to high. Since the DX7 bus 114 a is driven by the subdecoder driver 110 a, and since the subdecoder driver is located in the non-crowded intersection area 24 a, it can be made of sufficient size. Furthermore, the DX7 bus 114 a is constructed in M3, which has the lowest resistance of the three metal layers. Thus, the DX7 bus 114 a produces a sharp rising wave form, thereby achieving high speed activation of the SW bus 72 a. In the preferred embodiment, a gate width (not shown) of the NMOS transistor 120 b of is narrower than that of a gate width (also not shown) of the NMOS transistor 120 a, thereby improving speed and layout area optimization. For example, in the preferred embodiment, the gate widths of transistors 120 a and 102 b are 2.2 microns and 1 micron, respectively. The narrow gate width of transistor 120 b contributes to smaller load capacitance and faster fall times for signals on the DXB bus 44 d. As a result, the DX bus 114 d achieves faster rise times. In addition, the gate width of 120 a is set to the sufficient value for falling speed of the subword line SW.
  • [0076]
    Referring to FIG. 10a, the sense amplifier circuit 98 a comprises a latch section 122 a and an equalizer section 124 a. The latch section 122 a comprises two NMOS transistors 126 a-126 b, connected between the bit line buses 70 and 104 a and a first latch bus 128. The latch section 122 a also comprises two PMOS transistors 130 a-130 b connected between the bit line buses 70 and 104 a and a second latch bus 132. All four transistors 126 a, 126 b, 130 a, 130 b are cross-coupled in a conventional latching manner for storing signs from the bitline buses 70 and 104 a.
  • [0077]
    The equalizer section 124 a includes three NMOS transistors 134 a-134 c for equaling the BL1 bus 70 and the BL1B bus 104 a during the standby or pre-charge modes. The three transistors 134 a-134 c are controlled by an equalization bus 136.
  • [0078]
    In a similar manner, the sense amplifier circuit 98 b comprises a latch section 122 b and an equalizer section 124 b connected to the bit line buses 104 b-104 c. The latch section 122 b and the equalizer section 124 b are also connected to the two latch buses 128, 132 and the equalization bus 136, respectively.
  • [0079]
    Referring to FIG. 10b, a further reduction in the size of the sense amplifier 22 a is achieved by other layout improvements. The equalizer sections 124 a and 124 b are constructed in shapes of alternating “T's” as discussed in greater detail below with reference to FIG. 11a. The latch sections 122 a and 122 b are constructed utilizing “H” shaped moat regions, as discussed in greater detail below with reference to FIG. 12a-b.
  • [0080]
    Referring to FIGS. 11a-11 b, to reduce the size constraints of the equalizer section 124 a caused by the transistors 134 a-134 c, a T-shaped gate region 138 a (FIG. 11a) is utilized. The equalizer signal bus 136 creates a gate for each of the transistors 134 a-134 c. in a similar manner, the equalizer section 124 b utilizes an inverted T-shaped gate region 138 b. As a result, the gate regions 138 a, 138 b can be compacted together, while still maintaining a required moat isolation distance 137 between the gate regions 138 a, 138 b. In so doing, a width 140 of the two gate regions is smaller than a conventional width 142 of two square gate regions 144 a and 144 b, as shown in FIG. 11b, and a small sense amplifier circuit 22 a corresponds to the small memory cell circuit 64 (FIG. 5a).
  • [0081]
    Referring to FIG. 12a, the sense amplifier 22 a also comprises an H-shaped moat 146. The BL1 bus 70, constructed in M1, must cross the BL1B bus 104 a, also constructed in M1, at the H-shaped moat 146 without electrically intersecting. Furthermore, the BL1 bus 70 must drive a transistor gate 148 a and the BL1B bus 104 a must drive a transistor gate 148 b. At a crossing point 150, the BL1B bus 104 a is connected to the transistor gate 148 b, constructed in ich runs under the metal layers. The gate 148 b not only serves to allow BL1B bus 104 a to cross the BL1 bus 70, but it is the gate for the transistor 130 b. After crossing the BL1 bus 70, the gate 148 b is reconnected to a connecting bus 152, also constructed in M1, thereby electrically connecting the BL1B bus 104 a to the connecting bus 152. Similarly, the BL2 bus 104 b and the BL2B 104 c bus also cross in the H-shaped moat 146.
  • [0082]
    Referring to FIG. 12b, these connections create an M1 to FG to M1 change and construct the two PMOS transistors 130 a-130 b. Not only does this change provide a size reduction, it without using an additional metal layer.
  • [0083]
    Furthermore, the H-shaped moat 146 solves another problem associated with the meshed system, that is, noise on the bit line buses 70 and 104 a-104 c. Noise at the sense amplifiers 22 a-22 c is often caused by signal buses constructed in M3 overlapping the bit line buses 70 and 104 a-c constructed in M1. Since the bit line buses 70 and 104 a do a crossing pattern, any noise or capacitive coupling induced from signal buses constructed in M3, such as the CF bus or the YS bus, will be the same for both the BL1 bus 70 and the BL1B bus 104 a, thereby effectively canceling the effect of noise. Likewise, any noise will be the same for the BL2 bus 104 b and the BL2B bus 104 c.
  • [0084]
    Referring to FIG. 13a, addition noise protection from signal buses constructed in M3 overlapping the bit line buses 70 and 104 a-c constructed in M1 can be reduced through M2 shielding. For example, in conventional prior art designs having first and second buses 154 a-154 b constructed in M1 and running in a vertical direction, and having a third bus 154 c constructed in M3 which also running in a vertical direction, noise is aggravated. Noise is induced from the third bus 154 c to the first and second buses 154 a and 154 b, since they overlap and run in the same direction, allowing the noise to be strengthened by the large area of overlap. This conventional design can be a problem, especially when the buses 154 a, 154 b are particularly sensitive to noise, such as the bit line buses 70 and 104 a of the present invention. Furthermore, in the conventional design, a group of other buses 156 a-156 d constructed in M2 and running in a horizontal direction have little to no shielding effect, as shown.
  • [0085]
    Referring to FIGS. 13b-13 c, the preferred embodiment reduces the noise between buses running in the same direction by improving the shielding effect of the M2 buses. In the preferred embodiment, the BL1 bus 70 and the BL1B bus 104 a are constructed in M1 and run in the vertical direction. Furthermore, the CF bus 61 a is constructed in M3 and runs in the vertical direction, just above the two bit line buses 70 and 104 a. Located between the CF bus 61 a and the bit line buses 70 and 104 a are four buses 158 a-158 d constructed in M2 and running in the horizontal directions.
  • [0086]
    Referring to FIG. 13b, one technique for reducing noise is used in a situation where the M2 buses 158 a and 158 d are noisy, active lines, such as parts of the sense amplifiers, and the M2 buses 158 b-c are inactive, quiet buses, such as a power supply bus, a first technique is used. Instead of having some of the M2 buses 158 a-158 d only extending across one of the bit line buses 70 and 104 a, as shown in FIG. 13a, the MS buses 158 b-158 c now extend over both bit line buses. In this manner, the M2 buses 158 a-158 d provide more of a shielding affect from any noise from the CF bus 61 a.
  • [0087]
    Referring to FIG. 13c, in a situation where two of the M2 buses 158 a and 158 d are inactive, quiet buses, such as a power supply bus, and the other two of the M2 buses 158 b, 158 c are active, noisy buses, a second technique is used. In this case, the bit line buses 70 and 104 a are better shielded from the noise of the CF bus 61 a by the quiet M2 buses 158 a, 158 d. Therefore, the quiet M2 buses 158 a, 158 d are drawn as large as possible, thereby maximizing their shielding affect.
  • [0088]
    Referring to FIG. 14a, the well structure of the sense amplifier can also be size determinative, especially in a situation like the preferred invention where power and signal meshes are utilized. In a first design, a triple well structure 160 comprising a p well (PW) 162 a, a deep well (DW) 164 a and a p-substrate (P-sub) 166 is used for noise protection from a sense amplifier circuit 170 to a subarray 168 a. Likewise, the triple well structure 160 comprises a p well (PW) 162 b, a deep n-type well (DW) 164 b and the P-Sub 166 for noise protection from a sense amplifier circuit 170 to a subarray 168 b. Although the wells 162 a, 162 b, 164 a, 164 b and substrate 166 may have various bias arrangements, one such arrangement provides:
    TABLE 1
    Well Bias Name Bias Voltage
    PW over DW VBBA 167a −1 V
    NW over DW VPP 167b 4.0 V
    DW VPP 167b 4.0 V
    P-Sub VBB 167c 0 V
    PW (not over DW) VBB 167c 0 V
    NW (not over DW) VDD 167d 3.3 V
  • [0089]
    It is noted that well biasing is well known in the art, and any descriptions of bias voltage are merely illustrative, and should not be limited to such in any manner.
  • [0090]
    The subarrays 168 a and 168 b are isolated from the noisy effects of the sense amplifiers 170 by two isolation n wells (NWs) 172 a and 172 b, respectively. The NWs 172 a, 172 b create separation transistors for sharing one sense amplifier between memory cell arrays located on either side. A negative bias voltage that is suitable for device isolation is supplied to the P-well 162 s and 162 b, where the above described separation transistors and the memory cell transistors are both located. The NWs 172 a, 172 b are biased to VPP 167 b for electrical isolation. Furthermore, the NW's 172 a, 172 b are located above the DWs 164 a, 164 b, respectively, and thereby bias the Dws to VPP. The sense amplifier circuit 170 has an additional NW 174, which is biased to VDD 167 d to provide faster operation of a p-type transistor 176. The advantage for DWs 164 a, 164 b being biased to VPP is that the subdecoders are CMOS circuits operating at the VPP voltage level (FIGS. 7a, 7 b, 14 c). On the other hand, because PMOS transistors of the sense amplifier circuit 170 operate at or below the VDD voltage level, the VDD voltage level is suitable as a bias voltage for the NW 174, instead of the VPP voltage level. The sense amplifier 170 also has two PWs 178 a, 178 b, biased to VBB 167 c through the P-sub 166. The PW 178 a supports a transistor 180 a and the PW 178 b supports transistors 180 b, 180 c.
  • [0091]
    Referring to FIG. 14b, the preferred embodiment is able to shrink the well structure of the sense amplifier 24 b, as compared to FIG. 14a. The preferred embodiment utilizes a triple well structure 182 comprising a PW 184 a, a DW 186 a, and a P-Sub 188, for subarray 18 a, and a PW 184 b, a DW 186 b, and the P-Sub 188, for subarray 18 b. The subarrays 18 a-18 b are thereby protected from the sense amplifier circuit 22 b. The triple well structure 182 also uses well-biasing similar to the illustrative biases described in Table 1. It is noted, however, that well biasing is well known in the art, and any descriptions of bias voltage are merely illustrative, and should not be limited to such in any manner.
  • [0092]
    The subarrays 18 a-18 b are isolated from the noisy effects of the sense amplifiers 24 b by two isolation NWs 190 a, 190 b, respectively. The isolation NWs 190 a, 190 b are biased to VPP 167 b for isolation. Furthermore, the isolation NWs 190 a, 190 b are located above the DWs 186 a-186 b, respectively, and thereby bias the DWs. The preferred embodiment differs from the conventional system of FIG. 14a in that the isolation NW 190 a also supports the transistor 130 d, which corresponds with the transistor 176 of FIG. 14a. As a result, the transistor 130 d will operate slower than the transistor 176 of FIG. 14a. However, the speed of the transistor 130 d is not critical to the overall timing of the sense amplifier circuit 90 a. Therefore, although the PMOS transistor 130 d is using a VPP biased well there is no overall speed degradation.
  • [0093]
    There is a size advantage, however, to the isolation NW 190 a over the conventional technique described in FIG. 14a. Instead of having the NW 172 a for the sole purpose of isolation, and the second NW 174 for the transistor 176 (FIG. 14a), the two are combined in the NW 190 a of the preferred embodiment, thereby shrinking the space of the sense amplifier 24 b. Furthermore, a single PW 192 can be used to support the transistors 134 a- 134 c.
  • [0094]
    Referring to FIG. 14c, a triple well structure 193 is implemented for the subdecoder 20 a. The P-Sub 188 and the DW 186 a extend throughout the subarray 18 a (FIG. 14b), across the subdecoder 20 a, and into a subarray 196. The PW 184 a is separated from a PW 198 by an NW 200, which is biased to VPP 167 b for isolation. By biasing the NW 200 at VPP 167 b, the SW bus 72 a can operate at VPP.
  • [0095]
    Referring to FIGS. 15a and 15 b, the sense amplifier 22 a includes four fuses 202 a-202 d used for a column redundancy scheme. The two fuses 202 b and 202 d are used to disable sense amplifier circuits 98 a-98 b, and the two fuses 202 a and 202 c are used to disable sense amplifier circuits 204 a-204 b. Column redundancy is well known to those skilled in the art; however, conventional designs result in a dramatic area penalty in the sense amplifier design due to the fuse placement. Accordingly, in the preferred embodiment, the fuses 202 a-202 d are lined in parallel with the bit line buses 70 and 104 a, even for the fuses corresponding to sense amplifiers located in a different area. In this way, the vertical running CF bus 61 a and the YS buses 35 c-35 d need to be offset for only one group of fuses, thereby providing the maximum space for the power and signal meshes 54, 56, 58 and 60.
  • [0096]
    Although the illustrative embodiment of the present invention has been shown and described, a latitude of modification, change and substitution is intended in the foregoing disclosure, and in certain instances, some features of the invention will be employed without a corresponding use of other features. For example, the horizontal and vertical directions were included to make the preferred embodiment simpler to describe, but are not intended to limit the present invention. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.
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Classifications
U.S. Classification257/257
International ClassificationG11C11/401, G11C11/34, H01L21/8242, G11C11/407, G11C11/409, H01L27/108, G11C7/18, G11C7/06, G11C5/02, G11C8/14, G11C5/14
Cooperative ClassificationG11C7/065, G11C5/025, G11C7/18, G11C5/14, G11C8/14
European ClassificationG11C5/02S, G11C8/14, G11C7/18, G11C5/14, G11C7/06L
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