Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20020000600 A1
Publication typeApplication
Application numberUS 09/338,542
Publication dateJan 3, 2002
Filing dateJun 23, 1999
Priority dateJun 24, 1998
Also published asEP0967651A2, EP0967651A3, US6448598
Publication number09338542, 338542, US 2002/0000600 A1, US 2002/000600 A1, US 20020000600 A1, US 20020000600A1, US 2002000600 A1, US 2002000600A1, US-A1-20020000600, US-A1-2002000600, US2002/0000600A1, US2002/000600A1, US20020000600 A1, US20020000600A1, US2002000600 A1, US2002000600A1
InventorsYoshihisa Nagano, Shinichiro Hayashi, Yasuhiro Uemoto
Original AssigneeYoshihisa Nagano, Shinichiro Hayashi, Yasuhiro Uemoto
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor memory
US 20020000600 A1
Abstract
A semiconductor memory includes plural lower electrodes formed on a semiconductor substrate; a capacitor dielectric film of an insulating metal oxide continuously formed over the plural lower electrodes; plural upper electrodes formed on the capacitor dielectric film in positions respectively corresponding to the plural lower electrodes; and plural transistors formed on the semiconductor substrate. The plural lower electrodes are respectively connected with source regions of the plural transistors.
Images(7)
Previous page
Next page
Claims(8)
What is claimed is:
1. A semiconductor memory comprising:
plural lower electrodes formed on a semiconductor substrate;
a capacitor dielectric film of an insulating metal oxide continuously formed over said plural lower electrodes;
plural upper electrodes formed on said capacitor dielectric film in positions respectively corresponding to said plural lower electrodes; and
plural transistors formed on said semiconductor substrate, wherein said plural lower electrodes are respectively connected with source regions of said plural transistors.
2. The semiconductor memory of claim 1, wherein an outer edge of said capacitor dielectric film is positioned in an outside portion away, by 1 μm or more, from an outer edge of an outermost lower electrode among said plural lower electrodes.
3. The semiconductor memory of claim 1, wherein each of said upper electrodes is made from a platinum film or a laminating film including a platinum film and an iridium oxide film.
4. The semiconductor memory of claim 1, wherein said capacitor dielectric film is made of a bismuth layer shaped perovskite ferroelectric, strontium barium titanate or tantalum pentaoxide.
5. A semiconductor memory comprising:
plural lower electrodes formed on a semiconductor substrate;
a capacitor dielectric film of an insulating metal oxide continuously formed over said plural lower electrodes;
an upper electrode formed over said capacitor dielectric film; and
plural transistors formed on said semiconductor substrate, wherein said plural lower electrodes are respectively connected with source regions of said plural transistors.
6. The semiconductor memory of claim 5, wherein an outer edge of said capacitor dielectric film is positioned in an outside portion away, by 1 μm or more, from an outer edge of an outermost lower electrode among said plural lower electrodes.
7. The semiconductor memory of claim 5, wherein said upper electrode is made from a platinum film or a laminating film including a platinum film and an iridium oxide film.
8. The semiconductor memory of claim 5, wherein said capacitor dielectric film is made of a bismuth layer shaped perovskite ferroelectric, strontium barium titanate or tantalum pentaoxide.
Description
BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor memory using an insulating metal oxide as a capacitor dielectric film.

[0002] A conventional semiconductor memory will now be described with reference to FIG. 6.

[0003] As shown in FIG. 6, a source region 32, a drain region 33 and a gate portion of a transfer gate having a function as a transistor of a memory cell are formed on a silicon substrate 31, and the gate portion includes a gate electrode 34 serving as a word line and an insulating film 34R covering the gate electrode 34. The drain region 33 is connected with a bit line 35.

[0004] Transistors each including the source region 32, the drain region 33, the gate electrode 34 and the like are disposed on the silicon substrate 31 in the form of an array so as to constitute a memory cell array, but the memory cell array is omitted in FIG. 6.

[0005] On the transistor, a first insulating layer 36 is formed, and the top surface of the first insulating layer 36 is flattened. In the first insulating layer 36, a contact hole 37 connected with the source region 32 is formed, and a conductive plug 38 is buried in the contact hole 37.

[0006] On the plug 38, a lower electrode 39 and a capacitive insulting film 40 of an insulating metal oxide processed by dry etching are formed, and on the side surfaces of the lower electrode 39 and the capacitor dielectric film 40, side walls 41 are formed. On the capacitor dielectric film 40, an upper electrode 42 is formed. The lower electrode 39, the capacitor dielectric film 40 and the upper electrode 42 together form a capacitor.

[0007] A second insulating layer 43 is formed so as to cover the capacitor. In the second insulating layer 43, a contact hole 44 reaching the upper electrode 42 is formed, and in the contact hole 44, a conductive metal wire 45 is formed.

[0008] In this conventional semiconductor memory, in forming the capacitor dielectric film 40 through the dry etching, strain derived from ion collision is caused in the crystal structure of the processed area of the capacitor dielectric film 40. As the capacitor has a finer structure, this strain more harmfully affects the electrical characteristic. As a result, the breakdown voltage of the capacitor is lowered.

SUMMARY OF THE INVENTION

[0009] An object of the invention is providing a semiconductor memory including a capacitor with a high breakdown voltage and fabricated without conducting dry etching on a capacitor dielectric film.

[0010] In order to achieve the object, the first semiconductor memory of this invention comprises plural lower electrodes formed on a semiconductor substrate; a capacitor dielectric film of an insulating metal oxide continuously formed over the plural lower electrodes; plural upper electrodes formed on the capacitor dielectric film in positions respectively corresponding to the plural lower electrodes; and plural transistors formed on the semiconductor substrate, wherein the plural lower electrodes are respectively connected with source regions of the plural transistors.

[0011] The second semiconductor memory of this invention comprises plural lower electrodes formed on a semiconductor substrate; a capacitor dielectric film of an insulating metal oxide continuously formed over the plural lower electrodes; an upper electrode formed over the capacitor dielectric film; and plural transistors formed on the semiconductor substrate, wherein the plural lower electrodes are respectively connected with source regions of the plural transistors.

[0012] In the first or second semiconductor memory, the capacitor dielectric film is formed continuously over the plural lower electrodes, and hence, there is no need to conduct dry etching for patterning the capacitor dielectric film. Accordingly, strain can be prevented from being caused in the crystal structure over the entire capacitor dielectric film, resulting in improving the breakdown voltage of the capacitor.

[0013] In the first or second semiconductor memory, an outer edge of the capacitor dielectric film is preferably positioned in an outside portion away, by 1 μm or more, from an outer edge of an outermost lower electrode among the plural lower electrodes.

[0014] In the first or second semiconductor memory, each of the upper electrodes is preferably made from a platinum film or a laminating film including a platinum film and an iridium oxide film.

[0015] In the first or second semiconductor memory, the capacitor dielectric film is preferably made of a bismuth layer shaped perovskite ferroelectric, strontium barium titanate or tantalum pentaoxide.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a sectional view of a main part of a semiconductor memory according to Embodiment 1 of the invention;

[0017]FIG. 2 is a characteristic diagram for showing the relationship between a breakdown voltage of a capacitor disposed in the outermost portion in the semiconductor memory of Embodiment 1 and a distance t between the edge of a lower electrode and the edge of a capacitor insulating film in this capacitor;

[0018]FIG. 3 is a sectional view of a main part of a semiconductor memory according to a modification of Embodiment 1;

[0019]FIG. 4 is a sectional view of a main part of a semiconductor memory according to Embodiment 2 of the invention;

[0020]FIG. 5 is a sectional view of a main part of a semiconductor memory according to a modification of Embodiment 2; and

[0021]FIG. 6 is a sectional view of a part of a conventional semiconductor memory.

DETAILED DESCRIPTION OF THE INVENTION

[0022] Embodiment 1

[0023] A semiconductor memory according to Embodiment 1 of the invention will now be described with reference to FIG. 1.

[0024] As shown in FIG. 1, a source region 2, a drain region 3 and a gate portion of a transfer gate having a function as a transistor of a memory cell are formed on a silicon substrate 1, and the gate portion includes a gate electrode 4 serving as a word line and an insulating film 4R covering the gate electrode 4. The drain region 3 is connected with a bit line 5.

[0025] Transistors each including the source region 2, the drain region 3, the gate electrode 4 and the like are disposed on the silicon substrate 1 in the form of an array so as to constitute a memory cell array, but the memory cell array is omitted in FIG. 1.

[0026] On the transistor, a first insulating layer 6 is formed, and the top surface of the first insulating layer 6 is flattened. In the first insulating layer 6, a contact hole 7 connected with the source region 2 is formed, and a conductive plug 8 is buried in the contact hole 7.

[0027] On the plugs 8 of the transistors, plural lower electrodes 9 are respectively formed, and on the plural lower electrodes 9, a capacitor dielectric film 10 of an insulating metal oxide is continuously formed. Upper electrodes 11 are formed on the capacitor dielectric film 10 in positions respectively corresponding to the lower electrodes 9. The lower electrode 9, the capacitor dielectric film 10 and the upper electrode 11 together form a capacitor.

[0028] A second insulating layer 12 is formed so as to cover the capacitor. In the second insulating layer 12, a contact hole 13 reaching the upper electrode 11 is formed, and a conductive metal wire 14 is formed in the contact hole 13.

[0029] In the semiconductor memory of this embodiment, since the capacitor dielectric film 10 is continuously formed over the plural lower electrodes 9, there is no need to conduct dry etching in order to pattern the capacitor dielectric film 10 into the shape corresponding to each lower electrode 9. Accordingly, strain derived from ion collision can be prevented from being caused in the crystal structure over the entire capacitor dielectric film 10, resulting in improving the breakdown voltage of the capacitor.

[0030] In Embodiment 1, when the upper electrode 11 is made from a platinum film or a laminating film including a platinum film and an iridium oxide film, the resultant capacitor can attain a better characteristic.

[0031] While the breakdown voltage of the capacitor is 15 V in the conventional semiconductor memory, capacitors excluding those disposed in the outermost portion in the semiconductor memory of Embodiment 1 attain an improved breakdown voltage of 35 V.

[0032]FIG. 2 shows the relationship between the breakdown voltage of a capacitor disposed in the outermost portion and a distance t (see FIG. 1) between the edge of the lower electrode 9 and the edge of the capacitor dielectric film 10 in this capacitor. As is understood from FIG. 2, when the distance t is 1 μm or more, the capacitor disposed in the outermost portion can attain a breakdown voltage of 35 V similarly to the other capacitors.

[0033] In fabricating a nonvolatile semiconductor memory, the insulating metal oxide included in the capacitor dielectric film 10 is preferably a bismuth layer shaped perovskite ferroelectric. The bismuth layer shaped perovskite ferroelectric is excellent in charge retention performance and polarization inversion characteristic.

[0034] Alternatively, in fabricating a volatile semiconductor memory, the insulating metal oxide included in the capacitor dielectric film 10 is preferably strontium barium titanate or tantalum pentaoxide. Strontium barium titanate and tantalum pentaoxide have a dielectric constant of 400 and 25, respectively, which are much larger than that of an insulating film of silicon nitride or silicon oxide. Accordingly, a dynamic RAM in the Gbit class can be easily realized by using these materials.

[0035] Modification of Embodiment 1

[0036] A semiconductor memory according to a modification of Embodiment 1 will now be described with reference to FIG. 3. In the modification of FIG. 3, like reference numerals are used to refer to like elements shown in FIG. 1, and the description is omitted.

[0037] As a characteristic of the semiconductor memory according to the modification of Embodiment 1, as is shown in FIG. 3, an upper electrode 11 is formed over an entire capacitor dielectric film 10, and one contact hole 13 and one metal wire 14 are formed.

[0038] Embodiment 2

[0039] A semiconductor memory according to Embodiment 2 of the invention will now be described with reference to FIG. 4.

[0040] In Embodiment 2 of FIG. 4, like reference numerals are used to refer to like elements used in Embodiment 1 of FIG. 1, and the description is omitted.

[0041] As a characteristic of the semiconductor memory of Embodiment 2, an insulating film 15 having the same thickness as a lower electrode 9 is formed between the adjacent lower electrodes 9.

[0042] In the semiconductor memory of Embodiment 2, since the upper surface of the lower electrode 9 and the upper surface of the insulating film 15 are disposed on the same plane, a flat capacitor dielectric film 10 can be formed by a simple film forming method such as a spin-on method without using a complicated method such as CVD. Thus, the electric characteristic of the capacitor can be improved.

[0043] Modification of Embodiment 2

[0044] A semiconductor memory according to a modification of Embodiment 2 will now be described with reference to FIG. 5. In the modification of FIG. 5, like reference numerals are used to refer to like elements used in Embodiment 1 of FIG. 1, and the description is omitted.

[0045] As a characteristic of the semiconductor memory according to the modification of Embodiment 2, as is shown in FIG. 5, an upper electrode 11 is formed over an entire capacitor dielectric film 10, and one contact hole 13 and one metal wire 14 are formed.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7768050Jul 9, 2007Aug 3, 2010The Trustees Of The University Of PennsylvaniaFerroelectric thin films
Classifications
U.S. Classification257/310, 257/E21.009, 257/295, 257/E21.648
International ClassificationH01L27/04, H01L21/8242, H01L21/8246, H01L27/108, H01L21/822, H01L21/02, H01L27/105, H01L27/10
Cooperative ClassificationH01L27/10852, H01L28/55
European ClassificationH01L27/108M4B2, H01L28/55
Legal Events
DateCodeEventDescription
Jun 23, 1999ASAssignment
Owner name: MATSUSHITA ELECTRONICS CORPORATION, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NAGANO, YOSHIHISA;HAYASHI, SHINICHIRO;UEMOTO, YASUHIRO;REEL/FRAME:010063/0058
Effective date: 19990617
Jun 7, 2001ASAssignment
Jun 8, 2004CCCertificate of correction
Feb 13, 2006FPAYFee payment
Year of fee payment: 4
Jan 29, 2010FPAYFee payment
Year of fee payment: 8
Feb 21, 2014FPAYFee payment
Year of fee payment: 12