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Publication numberUS20020000651 A1
Publication typeApplication
Application numberUS 09/897,248
Publication dateJan 3, 2002
Filing dateJul 2, 2001
Priority dateMar 9, 1999
Also published asDE10011368A1, US6486553
Publication number09897248, 897248, US 2002/0000651 A1, US 2002/000651 A1, US 20020000651 A1, US 20020000651A1, US 2002000651 A1, US 2002000651A1, US-A1-20020000651, US-A1-2002000651, US2002/0000651A1, US2002/000651A1, US20020000651 A1, US20020000651A1, US2002000651 A1, US2002000651A1
InventorsTomoko Takizawa, Masanori Takeuchi
Original AssigneeTomoko Takizawa, Masanori Takeuchi
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device and method of fabricating the same
US 20020000651 A1
Abstract
There is provided a semiconductor device including (a) a semiconductor chip, (b) a wiring making electrical connection with the semiconductor chip and containing copper (Cu) therein, (c) a solder ball making contact with the wiring and containing tin (Sn) therein, and (d) a layer made of copper-tin (CuSn) alloy, sandwiched between the wiring and the solder ball, and having a thickness equal to or greater than about 1.87 micrometers. The copper-tin alloy layer strengthens connection between the wiring and the solder ball, and hence, ensures reduction in occurrence of breakage and/or cracking in the wiring and the solder ball. As a result, it would be possible to avoid the solder ball from being separated from the wiring due to the breakage and cracking. Accordingly, a fabrication yield of the semiconductor device can be enhanced.
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Claims(26)
What is claimed is:
1. A semiconductor device comprising:
(a) a semiconductor chip;
(b) a wiring making electrical connection with said semiconductor chip and containing copper (Cu) therein;
(c) a solder ball making contact with said wiring and containing tin (Sn) therein; and
(d) a layer made of copper-tin (CuSn) alloy, sandwiched between said wiring and said solder ball, and having a thickness equal to or greater than about 1.87 micrometers.
2. The semiconductor device as set forth in claim 1, wherein said copper-tin (CuSn) alloy layer has a thickness equal to or greater than 2 micrometers.
3. The semiconductor device as set forth in claim 2, wherein said copper-tin (CuSn) alloy layer has a thickness equal to or greater than 3 micrometers.
4. The semiconductor device as set forth in claim 1, wherein said solder ball contains agglomerates scattering therein, said agglomerates being composed of material other than tin.
5. The semiconductor device as set forth in claim 4, wherein said agglomerates are composed of lead (Pb), and wherein said lead agglomerates are scattered at a density of 20104 mm−3 or greater.
6. The semiconductor device as set forth in claim 4, wherein said agglomerates are composed of lead (Pb), and wherein said lead agglomerates have a cross-sectional area of 10 square micrometer or smaller in average.
7. The semiconductor device as set forth in claim 1, further comprising a printed wiring board making electrical connection with said solder ball.
8. A semiconductor device comprising:
(a) a semiconductor chip;
(b) a wiring making electrical connection with said semiconductor chip, having first and second surfaces, and containing copper (Cu) therein;
(c) a solder ball making contact with said wiring at said first surface and containing tin (Sn) therein;
(d) a film substrate making contact with said wiring at said second surface, said film substrate being formed with a through-hole reaching said wiring;
(e) an electrical conductor filling said through-hole therewith;
(f) a first layer covering said electrical conductor therewith at the opposite side of said wiring, and made of gold; and
(g) a second layer made of copper-tin alloy, sandwiched between said wiring and said solder ball, and having a thickness equal to or greater than about 1.87 micrometers.
9. The semiconductor device as set forth in claim 8, wherein said second layer has a thickness equal to or greater than 2 micrometers.
10. The semiconductor device as set forth in claim 9, wherein said second layer has a thickness equal to or greater than 3 micrometers.
11. The semiconductor device as set forth in claim 8, wherein said solder ball contains agglomerates scattering therein, said agglomerates being composed of material other than tin.
12. The semiconductor device as set forth in claim 11, wherein said agglomerates are composed of lead (Pb), and wherein said lead agglomerates are scattered at a density of 20104 mm−3 or greater.
13. The semiconductor device as set forth in claim 11, wherein said agglomerates are composed of lead (Pb), and wherein said lead agglomerates have a cross-sectional area of 10 square micrometer or smaller in average.
14. The semiconductor device as set forth in claim 8, further comprising a printed wiring board making electrical connection with said solder ball.
15. A method of fabricating a semiconductor device, comprising the steps of:
(a) forming a wiring containing copper (Cu), on a substrate;
(b) mounting a solder ball containing tin (Sn), on said wiring; and
(c) keeping a product resulted from said step (b), in inactive gas atmosphere or in reducing gas atmosphere at a temperature equal to or greater than a melting point of said solder ball.
16. The method as set forth in claim 15, wherein said product resulted from said step (b) is kept in said inactive gas atmosphere or in said reducing gas atmosphere for an hour or longer.
17. The method as set forth in claim 15, further comprising the step of forming a gold layer on said wiring in advance of mounting said solder ball on said wiring.
18. A method of fabricating a semiconductor device, comprising the steps of:
(a) forming a wiring containing copper (Cu), on a substrate;
(b) covering said wiring with a resist having a recess through which said wiring appears;
(c) forming a through-hole through said substrate so that said through-hole reaches said wiring;
(d) filling electrical conductor in said through-hole;
(e) covering said electrical conductor with a gold layer;
(f) connecting said substrate to a semiconductor chip.
(g) mounting a solder ball containing tin (Sn), in said recess; and
(h) keeping a product resulted from said step (g), in inactive gas atmosphere or in reducing gas atmosphere at a temperature equal to or greater than a melting point of said solder ball.
19. The method as set forth in claim 18, wherein said product resulted from said step (g) is kept in said inactive gas atmosphere or in said reducing gas atmosphere for an hour or longer.
20. The method as set forth in claim 18, further comprising the step of forming a gold layer on said wiring in advance of mounting said solder ball on said wiring.
21. A semiconductor device comprising:
(a) a semiconductor chip;
(b) a wiring making electrical connection with said semiconductor chip and containing copper (Cu) therein;
(c) a solder ball making contact with said wiring and containing tin (Sn) therein; and
(d) a layer made of copper-tin (CuSn) alloy, sandwiched between said wiring and said solder ball, and having a thickness equal to or greater than about 1.87 micrometers,
said semiconductor device being resulted from the steps of:
(a) forming said wiring on a substrate;
(b) mounting said solder ball on said wiring; and
(c) keeping a product resulted from said step (b), in inactive gas atmosphere or in reducing gas atmosphere at a temperature equal to or greater than a melting point of said solder ball.
22. The semiconductor device as set forth in claim 21, wherein said product resulted from said step (b) is kept in said inactive gas atmosphere or in said reducing gas atmosphere for an hour or longer.
23. The semiconductor device as set forth in claim 21, wherein said copper-tin (CuSn) alloy layer has a thickness equal to or greater than 2 micrometers.
24. The semiconductor device as set forth in claim 21, wherein said copper-tin (CuSn) alloy layer has a thickness equal to or greater than 3 micrometers.
25. A semiconductor device comprising:
(a) a semiconductor chip;
(b) a wiring making electrical connection with said semiconductor chip and containing copper (Cu) therein; and
(c) a solder ball making contact with said wiring and containing tin (Sn) therein, said solder ball containing lead (Pb) agglomerates scattering therein at a density of 20104 mm−3 or greater,
said semiconductor device being resulted from the steps of:
(a) forming said wiring on a substrate;
(b) mounting said solder ball on said wiring; and
(c) keeping a product resulted from said step (b), in inactive gas atmosphere or in reducing gas atmosphere at a temperature equal to or greater than a melting point of said solder ball.
26. A semiconductor device comprising:
(a) a semiconductor chip;
(b) a wiring making electrical connection with said semiconductor chip and containing copper (Cu) therein; and
(c) a solder ball making contact with said wiring and containing tin (Sn) therein, said solder ball containing lead (Pb) agglomerates scattering therein, said lead agglomerates having a cross-sectional area of 10 square micrometer or smaller in average,
said semiconductor device being resulted from the steps of:
(a) forming said wiring on a substrate;
(b) mounting said solder ball on said wiring; and
(c) keeping a product resulted from said step (b), in inactive gas atmosphere or in reducing gas atmosphere at a temperature equal to or greater than a melting point of said solder ball.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to enhancement of a fabrication yield of a semiconductor device.

[0003] 2. Description of the Related Art

[0004] In response to requirement for an electronic device to accomplish higher performance, to be smaller in size and lighter in weight, and to be able to operate at a higher rate, many new semiconductor devices have been developed. For instance, an electronic device is formed smaller in size and lighter in weight by more highly integrating a semiconductor chip to thereby fabricate a semiconductor device in smaller size and weight.

[0005]FIGS. 1A to 1C illustrate a conventional semiconductor device. FIG. 1A is a cross-sectional view of a conventional semiconductor device, FIG. 1B is an enlarged view of a connection between a wiring layer and a solder ball, and FIG. 1C is a cross-sectional view illustrating that the semiconductor device illustrated in FIG. 1A is electrically connected to a printed wiring board.

[0006] With reference to FIG. 1A, the conventional semiconductor device is comprised of a semiconductor chip 1, a film substrate 3, a polyimide adhesive layer 31 adhering the film substrate 3 to the semiconductor chip 1, a resist 32 covering the wiring layer 2 therewith and formed with a land 7 which is a recess formed at a surface thereof, a wiring layer 2 formed on the film substrate 3, a solder ball 101 mounted on the wiring layer 2 in the land 7, a gold (Au) layer 8 covering the wiring layer 2 therewith within the land 7, a metal 5 filled in a through-hole 4 formed through both the film substrate 3 and the polyimide adhesive layer 31, and a gold (Au) layer 6 covering therewith the metal 5 at a top surface thereof.

[0007] The wiring layer 2 is in electrical connection with the semiconductor chip 1, and contains copper (Cu) therein. The solder ball 101 contains tin (Sn) therein. Though FIG. 1A explicitly illustrates the gold layer 8 formed on the wiring layer 2, it is considered that the gold layer 8 is diffused into the solder ball 101 in a heating step such as a temperature cycle test to be carried out after completion of the semiconductor device, and hence, it is further considered that the gold layer 8 will not exist on the wiring layer 2 after such a heating step is carried out.

[0008] As illustrated in FIG. 1C, the semiconductor device illustrated in FIG. 1A is electrically connected to a printed wiring board 34 through the solder ball 101.

[0009]FIG. 2A is an enlarged view of the wiring layer 2 and the solder ball 101, wherein the solder ball 101 is composed of SnPb eutectic solder containing tin 82 at 63% and lead 83 at 37%. FIG. 2B is a partially enlarged view of a boundary between the wiring layer 2 and the solder ball 101. As illustrated in FIG. 2B, a CuSn alloy layer 81 having a thickness of 1.75 micrometer to 2.0 micrometer is sandwiched between the wiring layer 2 and the solder ball 101.

[0010] A method of fabricating the conventional semiconductor device illustrated in FIGS. 1A to 1C is explained hereinbelow with reference to FIGS. 3A to 3H and 4A to 4H. FIGS. 3A to 3H are partial cross-sectional views of the semiconductor device illustrated in FIG. 1A.

[0011] First, as illustrated in FIG. 3A, the wiring layer 2 containing copper therein is formed on an upper surface of the film substrate 3, and the adhesive layer 31 is formed on a lower surface of the film substrate 3. The film substrate 3 has a thickness of 12 micrometers, the wiring layer 2 has a thickness of 18 micrometers, and the adhesive layer 31 has a thickness of 10 micrometers. The film substrate 3 is composed of a material having a resistant to a temperature of 250 degrees centigrade or greater, such as polyimide. The adhesive layer 31 is composed of polyimide.

[0012] Then, as illustrated in FIG. 3B, the wiring layer 2 is patterned into a predetermined pattern.

[0013] Then, as illustrated in FIG. 3C, the patterned wiring layer 2 and the film substrate 3 are both covered with the resist 32.

[0014] Then, as illustrated in FIG. 3D, there is formed the through-hole 4 through the adhesive layer 31 and the wiring layer 2, for instance, by means of a laser beam gun.

[0015] Then, as illustrated in FIG. 3E, the through-hole 4 is filled with the metal 5 such as copper or aluminum.

[0016] Then, as illustrated in FIG. 3F, the metal 5 is covered at a top surface thereof with the gold layer 6.

[0017] Then, as illustrated in FIG. 3G, the resist 32 is formed with the land 7 above the wiring layer 2. In later steps, the solder ball 101 is mounted on the wiring layer 2 in the land 7.

[0018] Then, as illustrated in FIG. 3H, the land 7 is covered with the thin gold layer 8.

[0019] Thus, there is completed a tape substrate 93 comprised of the film substrate 3 having the wiring layer 2 formed on the upper surface. Though FIGS. 3A to 3H illustrate only one land 7, it should be noted that the film substrate 3 is in the form of a sheet, and the film substrate 3 is formed with a plurality of lands 7 in each of which the solder ball 101 is to be mounted in later steps.

[0020] A method of mounting solder balls on the wiring layer 2 is explained hereinbelow with reference to FIGS. 4A to 4H.

[0021] First, as illustrated in FIG. 4A, the tape substrate 93 resulted from the steps illustrated in FIGS. 3A to 3H is placed with the gold layer 6 being upwardly directed. For simplification, the gold layer 6 is not illustrated in FIG. 4A.

[0022] Then, as illustrated in FIG. 4B, stiffeners 41 are adhered on the tape substrate 93 at opposite its opposite ends. The stiffeners 41 are composed of copper or stainless, for instance. The stiffeners 41 are used for fixing the tape substrate 93 when the semiconductor chip 1 is mounted onto the tape substrate 93.

[0023] Then, as illustrated in FIG. 4C, the semiconductor chip 1 is mounted on the tape substrate 93, surrounded by the stiffeners 41. Then, the gold layer 6 is electrically connected to an electrode 12 of the semiconductor chip 1 through a bonding wire (not illustrated). The connection is accomplished by means of a bonding tool, a heater and a ultrasonic wave generator (not illustrated).

[0024] Then, as illustrated in FIG. 4D, resin 42 is applied between the tape substrate 93 and the semiconductor chip 1, and then, is cured to thereby reinforce a connection between the tape substrate 93 and the semiconductor chip 1. The resin 42 is composed of epoxy resin in liquid, for instance.

[0025] Then, as illustrated in FIG. 4E, a product resulted from the step illustrated in FIG. 4D is covered with a cover 43 for the purpose of protection of the semiconductor chip 1. Then, the cover 43 is sealed under atmospheric pressure. The cover 43 is made of Cu, Al or SiC, for instance.

[0026] Electrically conductive adhesive 44 such as Ag paste or Cu paste is coated on a lower surface of the cover 43. The adhesive 44 is heated, and hence, cured when the cover 43 is sealed.

[0027] Then, as illustrated in FIG. 4F, the solder balls 101 are absorbed to a positioner 45, and subsequently, the solder balls 101 are mounted onto the lands 7 formed above the wiring layer 2. Thereafter, flux (not illustrated) is applied across the solder balls 101 and the lands 7. Then, the solder balls 7 are caused to reflow to thereby physically connect the solder balls 101 to the lands 7. Then, the flux is washed out.

[0028] Thus, there is completed such a product as illustrated in FIG. 4G. The product is then subject to a temperature cycle test in order to test performances and resistance to damages.

[0029] Then, as illustrated in FIG. 4H, the solder balls 101 are caused to reflow to thereby physically connect the solder balls 101 to the printed wiring board 34. Thus, there is completed a semiconductor device as a final product.

[0030] However, the conventional semiconductor device illustrated in FIGS. 1A to 1C is accompanied with the following problem.

[0031] As mentioned earlier, a semiconductor chip is highly and highly integrated in order to meet requirement of fabricating a semiconductor device in a smaller size and a smaller weight. In a more highly integrated semiconductor chip, the greater number of pins has to be formed per a unit area of a semiconductor chip, resulting in a smaller spacing between adjacent pins. As the number of pins is increased, the number of external terminals, that is, solder balls to be connected to one semiconductor chip is also increased, resulting in a smaller spacing between adjacent solder balls.

[0032] In general, as a spacing between adjacent solder balls is decreased, a contact area through which a solder ball is connected to a wiring layer is also decreased. As a result, a connection strength between a solder ball and a wiring layer is reduced.

[0033] As explained above, in the conventional semiconductor device illustrated in FIGS. 1A to 1C, since a contact area through which the solder ball 101 makes contact with the wiring layer 2 is relatively small, a connection strength between the solder ball 101 and the wiring layer 2 is resultingly small. Accordingly, a connection at which the solder ball 101 is connected to the wiring layer 2 is likely to be broken or cracked, resulting in separation of the solder ball 101 from the wiring layer 2. This results in deterioration in fabrication yield of the semiconductor device.

SUMMARY OF THE INVENTION

[0034] In view of the above-mentioned problem, it is an object of the present invention to provide a semiconductor device which is capable of preventing separation of a solder ball from a wiring layer, and further, to provide a method of fabricating a semiconductor device which method is capable of doing the same.

[0035] In order to solve the above-mentioned problem, the inventors had studied enhancement in strength at a connection between a solder ball and a wiring layer. As a result of the long-term study, the inventors had found out that it would be possible to enhance the strength by forming a copper-tin alloy layer between a solder ball and a wiring layer to thereby prevent occurrence of breakage and cracking at a connection between a solder ball and a wiring layer. The inventors had further found out that it would be possible to form a copper-tin alloy layer by keeping a solder ball mounted on a wiring layer, at a temperature equal to or greater than a melting point of the solder ball for a predetermined period of time in inactive or reducing gas atmosphere.

[0036] Specifically, in one aspect of the present invention, there is provided a semiconductor device including (a) a semiconductor chip, (b) a wiring making electrical connection with the semiconductor chip and containing copper (Cu) therein, (c) a solder ball making contact with the wiring and containing tin (Sn) therein, and (d) a layer made of copper-tin (CuSn) alloy, sandwiched between the wiring and the solder ball, and having a thickness equal to or greater than about 1.87 micrometers.

[0037] If the copper-tin alloy layer had a thickness smaller than 1.87 micrometers, it would be impossible to sufficiently enhance a strength at a connection between a solder ball and a wiring layer, resulting in that the connection might be broken or cracked in a heating step such as a temperature cycle test, in which case, a solder ball is separated from a wiring layer.

[0038] However, it would be possible to enhance a strength at a connection between a solder ball and a wiring layer by forming the above-mentioned copper-tin alloy layer having a thickness equal to or greater than about 1.87 micrometers, between the solder ball and the wiring layer. As a result, it would be possible to prevent or reduce occurrence of breakage or cracking at the connection, ensuring that the solder ball is not separated from the wiring layer. Thus, the present invention enhances a strength at the connection, and hence, enhances a fabrication yield of a semiconductor device.

[0039] It is preferable that the copper-tin alloy layer has a thickness equal to or greater than 2 micrometers, and more preferable that the copper-tin alloy layer has a thickness equal to or greater than 3 micrometers.

[0040] There is further provided a semiconductor device including (a) a semiconductor chip, (b) a wiring making electrical connection with the semiconductor chip, having first and second surfaces, and containing copper (Cu) therein, (c) a solder ball making contact with the wiring at the first surface and containing tin (Sn) therein, (d) a film substrate making contact with the wiring at the second surface, the film substrate being formed with a through-hole reaching the wiring, (e) an electrical conductor filling the through-hole therewith, (f) a first layer covering the electrical conductor therewith at the opposite side of the wiring, and made of gold, and (g) a second layer made of copper-tin alloy, sandwiched between the wiring and the solder ball, and having a thickness equal to or greater than about 1.87 micrometers.

[0041] The above-mentioned semiconductor chip makes it possible to enhance a strength at a connection between a solder ball and a wiring layer by forming the above-mentioned copper-tin alloy layer having a thickness equal to or greater than about 1.87 micrometers, between the solder ball and the wiring layer. As a result, it would be possible to prevent or reduce occurrence of breakage or cracking at the connection, ensuring that the solder ball is not separated from the wiring layer. Thus, the present invention enhances a strength at the connection, and hence, enhances a fabrication yield of a semiconductor device.

[0042] It is preferable that the solder ball contains agglomerates scattering therein, the agglomerates being composed of material other than tin.

[0043] For instance, the agglomerates are composed of lead (Pb) scattering at a density of 20104 mm−3 or greater.

[0044] If the lead agglomerates scatters at a density smaller than 20104 mm−3, a solder ball is likely to be deformed by the lead agglomerates, in which case, a connection between a solder ball and a wiring layer might be broken and cracked in a heating step such as a temperature cycle test, and hence, it would be impossible to prevent separation of the solder ball from the wiring layer.

[0045] However, if a solder ball contains lead agglomerates at a density of 20104 mm−3 or greater, it would be possible to prevent deformation of the solder ball, and hence, occurrence of breakage and cracking at the connection. As a result, it would be possible to prevent separation of the solder ball from the wiring layer which separation is caused by the above-mentioned breakage and cracking of the connection. Thus, the present invention enhances a strength at the connection, and hence, enhances a fabrication yield of a semiconductor device

[0046] It is preferable that the lead agglomerates have a cross-sectional area of 10 square micrometer or smaller in average.

[0047] If the lead agglomerates have a cross-sectional area greater than 10 square micrometer in average, a solder ball is likely to be deformed by the lead agglomerates, in which case, a connection between a solder ball and a wiring layer might be broken and cracked in a heating step such as a temperature cycle test, and hence, it would be impossible to prevent separation of the solder ball from the wiring layer.

[0048] However, if the lead agglomerates have a cross-sectional area of 10 square micrometer or smaller in average, it would be possible to prevent deformation of the solder ball, and hence, occurrence of breakage and cracking at the connection. As a result, it would be possible to prevent separation of the solder ball from the wiring layer which separation is caused by the above-mentioned breakage and cracking of the connection. Thus, the present invention enhances a strength at the connection, and hence, enhances a fabrication yield of a semiconductor device

[0049] The semiconductor device may further include a printed wiring board making electrical connection with the solder ball.

[0050] In another aspect of the present invention, there is provided a method of fabricating a semiconductor device, including the steps of (a) forming a wiring containing copper (Cu), on a substrate, (b) mounting a solder ball containing tin (Sn), on the wiring, and (c) keeping a product resulted from the step (b), in inactive gas atmosphere or in reducing gas atmosphere at a temperature equal to or greater than a melting point of the solder ball.

[0051] In accordance with the above-mentioned method, tin contained in the solder ball is diffused in liquid into the wiring layer containing copper, resulting in that a copper-tin alloy layer is formed between the solder ball and the wiring layer, having a thickness sufficient to prevent the solder ball from being separated from the wiring layer. The thus formed copper-tin alloy layer enhances a strength of a connection between the solder ball and the wiring layer, and hence, ensures that the connection is not broken and cracked. Thus, the present invention enhances a strength at the connection, and hence, enhances a fabrication yield of a semiconductor device.

[0052] The product resulted from the step (b) is kept in an inactive or reducing gas atmosphere for a predetermined period of time sufficient to enhance a strength of a connection between the solder ball and the wiring layer.

[0053] For instance, the product is kept in an inactive or reducing gas atmosphere for an hour or longer.

[0054] There is further provided a method of fabricating a semiconductor device, including the steps of (a) forming a wiring containing copper (Cu), on a substrate, (b) covering the wiring with a resist having a recess through which the wiring appears, (c) forming a through-hole through the substrate so that the through-hole reaches the wiring, (d) filling electrical conductor in the through-hole, (e) covering the electrical conductor with a gold layer, (f) connecting the substrate to a semiconductor chip. (g) mounting a solder ball containing tin (Sn), in the recess, and (h) keeping a product resulted from the step (g), in inactive gas atmosphere or in reducing gas atmosphere at a temperature equal to or greater than a melting point of the solder ball.

[0055] In accordance with the above-mentioned method, tin contained in the solder ball is diffused in liquid into the wiring layer containing copper, resulting in that a copper-tin alloy layer is formed between the solder ball and the wiring layer, having a thickness sufficient to prevent the solder ball from being separated from the wiring layer. The thus formed copper-tin alloy layer enhances a strength of a connection between the solder ball and the wiring layer, and hence, ensures that the connection is not broken and cracked. Thus, the present invention enhances a strength at the connection, and hence, enhances a fabrication yield of a semiconductor device.

[0056] The method may further include the step of forming a gold layer on the wiring in advance of mounting the solder ball on the wiring.

[0057] By forming a gold layer on the wiring and then mounting the solder ball on the gold layer, it would be possible to prevent the wiring layer from being oxidized.

[0058] There is provided a semiconductor device including (a) a semiconductor chip, (b) a wiring making electrical connection with the semiconductor chip and containing copper (Cu) therein, (c) a solder ball making contact with the wiring and containing tin (Sn) therein, and (d) a layer made of copper-tin (CuSn) alloy, sandwiched between the wiring and the solder ball, and having a thickness equal to or greater than about 1.87 micrometers, the semiconductor device being resulted from the steps of (a) forming the wiring on a substrate, (b) mounting the solder ball on the wiring, and (c) keeping a product resulted from the step (b), in inactive gas atmosphere or in reducing gas atmosphere at a temperature equal to or greater than a melting point of the solder ball.

[0059] There is further provided a semiconductor device including (a) a semiconductor chip, (b) a wiring making electrical connection with the semiconductor chip and containing copper (Cu) therein, and (c) a solder ball making contact with the wiring and containing tin (Sn) therein, the solder ball containing lead (Pb) agglomerates scattering therein at a density of 20104 mm−3 or greater, the semiconductor device being resulted from the steps of (a) forming the wiring on a substrate, (b) mounting the solder ball on the wiring, and (c) keeping a product resulted from the step (b), in inactive gas atmosphere or in reducing gas atmosphere at a temperature equal to or greater than a melting point of the solder ball.

[0060] There is still further provided a semiconductor device including (a) a semiconductor chip, (b) a wiring making electrical connection with the semiconductor chip and containing copper (Cu) therein, and (c) a solder ball making contact with the wiring and containing tin (Sn) therein, the solder ball containing lead (Pb) agglomerates scattering therein, the lead agglomerates having a cross-sectional area of 10 square micrometer or smaller in average, the semiconductor device being resulted from the steps of (a) forming the wiring on a substrate, (b) mounting the solder ball on the wiring, and (c) keeping a product resulted from the step (b), in inactive gas atmosphere or in reducing gas atmosphere at a temperature equal to or greater than a melting point of the solder ball.

[0061] The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0062]FIG. 1A is a cross-sectional view of a conventional semiconductor device.

[0063]FIG. 1B is an enlarged view of a connection between a wiring layer and a solder ball.

[0064]FIG. 1C is a cross-sectional view illustrating that the semiconductor device illustrated in FIG. 1A is electrically connected to a printed wiring board.

[0065]FIG. 2A is an enlarged view of a solder ball in the semiconductor device illustrated in FIG. 1A.

[0066]FIG. 2B is a partially enlarged view of a connection between a wiring layer and a solder ball in the semiconductor device illustrated in FIG. 2A.

[0067]FIGS. 3A to 3H are cross-sectional view of a semiconductor device, each illustrating respective steps of a method of fabricating the conventional semiconductor device illustrated in FIG. 1A.

[0068]FIGS. 4A to 4H are cross-sectional view of a semiconductor device, each illustrating respective steps of a method of fabricating the conventional semiconductor device illustrated in FIG. 1A.

[0069]FIG. 5A is a cross-sectional view of a semiconductor device in accordance with a preferred embodiment of the present invention.

[0070]FIG. 5B is an enlarged view of a connection between a wiring layer and a solder ball.

[0071]FIG. 5C is a cross-sectional view illustrating that the semiconductor device illustrated in FIG. 5A is electrically connected to a printed wiring board.

[0072]FIG. 6A is an enlarged view of a solder ball in the semiconductor device illustrated in FIG. 5A.

[0073]FIG. 6B is a partially enlarged view of a connection between a wiring layer and a solder ball in the semiconductor device illustrated in FIG. 6A.

[0074]FIGS. 7A to 7G are cross-sectional view of a semiconductor device, each illustrating respective steps of a method of fabricating the semiconductor device illustrated in FIG. 5A.

[0075]FIGS. 8A to 8I are cross-sectional view of a semiconductor device, each illustrating respective steps of a method of fabricating the semiconductor device illustrated in FIG. 5A.

[0076]FIG. 9 is a graph showing a shear strength of a connection between a solder ball and a wiring layer.

[0077]FIG. 10 illustrates an example of an apparatus for measuring a shear strength of a connection between a solder ball and a wiring layer.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0078]FIGS. 1A to 1C illustrate a semiconductor device in accordance with the first embodiment of the present invention.

[0079] As illustrated in FIG. 1A, the semiconductor device is comprised of a semiconductor chip 1, a film substrate 3, a polyimide adhesive layer 31 adhering the film substrate 3 to the semiconductor chip 1, a resist 32 covering the wiring layer 2 therewith and formed with a land 7 which is a recess formed at a surface thereof, a wiring layer 2 formed on the film substrate 3, a solder ball 11 mounted on the wiring layer 2 in the land 7, a layer 21 (see FIG. 1B) made of copper-tin alloy and sandwiched between the solder ball 11 and the wiring layer 2, a metal 5 filled in a through-hole 4 formed through both the film substrate 3 and the polyimide adhesive layer 31, and a gold (Au) layer 6 covering therewith the metal 5 at a top surface thereof.

[0080] The wiring layer 2 is in electrical connection with the semiconductor chip 1, and contains copper (Cu) therein. The solder ball 11 contains tin (Sn) therein.

[0081] In the semiconductor device in accordance with the first embodiment, the through-hole 4 is formed just above an electrode 12 of the semiconductor chip 12. The solder ball 11 is electrically connected to the electrode 12 through the metal 5 filled in the through-hole 4. It is not always necessary that the solder ball 11 is located just above the electrode 12.

[0082] As illustrated in FIG. 5C, the semiconductor device in accordance with the first embodiment further includes a printed wiring board 34 electrically connected to the solder ball 11.

[0083]FIG. 6A is an enlarged view of the wiring layer 2 and the solder ball 11, wherein the solder ball 11 is composed of SnPb eutectic solder containing tin 22 at 65% and lead at 35%. FIG. 6B is a partially enlarged view of a boundary between the wiring layer 2 and the solder ball 101. As illustrated in FIG. 6B, the CuSn alloy film 21 having a thickness of 3 micrometer to 4 micrometer is sandwiched between the wiring layer 2 and the solder ball 11.

[0084] The solder ball 11 predominantly contains tin (Sn). Though the layer 21 sandwiched between the solder ball 11 and the wiring layer 2 is composed of CuSn alloy in the first embodiment, the layer 21 may be composed of SnPb alloy or SnAg alloy. As an alternative, the layer 21 may be free of Pb. For instance, the layer 21 may be composed of SnAn alloy, SnBi alloy, SnNi alloy, SnCd alloy, SnS alloy, SnAs alloy, or SnZn alloy.

[0085] As mentioned earlier, the CuSn alloy layer 21 is sandwiched between the solder ball 11 and the wiring layer 2 in the first embodiment. The CuSn alloy layer 21 makes it possible to prevent occurrence of breakage and cracking across the solder ball 11 and the wiring layer 2, preventing that the solder ball 11 is separated from the wiring layer 2 due to the breakage and/or cracking across the solder ball 11 and the wiring layer 2. As a result, it would be possible to enhance a fabrication yield of the semiconductor device.

[0086] The CuSn alloy layer 21 has a thickness preferably of 1.87 micrometers or greater, more preferably of 2 micrometers or greater, and most preferably of 3 micrometers or greater.

[0087] When the solder ball 11 contains materials other than tin (Sn), those materials generally exist in the form of agglomerates. As those agglomerates are larger in size, the solder ball 11 is more likely to be deformed, and hence, breakage and cracking are more likely to occur at a connection between the solder ball 11 and the wiring layer 2. Hence, the agglomerates have to be scattered in a smaller size in the solder ball 11.

[0088] For instance, when the solder ball 11 contains lead (Pb) 23 as well as tin (Sn) 22, as illustrated in FIGS. 6A and 6B, it is preferable that the lead 23 scatters in the solder ball 11 in the form of small agglomerates.

[0089] A method of fabricating the semiconductor device in accordance with the first embodiment, illustrated in FIGS. 5A to 5C, is explained hereinbelow with reference to FIGS. 7A to 7G and 8A to 8I.

[0090] First, as illustrated in FIG. 7A, the wiring layer 2 containing copper therein is formed on an upper surface of the film substrate 3, and the adhesive layer 31 is formed on a lower surface of the film substrate 3. The film substrate 3 has a thickness of 12 micrometers, the wiring layer 2 has a thickness of 18 micrometers, and the adhesive layer 31 has a thickness of 10 micrometers. The film substrate 3 is composed of a material having a resistant to a temperature of 250 degrees centigrade or greater, such as polyimide. The adhesive layer 31 is composed of polyimide.

[0091] Then, as illustrated in FIG. 7B, the wiring layer 2 is patterned into a predetermined pattern.

[0092] Then, as illustrated in FIG. 7C, the patterned wiring layer 2 and the film substrate 3 are both covered with the resist 32.

[0093] Then, as illustrated in FIG. 7D, there is formed the through-hole 4 through the adhesive layer 31 and the wiring layer 2, for instance, by means of a laser beam gun.

[0094] Then, as illustrated in FIG. 7E, the through-hole 4 is filled with the metal 5 such as copper or aluminum.

[0095] Then, as illustrated in FIG. 7F, the metal 5 is covered at a top surface thereof with the gold layer 6.

[0096] Then, as illustrated in FIG. 7G, the resist 32 is formed with the land 7 above the wiring layer 2. In later steps, the solder ball 11 is mounted on the wiring layer 2 in the land 7.

[0097] Thus, there is completed a tape substrate 33 comprised of the film substrate 3 having the wiring layer 2 formed on the upper surface. Though FIGS. 7A to 7G illustrate only one land 7, it should be noted that the film substrate 3 is in the form of a sheet, and the film substrate 3 is formed with a plurality of lands 7 in each of which the solder ball 11 is to be mounted in later steps.

[0098] A method of mounting the solder balls 11 on the wiring layer 2 is explained hereinbelow with reference to FIGS. 8A to 8I.

[0099] First, as illustrated in FIG. 8A, the tape substrate 33 resulted from the steps illustrated in FIGS. 7A to 7G is placed with the gold layer 6 being upwardly directed. For simplification, the gold layer 6 is not illustrated in FIG. 8A.

[0100] Then, as illustrated in FIG. 8B, stiffeners 41 are adhered on the tape substrate 33 at its opposite ends. The stiffeners 41 are composed of copper or stainless, for instance.

[0101] Then, as illustrated in FIG. 8C, the semiconductor chip 1 is mounted on the tape substrate 93, surrounded by the stiffeners 41. Then, the gold layer 6 is electrically connected to the electrode 12 of the semiconductor chip 1 through a bonding wire (not illustrated). The connection is accomplished by means of a bonding tool, a heater and a ultrasonic wave generator (not illustrated).

[0102] Then, as illustrated in FIG. 8D, resin 42 is applied between the tape substrate 33 and the semiconductor chip 1, and then, is cured to thereby reinforce a connection between the tape substrate 33 and the semiconductor chip 1. The resin 42 is composed of epoxy resin in liquid, for instance.

[0103] Then, as illustrated in FIG. 8E, a product resulted from the step illustrated in FIG. 8D is covered with a cover 43 for the purpose of protection of the semiconductor chip 1. Then, the cover 43 is sealed under atmospheric pressure. The cover 43 is made of Cu, Al or SiC, for instance.

[0104] Electrically conductive adhesive 44 such as Ag paste or Cu paste is coated on a lower surface of the cover 43. The adhesive 44 is heated, and hence, cured when the cover 43 is sealed.

[0105] Then, as illustrated in FIG. 8F, the solder balls 11 are absorbed to a positioner 45, and subsequently, the solder balls 11 are mounted onto the lands 7 formed above the wiring layer 2. Thereafter, flux (not illustrated) is applied across the solder balls 11 and the lands 7. Then, the solder balls 7 are caused to reflow to thereby physically connect the solder balls 11 to the lands 7. Then, the flux is washed out.

[0106] Thus, there is completed such a product as illustrated in FIG. 8G. The thus obtained product is kept at a temperature equal to or higher than a melting point of the solder ball 11 for a predetermined period of time, for instance, an hour, in inactive or reducing gas atmosphere, as illustrated in FIG. 8H.

[0107] The resultant is then subject to a temperature cycle test in order to test performances and resistance to damages.

[0108] Then, as illustrated in FIG. 8I, the solder balls 11 are caused to reflow to thereby physically connect the solder balls 11 to the printed wiring board 34. Thus, there is completed a semiconductor device as a final product.

[0109] As mentioned earlier, by keeping the product illustrated in FIG. 8G at a temperature equal to or higher than a melting point of the solder ball 11 for a predetermined period of time in inactive or reducing gas atmosphere, tin contained in the solder ball 11 and copper contained in the wiring layer 2 are coupled with each other to thereby form the CuSn alloy layer 21 between the solder ball 11 and the wiring layer 2.

[0110] Herein, an inactive gas atmosphere indicates an atmosphere of gas which does not react with both the solder ball 11 and the wiring layer 2, such as N2, Ar, He and Ne alone or in combination. A reducing gas atmosphere indicates an atmosphere of reducing gas such as CO or H2.

[0111] By keeping the product illustrated in FIG. 8G at a temperature equal to or higher than a melting point of the solder ball 11 for a predetermined period of time in inactive or reducing gas atmosphere, tin contained in the solder ball 11 is diffused in liquid into copper matrix in the wiring layer 2, resulting in that the CuSn alloy layer 21 having a thickness sufficient to prevent separation of the solder ball 11 from the wiring layer 2 is formed between the solder ball 11 and the wiring layer 2. Hence, a connection between the solder ball 11 and the wiring layer 2 could have an enhanced strength, which ensures that the connection is unlikely to be broken and cracked. As a result, it would be possible to reduce defective semiconductor devices in which the solder ball 11 is broken or cracked, and hence, to enhance a fabrication yield of the semiconductor device.

[0112] In the first embodiment, a thin gold layer is not formed on the wiring layer 2 in the land 7 unlike the conventional semiconductor device illustrated in FIG. 1A. However, the formation of the thin gold layer on the wiring layer would prevent the wiring layer 2 from being oxidized and facilitate formation of the CuSn alloy layer 21. Hence, a thin gold layer such as the gold layer 8 illustrated in FIGS. 1A and 1C may be deposited on the wiring layer 2 even in the first embodiment.

EXAMPLE 1

[0113] Hereinbelow is explained a first example of the semiconductor device in accordance with the above-mentioned embodiment, illustrated in FIGS. 5A to 5C. In Example 1, the solder ball 11 is composed of SnPb eutectic solder including Sn at 63% and Pb at 37%. FIG. 6A is an enlarged view of the solder ball 11, and FIG. 6B is a partially enlarged view of the solder ball 11, the CuSn alloy layer 21, and the wiring layer 2.

[0114] As illustrated in FIG. 6B, the CuSn alloy layer 21 is formed between the solder ball 11 and the wiring layer 2. The CuSn alloy layers 21 in the semiconductor device in accordance with the above-mentioned embodiment have a thickness in the range of 1.87 micrometers to 4.0 micrometers. Most of the CuSn alloy layers 21 have a thickness in the range of 3.0 micrometers to 4.0 micrometers.

[0115] In contrast, most of the CuSn alloy layers 21 in the conventional semiconductor device illustrated in FIGS. 2A and 2B have a thickness in the range of 1.0 micrometers to 1.5 micrometers. This indicates that the CuSn alloy layer 21 is thicker in the above-mentioned embodiment than in the conventional semiconductor device.

[0116] Thus, the CuSn layer 21 is required to have a thickness equal to 1.87 micrometers at smallest in order to prevent the solder ball 11 from being separated from the wiring layer 2. As will be understood in view of comparison between the conventional semiconductor device and the above-mentioned embodiment, the CuSn layer 21 having a thickness equal to or greater than 1.87 micrometers can enhance a strength at a connection of the solder ball 11 and the wiring layer 2, resulting in reduction in occurrence of breakage and/or cracking of the connection. This ensures a higher fabrication yield of the semiconductor device.

[0117] As mentioned earlier, when the solder ball 11 contains materials other than tin (Sn), those materials generally exist in the form of agglomerates. The solder ball 11 illustrated in FIGS. 6A and 6B contain lead in the form of agglomerates. As those lead agglomerates 23 are larger in size, the solder ball 11 is more likely to be deformed, and hence, breakage and cracking are more likely to occur at a connection between the solder ball 11 and the wiring layer 2. Hence, the lead agglomerates 23 have to be scattered in a smaller size in the solder ball 11.

[0118] The solder ball 11 illustrated in FIGS. 6A and 6B contains the lead agglomerates 23 at a density of 20104 mm−3 or greater. In contrast, the solder ball 101 in the conventional semiconductor device, illustrated in FIGS. 2A and 2B, contains the lead agglomerates 83 at a density of 15104 mm−3. Thus, it is understood that the solder ball 11 in the semiconductor device in accordance with the above-mentioned embodiment contains the lead agglomerates 23 at a greater density than that of the conventional semiconductor device. That is, the lead agglomerates 23 are scattered more widely than the lead agglomerates 83 in the solder ball 101 in the conventional semiconductor device.

[0119] The lead agglomerates 23 in the solder ball 11 illustrated in FIGS. 6A and 6B have a cross-sectional area in the range of 1 to 10 square micrometers. In contrast, the lead agglomerates 83 in the solder ball 101 illustrated in FIGS. 2A and 2B have a cross-sectional area in the range of 10 to 30 square micrometers. Thus, it is understood that the solder ball 11 in the semiconductor device in accordance with the above-mentioned embodiment contains the lead agglomerates 23 in a smaller size than that of the conventional semiconductor device.

[0120] As mentioned above, the solder ball 11 in Example 1 contains the lead agglomerates 23 at a greater density and in a smaller size than those of the conventional solder ball 101. As a result, the solder ball 11 in Example 1 is unlikely to be deformed, and it would be possible to prevent occurrence of breakage and/or cracking at the connection between the solder ball 11 and the wiring layer 2. Thus, a semiconductor device can be fabricated in a higher fabrication yield.

EXAMPLE 2

[0121] In Example 2, the solder ball 11 is composed of SnPb eutectic solder including Sn at 63% and Pb at 37%, similarly to Example 1. In Example 2, the semiconductor device resulted from the steps illustrated in FIGS. 7A to 7G and 8A to 8G was kept at a temperature equal to or greater than a melting point of the solder ball 11 in N2 gas atmosphere, and then, the printed wiring board 34 was connected to the solder ball 11. Thereafter, a shear strength at the connection between the solder ball 11 and the wiring layer 2 was measured.

[0122] The result of measurement is shown in FIG. 9 in which an axis of ordinate indicates a shear strength in the unit of gram-force (gf) and an axis of abscissa indicates a period of time in the unit of hour during which the semiconductor device is kept at a temperature equal to or greater than a melting point of the solder ball 11 in N2 gas atmosphere.

[0123] In FIG. 9, ◯ indicates a shear strength of the connection, measured when the solder ball 11 is kept at 240 degrees centigrade which is higher than a melting point of CuSn eutectic solder, 183 degrees centigrade, and  indicates a shear strength of the connection, as a reference, measured when the solder ball 11 is kept at 150 degrees centigrade which is lower than a melting point of CuSn eutectic solder, 183 degrees centigrade.

[0124] A shear strength of the connection was measured by means of an apparatus illustrated in FIG. 10. The illustrated apparatus includes a measurement tool 61 by which the solder ball 11 is sheared at the connection between the solder ball 11 and the wiring layer 2 in a direction indicated with an arrow A, that is, a direction substantially parallel to the connection. A shear strength of the connection was measured when the solder ball 11 is sheared by means of the apparatus.

[0125] In Example 2, the solder ball 11 is designed to have a diameter of 0.5 mm, a pitch between adjacent solder balls 11 is 0.8 mm, and the land 7 has a diameter of 0.4 mm. As is obvious in view of FIG. 9, a shear strength is enhanced in a case wherein the semiconductor device is kept at a temperature equal to or greater than a melting point of the solder ball 11 than in a case wherein the semiconductor device is kept at a temperature smaller than a melting point of the solder ball 11. The reason of this is considered that tin contained in the solder ball 11 is diffused in liquid into the wiring layer 2 containing copper by keeping the semiconductor device at a temperature equal to or greater than a melting point of the solder ball 11, and resultingly, a CuSn alloy layer is formed between the solder ball 11 and the wiring layer 2.

[0126] According to the experiment which the inventors had conducted, a shear strength of the connection between the solder ball 11 and the wiring layer 2 can be enhanced by 680 gram-forces or greater by keeping the semiconductor device at a temperature equal to or greater than a melting point of the solder ball 11 for an hour or longer. Thus, it would be possible to have the connection had a strength sufficient to prevent the solder ball 11 from being separated from the wiring layer 2.

[0127] As illustrated in FIGS. 6A and 6B, the solder ball 11 contains lead 23 in the form of agglomerates. That is, the solder ball 11 contains Cu, Sn and Pb. Table 1 shows thermal expansion coefficients and densities of both ingredients Cu, Sn and Pb contained in the solder ball 11 and CuSn alloy of which the layer 21 is composed.

TABLE 1
Material TEC [ppm] Density [g/cm3]
Cu 16.8 8.93
Pb 29 11.34
Sn 21 7.28
Cu-Sn alloy 17.1-17.8

[0128] A thermal expansion coefficient (TEC) is indicated in the unit of ppm, and a density is indicated in the unit of g/cm3.

[0129] The larger the lead agglomerates 23 are in size, more likely the solder balls 11 are to be deformed, and hence, are to be broken or cracked at the connection between themselves and the wiring layer 2. Hence, the lead agglomerates 23 have to be as small as possible in order to prevent generation of deformation in the solder balls 11.

[0130] In view of Table 1, Pb has a greater thermal expansion coefficient than thermal expansion coefficients of Cu, Sn and CuSn alloy, and in addition Pb has a greater density than densities of Cu and Sn. Accordingly, when the semiconductor device is subject to a temperature cycle test, which is to be carried out at a temperature lower than a melting point of the solder balls 11, the lead agglomerates 23 expands to a greater degree than Cu, Sn and CuSn alloy, and resultingly, the lead agglomerates 23 would have deformation to a greater degree than Cu, Sn and CuSn alloy. Thus, the larger the lead agglomerates 23 are in size, more likely deformation is to be generated in the solder ball 11, and in addition, more likely the solder balls 11 are to be broken or cracked at the connection.

[0131] In contrast, in Example 2, the solder balls 11 are kept at a temperature equal to or greater than a melting point thereof, and as a result, the crystal structure of the solder ball 11 is changed so that the lead agglomerates 23 are smaller in size and scattered more widely than the lead agglomerates 83 contained in the conventional solder ball 101 illustrated in FIGS. 2A and 2B.

[0132] As mentioned above, in accordance with Example 2, since the lead agglomerates 23 are smaller in size than the lead agglomerates 83 contained in the conventional solder ball 101, the lead agglomerates 23 would have deformation to a smaller degree, and in addition, since the lead agglomerates 23 are scattered more widely than the lead agglomerates 83 contained in the conventional solder ball 101, deformation caused by the lead agglomerates 23 could be dispersed. As a result, the connection between the solder ball 11 and the wiring layer 2 could have an enhanced strength.

[0133] Though the solder ball 11 is composed of SnPb eutectic solder in Example 2, a material of which the solder ball 11 is composed is not to be limited to that. Unless the solder ball 11 contains tin (Sn), the solder ball 11 may contain other elements. For instance, the solder ball 11 may be composed of SnAg alloy, SnZn alloy, SnCd alloy, SnNi alloy, SnS alloy, SnAs alloy, or SnBi alloy.

[0134] While the present invention has been described in connection with certain preferred embodiments, it is to be understood that the subject matter encompassed by way of the present invention is not to be limited to those specific embodiments. On the contrary, it is intended for the subject matter of the invention to include all alternatives, modifications and equivalents as can be included within the spirit and scope of the following claims.

[0135] The entire disclosure of Japanese Patent Application No. 11-61912 filed on Mar. 9, 1999 including specification, claims, drawings and summary is incorporated herein by reference in its entirety.

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