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Publication numberUS20020000663 A1
Publication typeApplication
Application numberUS 09/195,614
Publication dateJan 3, 2002
Filing dateNov 19, 1998
Priority dateNov 20, 1997
Also published asUS6396146
Publication number09195614, 195614, US 2002/0000663 A1, US 2002/000663 A1, US 20020000663 A1, US 20020000663A1, US 2002000663 A1, US 2002000663A1, US-A1-20020000663, US-A1-2002000663, US2002/0000663A1, US2002/000663A1, US20020000663 A1, US20020000663A1, US2002000663 A1, US2002000663A1
InventorsTakeo Nakayama
Original AssigneeTakeo Nakayama
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device and its manufacturing method
US 20020000663 A1
Abstract
Dummy patterns are formed in signal patterns of a first metal layer, an insulating film covering such patterns is flattened by CMP, and only dummy patterns are selectively etched by anisotropic etching through holes opened at specific intervals. Then the opened holes are filled with an insulating film, and cavities are formed. In the upper part of the cavity, a signal line of the second metal layer is formed. As a result, a semiconductor device is provided by the CMP flattening technology without being accompanied by increase of parasitic capacity between signal lines by metal dummy patterns or shorting due to dust and the like.
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Claims(20)
1. A semiconductor device comprising:
wiring patterns and dummy patterns formed on a first insulating film, and
a second insulating film composed in a region on the first insulating film including the wiring patterns and the dummy patterns, with the surface being flattened,
wherein the dummy patterns are selectively formed in cavities.
2. The device according to claim 1, wherein second wiring patterns are further composed on the second insulating film.
3. The device according to claim 2, wherein the cavities are formed in the lower part of the second wiring patterns.
4. The device according to claim 1, wherein the wiring patterns and the dummy patterns excluding the cavities are formed of a same material.
5. The device according to claim 2, wherein the wiring patterns and the dummy patterns excluding the cavities are formed of a same material.
6. The device according to claim 1, wherein the wiring patterns and the dummy patterns excluding the cavities are formed of a metal material.
7. The device according to claim 2, wherein the wiring patterns and the dummy patterns excluding the cavities are formed of a metal material.
8. A semiconductor device comprising:
wiring patterns and dummy patterns of a different material from the wiring patterns formed on a first insulating film, and
a second insulating film composed in a region on the first insulting film including the wiring patterns and the dummy patterns, with the surface being flattened.
9. The device according to claim 8, wherein the material of the dummy patterns is carbon.
10. The device according to claim 8, wherein the material of the dummy patterns is polycrystalline Si.
11. The device according to claim 8, wherein the material of the dummy patterns is SiN.
12. A method of manufacturing a semiconductor device comprising:
a step of forming plural wiring patterns and plural dummy patterns on a first insulating film,
a step of depositing a second insulating film in a region on the first insulating film including the plural wiring patterns and dummy patterns,
a step of flattening the surface of the second insulating film by using the CMP technology,
a step of selectively providing opening holes in the second insulating film on the plural dummy patterns,
a step of etching the dummy patterns through the opening holes, and
a step of depositing a third insulating film in a region on the second insulating film including the opening holes.
13. The method according to claim 12, further comprising a step of forming second wiring patterns on the third insulating film.
14. The method according to claim 12, wherein the opening holes are disposed in a plurality for one dummy pattern.
15. The method according to claim 13, wherein the opening holes are disposed in a plurality for one dummy pattern.
16. The method according to claim 12, wherein the opening holes are cylindrical in shape.
17. The method according to claim 13, wherein the opening holes are cylindrical in shape.
18. The method according to claim 12, wherein the second wiring pattern is formed above the opening holes.
19. The method according to claim 12, wherein the wiring patterns and dummy patterns are made of a metal material.
20. The method according to claim 13, wherein the wiring patterns and dummy patterns are made of a metal material.
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a multi-layer metal wiring technology.
  • [0002]
    Hitherto, in a semiconductor device having metal wiring of two or more layers, when the lower surface of the metal wiring layer is flattened by CMP (chemical mechanical polishing) technology, a dummy pattern is generally disposed for enhancement of its flatness.
  • [0003]
    [0003]FIG. 27 is a sectional view showing a constitution for disposing two-layer metal wiring on a semiconductor device. After forming a semiconductor element, an interlayer insulating film 6, and the like on a silicon substrate 1, the metal wiring layer of first layer is patterned by lithographic technology and reactive ion etching technology. As a result, a signal line pattern 2 and a dummy pattern 3 for enhancing the flatness in the subsequent CMP process are formed.
  • [0004]
    Consequently, after depositing an SiO2 interlayer insulating film 4 by plasma CVD technology, the interlayer insulating film 4 is flattened by the CMP technology so that the metal pattern of the first layer may not be exposed. Same as in the first layer, next, the signal line pattern 5 is patterned by the lithographic technology and reactive ion etching technology. In this way, in the metal wiring layer of the first layer, a dummy pattern 3 is present besides the signal line 2 and power source wire actually used as wiring.
  • [0005]
    In such conventional constitution, by placing the dummy pattern for enhancing the flatness in CMP flattening process, a problem of increase of parasitic capacity between signal lines occurs. As the parasitic capacity between signal lines increases, not only the signal propagation speed is lowered, but also the noise resistance of the device drops. Besides, owing to the dummy pattern, the resistance to dust becomes weaker, and the signal lines are shorted, and probability of lowering of yield becomes higher. Still worse, since the dummy pattern is in an electrically floating state, simulation by circuit simulator is difficult, and the circuit design is very difficult.
  • BRIEF SUMMARY OF THE INVENTION
  • [0006]
    The present invention is devised to solve the aforementioned problems, and it is hence an object thereof to provide a semiconductor device manufactured by CMP flattening process not accompanied by increase of parasitic capacity between signal lines due to metal dummy pattern used for CMP flattening, shorting due to dust and the like, or complication of circuit design, and a method of manufacturing the same.
  • [0007]
    To achieve the aforementioned object, according to the present invention, after completion of flattening by CMP, a dummy pattern is selectively etched by anisotropic etching through holes opened at specific intervals, and the opened holes are filled with an insulating film, and a cavity is formed. By forming a cavity in the portion of the dummy pattern in this manner, it is intended to solve the problem of parasitic capacity and difficulty of circuit design.
  • [0008]
    That is, the semiconductor device of the present invention comprises wiring patterns and dummy patterns formed on a first insulating film, a second insulating film provided in a region on the first insulating film containing the wiring patterns and dummy patterns, having the surface flattened by CMP, and second wiring patterns disposed on the second insulating film, in which the dummy patterns are formed selectively in cavities.
  • [0009]
    A semiconductor device manufacturing method of the present invention comprises a step of forming plural wiring patterns and plural dummy patterns on the first insulating film, a step of depositing a second insulating film in a region on the first insulating film including the plural wiring patterns and dummy patterns, a step of flattening the surface of the second insulating film by using the CMP technology, a step of selectively providing opening holes in the second insulating film on the plural dummy patterns, a step of etching the dummy patterns through the opening holes, a step of depositing a third insulating film in a region on the second insulating film including the opening holes, and a step of forming second wiring patterns on the third insulating film.
  • [0010]
    Since the dummy patterns are selectively etched by the anisotropic etching after completion of flattening by CMP, cavities are formed in the dummy patterns. As a result, the parasitic capacity between the signal lines decreases, and complication of circuit design can be prevented.
  • [0011]
    Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
  • [0012]
    The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
  • [0013]
    [0013]FIG. 1 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0014]
    [0014]FIG. 2 is a perspective view for explaining a CMP technology;
  • [0015]
    [0015]FIG. 3 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0016]
    [0016]FIG. 4 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0017]
    [0017]FIG. 5 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0018]
    [0018]FIG. 6 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0019]
    [0019]FIG. 7 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0020]
    [0020]FIG. 8 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0021]
    [0021]FIG. 9 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0022]
    [0022]FIG. 10 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0023]
    [0023]FIGS. 11A and 11B are plan views showing a constitution of a semiconductor device of the present invention;
  • [0024]
    [0024]FIGS. 12A and 12B are plan views showing a constitution of a semiconductor device of the present invention;
  • [0025]
    [0025]FIG. 13 is a sectional view for explaining the operation of a semiconductor device of the present invention;
  • [0026]
    [0026]FIG. 14 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0027]
    [0027]FIG. 15 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0028]
    [0028]FIG. 16 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0029]
    [0029]FIG. 17 is a plan view for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0030]
    [0030]FIG. 18 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0031]
    [0031]FIG. 19 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0032]
    [0032]FIG. 20 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0033]
    [0033]FIG. 21 is a plan view for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0034]
    [0034]FIG. 22 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0035]
    [0035]FIG. 23 is a plan view for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0036]
    [0036]FIG. 24 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0037]
    [0037]FIG. 25 is a sectional structural diagram for explaining a manufacturing process of a semiconductor device of the present invention;
  • [0038]
    [0038]FIG. 26 is a plan view for explaining a manufacturing process of a semiconductor device of the present invention; and
  • [0039]
    [0039]FIG. 27 is a sectional structural diagram showing a constitution of a conventional semiconductor device.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0040]
    Referring to the drawings, preferred embodiments of the present invention are described in detail below.
  • [0041]
    [0041]FIG. 1 to FIG. 10 show the manufacturing process of a semiconductor device having metal wiring, and are sectional views for explaining part of the manufacturing process of the present invention having a dummy pattern etching step.
  • [0042]
    First, as shown in FIG. 1, on a P-type silicon single crystal substrate 1, for example, a MOSFET (not shown) and an element separation region 7 are formed by a known technology. Then, a phosphorus-containing SiO2 film is deposited as an interlayer insulating film 6 in 7000 angstroms by chemical vapor phase growth method, and it is further flattened by CMP technology.
  • [0043]
    This CMP is a technology of flattening the film on the wafer while etching by a complex process of chemical reaction and mechanical polishing between the film to be polished and the abrasive. The apparatus consists of, as shown in FIG. 2, a head 20 sucking the wafer with the surface down, and a table 21 on which an independently rotating polishing cloth is adhered, and the head 20 is pressed against the table 21 while injecting the abrasive to polish.
  • [0044]
    The CMP technology is applied in flattening of the interlayer insulating film, burying of multi-layer metal, or burying of poly-Si into trench, and it is used in mass production since start of manufacture of 64M DRAM. When the film to be polished varies, aside from the polishing condition (applied load, table rotating number and the like), the abrasive and polishing cloth are different. As abrasive particles, colloidal silica, cerium oxide, aluminum oxide and the like may be used. As the polishing cloth, various types may be used, including soft and stiff materials, and flat and fluted materials.
  • [0045]
    In application of CMP in device manufacturing process, what is important is the method of detecting the end point to determine when to stop polishing, and the method of cleaning after CMP process. As the end point detecting method, the polishing time is calculated from the polishing rate to the film thickness to be polished, and the end point is detected. Besides, since the CMP is cutting of wafer surface by abrasive, in principle, it is a process accompanied by generation of particles, and the wafer surface is contaminated by metal impurities and the like in the abrasive, and hence after-process cleaning is important. As the method of cleaning, what is most general is the brushing method for removing particles physically. Since several kinds of films appear on the surface after CMP, particles and metal impurities must be removed from all of them. To remove them, surface active agents and the like are added, and the removal level is considerably improved.
  • [0046]
    After such flattening by CMP, as shown in FIG. 3, a metal wiring film 11 (Al—Si—Cu alloy or the like) is formed in a thickness of 7000 angstroms by sputtering. Consequently, as shown in FIG. 4, the metal wiring of the first layer is patterned by lithographic technology and reactive ion etching (RIE) technology. As a result, the wiring 2 used as signal line and dummy pattern 3 for enhancing the flatness in CMP flattening are formed.
  • [0047]
    Consequently, as shown in FIG. 5, an SiO2 interlayer insulating film 8 is deposited in 14000 angstroms by plasma CVD technology. Then, as shown in FIG. 6, the interlayer insulating film 8 is flattened by the CMP technology so that the metal patterns 2, 3 of the first layer may not be exposed.
  • [0048]
    Next, as shown in FIG. 7, by the lithographic technology and reactive ion etching technology in the condition for selectively etching the interlayer insulating film 8, opening holes for dummy pattern etching, that is, holes 9 are opened. In succession, as shown in FIG. 8, by using an etching solution mixing sulfuric acid and hydrogen peroxide by 1:1, the metal pattern 3 of the first layer used as dummy pattern is selectively etched anisotropically.
  • [0049]
    As shown in FIG. 9, sequentially, in order to plug the holes 9 opened for dummy pattern etching, an SiO2 interlayer insulating film 10 is deposited by 7000 angstroms again by plasma CVD technology. As a result, the holes 9 are filled with the insulating film 10. Then, a through-hole for coupling the metal of the first layer and the metal of the second layer is formed by lithographic technology and reactive ion etching technology (not shown).
  • [0050]
    As the metal wiring film of the second layer, a metal wiring film (Al—Si—Cu alloy or the like) is formed in 7000 angstroms by sputtering, and the metal wiring of the second layer is patterned by lithographic technology and reactive ion etching technology as shown in FIG. 10. As a result, the wiring 5 used as the signal line of the metal wiring of the second layer is formed. Then, forming a passivation film by a known technology, the pad portion is selectively opened as electrode.
  • [0051]
    The dummy pattern shape of the present invention for enhancing the flatness in the case of CMP flattening, and various examples of constitution and operation of opening holes for etching the dummy pattern are explained below by referring to FIG. 11 to FIG. 26.
  • [0052]
    [0052]FIG. 11A is a plan view showing an example of constitution of forming a relatively large dummy pattern as compared with the wiring pattern 2, etching this dummy pattern through plural opening holes 9, and forming cavities 12. FIG. 11B is a plan view of fabricating up to the second layer wiring pattern 5 of the upper layer as compared with the constitution in FIG. 11A.
  • [0053]
    [0053]FIG. 12A shows an example of constitution of forming plural rectangular dummy patterns in the wiring pattern 2, etching the dummy patterns through individual opening holes 9, and forming cavities 12. FIG. 12B is a plan view of fabricating up to the second layer wiring pattern 5 of the upper layer as compared with the constitution in FIG. 12A.
  • [0054]
    [0054]FIG. 13 is a sectional view of composing the second layer metal wiring of the upper layer in the upper part of the cavity. As shown in the diagram, when the second layer metal wiring 5 is formed on the cavity 12, the parasitic capacity CP of the upper layer wiring includes the space portion of the cavity 12. As a result, the delay of the signal transmitted through the second layer metal wiring 5 may be smaller as compared with the case in which the dummy pattern is present as metal pattern.
  • [0055]
    [0055]FIG. 14 to FIG. 26 are diagrams for explaining part of the manufacturing process of the semiconductor device according to the present invention, by forming plural dummy patterns in metal wirings, etching these dummy patterns selectively, and forming cavities.
  • [0056]
    First, as shown in FIG. 14, on a P-type silicon single crystal substrate 1, for example, an element separation region 7 and MOSFET (not shown) are formed by a known technology. Then, a phosphorus-containing SiO2 interlayer insulating film 6 is deposited in 7000 angstroms by chemical vapor phase growth method, and it is further flattened by CMP technology.
  • [0057]
    Next, as shown in FIG. 15, a metal wiring film 11 (Al—Si—Cu alloy or the like) is formed in 7000 angstroms by sputtering technology.
  • [0058]
    As shown in FIG. 16, consequently, the metal layer of first layer is patterned by lithographic technology and reactive ion etching technology by RIE. As a result, the wiring 2 used as signal line and dummy pattern 3 for enhancing the flatness in flattening are formed. FIG. 17 shows a plan view at this time. In this way, the dummy pattern 3 for enhancing the flatness when flattening is divided into plural sections.
  • [0059]
    Then, as shown in FIG. 18, an SiO2 interlayer insulating film 8 is deposited in 14000 angstroms by plasma CVD technology. Next, as shown in FIG. 19, the SiO2 interlayer insulating film 8 is flattened by CMP technology so that the first layer metals 2, 3 may not be exposed.
  • [0060]
    Consequently, as shown in FIG. 20, by lithographic technology, opening holes 9 for dummy pattern etching are formed selectively in the interlayer insulating film 8. A plan view at this time is shown in FIG. 21. Of the divided dummy patterns, only those free from problem in strength when cavities are formed are opened to form holes 9.
  • [0061]
    As shown in FIG. 22, by a chemical solution mixing sulfuric acid and hydrogen peroxide, the first layer metal pattern used as dummy pattern is selectively removed. FIG. 23 shows a plan view at this time. The arranged dummy patterns are removed so as to be free from problem in strength.
  • [0062]
    Next, as shown in FIG. 24, to plug the holes 9 opened for removing the dummy pattern, an SiO2 interlayer insulating film 19 is deposited in 7000 angstroms again by plasma CVD technology. As a result, the holes 9 are filled with the insulating film. Then, a through-hole for coupling the metal of the first layer and the metal of the second layer is formed by lithographic technology and reactive ion etching technology (not shown).
  • [0063]
    As the metal wiring film of the second layer, an Al—Si—Cu alloy is formed in 7000 angstroms by sputtering, and the metal wiring of the second layer is patterned by lithographic technology and reactive ion etching technology as shown in FIG. 25. As a result, the wiring 5 used as the signal line of the metal wiring of the second layer is formed. FIG. 26 is a plan view at this time. Then, a passivation film is formed by a known technology, the pad portion is selectively opened as electrode.
  • [0064]
    In the description of the foregoing embodiments, the first layer metal is used in forming the dummy pattern, but SiN, poly-Si, carbon or the like may be also used. When such material is used, by forming films of such materials after forming the metal wiring of the first layer, and patterning the films by lithographic technology, the dummy patterns can be formed.
  • [0065]
    As described herein, according to the present invention, the flatness of the CMP can be enhanced by using the dummy pattern, and the parasitic capacity of the wiring can be substantially decreased. In the circuit design, moreover, metal wiring of floating is not needed, and the difficult of circuit design is extremely improved.
  • [0066]
    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6951806 *Nov 30, 1999Oct 4, 2005Sun Microsystems, Inc.Metal region for reduction of capacitive coupling between signal lines
US7064053Aug 29, 2003Jun 20, 2006Stmicroelectronics SaProcess for fabricating an electrical circuit comprising a polishing step
US7648907Mar 23, 2007Jan 19, 2010Fujitsu LimitedSemiconductor device, wiring substrate forming method, and substrate processing apparatus
US7704856Mar 23, 2007Apr 27, 2010Fujitsu LimitedSemiconductor device, wiring substrate forming method, and substrate processing apparatus
US8116894 *Dec 19, 2008Feb 14, 2012Ricoh Company, Ltd.Chemical mechanical polishing method and chemical mechanical polishing device
US20040087140 *Aug 29, 2003May 6, 2004Srdjan KordicProcess for fabricating an electrical circuit comprising a polishing step
US20070184646 *Mar 23, 2007Aug 9, 2007Fujitsu LimitedSemiconductor device, wiring substrate forming method, and substrate processing apparatus
US20090170323 *Dec 19, 2008Jul 2, 2009Masanori MiyataChemical mechanical polishing method and chemical mechanical polishing device
EP1394845A2 *Aug 13, 2003Mar 3, 2004Philips Electronics N.V.Method for making an electric circuit including a polishing step
EP1394845A3 *Aug 13, 2003Jan 27, 2010STMicroelectronics S.A.Method for making an electric circuit including a polishing step
WO2005041273A2 *Oct 12, 2004May 6, 2005Infineon Technologies AgMethod for reducing parasitic couplings in circuits
WO2005041273A3 *Oct 12, 2004Sep 9, 2005Infineon Technologies AgMethod for reducing parasitic couplings in circuits
Classifications
U.S. Classification257/758, 257/E21.244, 257/E21.581, 257/E23.144
International ClassificationH01L21/3105, H01L21/3205, H01L21/768, H01L23/522, H01L23/532
Cooperative ClassificationH01L2924/0002, H01L21/7682, H01L23/5222, H01L21/31053, H01L23/53295
European ClassificationH01L23/532N4, H01L23/522C, H01L21/768B6, H01L21/3105B2
Legal Events
DateCodeEventDescription
Nov 19, 1998ASAssignment
Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NAKAYAMA, TAKEO;REEL/FRAME:009568/0163
Effective date: 19981113
Nov 4, 2005FPAYFee payment
Year of fee payment: 4
Jan 4, 2010REMIMaintenance fee reminder mailed
May 28, 2010LAPSLapse for failure to pay maintenance fees
Jul 20, 2010FPExpired due to failure to pay maintenance fee
Effective date: 20100528