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Publication numberUS20020001890 A1
Publication typeApplication
Application numberUS 09/887,288
Publication dateJan 3, 2002
Filing dateJun 22, 2001
Priority dateJun 28, 2000
Also published asUS6380013
Publication number09887288, 887288, US 2002/0001890 A1, US 2002/001890 A1, US 20020001890 A1, US 20020001890A1, US 2002001890 A1, US 2002001890A1, US-A1-20020001890, US-A1-2002001890, US2002/0001890A1, US2002/001890A1, US20020001890 A1, US20020001890A1, US2002001890 A1, US2002001890A1
InventorsJung-Ho Lee
Original AssigneeJung-Ho Lee
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for forming semiconductor device having epitaxial channel layer using laser treatment
US 20020001890 A1
Abstract
A method for fabricating a semiconductor device, and, more particularly, a method for fabricating a transistor using an epitaxial channel and a laser thermal treatment is disclosed. The method for forming a semiconductor device includes the steps of: forming a delta doping layer having impurity ions on a semiconductor substrate with a low energy ion-implantation; activating the impurity ions within the delta doping layer by thermally treating a surface of the semiconductor substrate with a laser; forming a channel epitaxial layer on the semiconductor substrate; forming a gate insulation layer and a gate electrode on the channel epitaxial layer in this order; and forming a source/drain region in the semiconductor substrate. Improved current drivability of the semiconductor device is achieved by an increase in the ion activity to adjust the threshold voltage. The delta doping effect through the low energy ion-implantation is maximized.
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Claims(20)
What is claimed:
1. A method for forming a semiconductor device comprising the steps of:
forming a doping layer having impurity ions on a semiconductor substrate with a low energy ion-implantation;
activating the impurity ions within the doping layer by thermally treating a surface of the semiconductor substrate with a laser;
forming a channel epitaxial layer on the semiconductor substrate;
forming a gate insulation layer on the channel epitaxial layer in this order;
forming a gate electrode on the gate insulation layer; and
forming a source/drain region in the semiconductor substrate.
2. The method as recited in claim 1, wherein the doping layer is formed by implanting boron ions into the semiconductor substrate and wherein the boron ions have a dose ranging from about 11012 to about 51013 atms/cm2 at a voltage ranging from about 0.1 to about 5 keV.
3. The method as recited in claim 1, wherein the doping layer is formed by implanting BF2 ions into the semiconductor substrate and wherein the BF2 ions have a dose ranging from about 11012 to about 51013 atms/cm2 at a voltage rate ranging from about 0.5 to about 25 keV.
4. The method as recited in claim 1, wherein the laser is a 308 nm-XeCl laser and the laser has a power ranging from about 0.1 to about 2 J/cm2.
5. The method as recited in claim 1, further comprising the step of making the surface of the semiconductor substrate amorphous by implanting silicon ions into the semiconductor substrate.
6. The method as recited in claim 1, further comprising the step of melting the surface of the semiconductor substrate by controlling a power of the laser.
7. The method as recited in claim 1, wherein the channel epitaxial layer is formed by LPCVD (Low Pressure Chemical Vapor Deposition) or UHV CVD (Ultra High Vacuum Chemical Vapor Deposition).
8. The method as recited in claim 7, wherein the LPCVD comprises the step of applying a hydrogen hardening to the semiconductor substrate for a time period ranging from about 1 minute to about 5 minutes at a temperature ranging from about 800 C. to about 900 C.
9. The method as recited in claim 8, wherein the channel epitaxial layer is formed by a gas mixture of dichlorosilane having a flow rate ranging from about 30 sccm to about 300 sccm and HCl having a flow rate ranging from about 30 sccm to about 200 sccm in a processing chamber for a time period ranging from about 3 minutes to about 10 minutes at a pressure ranging from about 10 torr to about 100 torr and at a temperature ranging from about 750 C. to about 950 C.
10. The method as recited in claim 7, wherein the channel epitaxial layer is formed by UHV CVD which forms the epitaxial silicon layer using silane or disilane at a pressure ranging from about 0.01 torr to about 1 torr and a temperature ranging from about 600 C. to about 700 C.
11. A semiconductor device formed using the method of claim 1.
12. A semiconductor device formed using the method of claim 2.
13. A semiconductor device formed using the method of claim 3.
14. A semiconductor device formed using the method of claim 4.
15. A semiconductor device formed using the method of claim 5.
16. A semiconductor device formed using the method of claim 6.
17. A semiconductor device formed using the method of claim 7.
18. A semiconductor device formed using the method of claim 8.
19. A semiconductor device formed using the method of claim 9.
20. A semiconductor device formed using the method of claim 10.
Description
    FIELD OF THE INVENTION
  • [0001]
    The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for fabricating a transistor using an epitaxial channel and a laser thermal treatment.
  • DESCRIPTION OF PRIOR ART
  • [0002]
    Recently, low energy ion-implantation and epitaxial channel processes have been considered as a technique to form highly integrated circuits having a line width of 0.1 μm or less because these processes may improve the short channel effect (SCE) at a low threshold voltage.
  • [0003]
    [0003]FIG. 1 is a cross-sectional view illustrating a method for forming a conventional semiconductor device. As shown in FIG. 1, a channel ion-implantation layer 12 and an epitaxial silicon layer 13 are formed on a semiconductor substrate 11 in this order. Accordingly, to guarantee the quality of the semiconductor device, at least two conditions should be satisfied. First, a profile of the implanted boron ions should be maintained over the epitaxial growing process and the following thermal treatments. Second, since the epitaxial silicon layer 13 is used as a channel, a high-quality epitaxial layer should grow without any interfacial boundary between the epitaxial silicon layer 13 and the semiconductor substrate 11.
  • [0004]
    However, as of now, the doping profile of the boron ions deteriorates at a temperature of 800 C. for the following epitaxial growing and a rapid thermal processing (RTP) at 950 C. for about 20 seconds. Also, since the epitaxial silicon layer grows on the semiconductor substrate into which the impurities are implanted, the impurities, such as oxygen, may form a layer between the epitaxial silicon layer and the semiconductor substrate. Such a layer may damage the physical characteristics of the epitaxial channel.
  • SUMMARY OF THE DISCLOSURE
  • [0005]
    A method for forming electrically stable semiconductor device by thermally treating a semiconductor substrate with a laser is disclosed.
  • [0006]
    A method for forming a thin semiconductor device having a decreased tunneling leakage current is also disclosed.
  • [0007]
    A method for forming a semiconductor device is disclosed which comprises the steps of: forming a delta doping layer having impurity ions on a semiconductor substrate with a low energy ion-implantation; activating the impurity ions within the delta doping layer by thermally treating a surface of the semiconductor substrate with a laser; forming a channel epitaxial layer on the semiconductor substrate; forming a gate insulation layer and a gate electrode on the channel epitaxial layer in this order; and forming a source/drain region in the semiconductor substrate.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0008]
    [0008]FIG. 1 is a cross-sectional view illustrating a method for forming a conventional semiconductor device;
  • [0009]
    [0009]FIGS. 2A to 2D are cross-sectional views illustrating one disclosed method for forming a semiconductor device;
  • [0010]
    [0010]FIG. 3 is a plot illustrating the doping profile of the boron ions according to the disclosed method; and
  • [0011]
    [0011]FIG. 4 is a plot showing threshold voltage and a variation of the threshold voltage in a 0.70 μm-nMOS.
  • DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS
  • [0012]
    Hereinafter, the present invention will be described in detail referring to the accompanying drawings.
  • [0013]
    Referring to FIG. 2A, a field oxide layer (not shown) is formed in a semiconductor substrate 21. An ion implantation for forming a well 22 is carried out by implanting impurity ions into the exposed semiconductor substrate 21 and the RTP is carried out at a temperature of approximately 950 C. for a few seconds in order to activate the implanted ions. After a screen oxide layer (not shown) is formed on the semiconductor substrate 21 to prevent the semiconductor substrate 21 from being damaged by the following high-energy ion implantation, a delta doping layer 23 is formed by implanting channel ions to adjust the threshold voltage into the semiconductor substrate 21 and the screen oxide layer is removed. At this time, in the ion implantation for adjusting the threshold voltage, the acceleration energy is low and then the implantation depth is very shallow on the semiconductor substrate 21. Boron or BF2 ions, as channel ions, may be used. In the case of boron ions, a dose for the implantation may range from about 11012 to about 51013 atms/cm2 at 0.1keV to about 5keV and, in the case of BF2 ions, a dose for the implantation may range from about 11012 to about 51013 atms/cm2 at a voltage ranging from about 0.5 keV to about 52 keV.
  • [0014]
    Referring to FIG. 2B, after performing the channel ion-implantation process, a laser thermal processing (LTP) 24 is applied to the semiconductor substrate 21. In the LTP, a surface of the semiconductor substrate 21 is melted and instantaneously thereafter re-crystallized. The ions in the surface of the semiconductor substrate 21, which has been treated by the LTP, are not diffused throughout the semiconductor substrate 21 in the following processes, but uniformly distributed. That is, since the ions hardly diffuse, more activated ions may be obtained. Further, the ions in a region, which is treated by the LTP, are suppressed in the following thermal treatments so that the preferred doping profile (Super Steep Retrograde; SSR) is maintained after the rapid thermal processing for the epitaxial silicon layer or source/drain region.
  • [0015]
    In an embodiment, the laser used in the LTP is a 308 nm-XeC1 laser and its energy ranges from about 0.1 J/cm2 to about 2 J/cm2. Instantaneously melting and recrystallization of the semiconductor substrate 21 in the LTP remove the impurities contained in the semiconductor substrate 21. Accordingly, it is possible to improve the quality of an epitaxial silicon layer by growing it on the impurity-removed semiconductor substrate 21.
  • [0016]
    Furthermore, in order to maximize the effect of the LTP, it may be possible to maximize the silicon melting during the LTP by making the surface of the semiconductor substrate 21 amorphous before performing the laser irradiation. In another method, it may be possible to melt the surface of the semiconductor substrate 21 by controlling the power of laser, regardless of the thickness of the amorphous layer.
  • [0017]
    Referring to FIG. 2C, an epitaxial silicon layer 25 for a channel is formed on the semiconductor substrate 21, which has been treated by the LTP, using the selective epitaxial silicon growing method. The epitaxial silicon layer 25, which is an undoped silicon layer, is formed to a thickness ranging from about 100 Å to about 500 Å by a LPCVD (Low Pressure Chemical Vapor Deposition) or a UHV CVD (Ultra High Vacuum Chemical Vapor Deposition) method.
  • [0018]
    In the case of a LPCVD method, after a hydrogen hardening procedure is applied in-situ to the semiconductor substrate 21 at a temperature ranging from about 800 C. to about 900 C. for a time period ranging from about 1 minute to about 5 minutes, the epitaxial silicon layer 25 is formed by using a gas mixture of dichlorosilane at a flow rate ranging from about 30 sccm to about 300 sccm and HCl at a flow rate ranging from about 30 sccm to about 200 sccm, at a pressure ranging from about 10 torr to about 100 torr and a temperature ranging from about 750 C. to about 950 C., for a time period ranging from about 3 minutes to about 10 minutes. In the case of the UHV CVD, the epitaxial silicon layer 25 is formed by using silane or disilane at a pressure ranging from about 0.01 torr to about 1 torr and a temperature ranging from about 600 C. to about 700 C. As stated above, if an epitaxial layer formed on the semiconductor substrate 21, which is treated by the laser, is used as a channel layer, a junction leakage current may be decreased due to the laser shock.
  • [0019]
    Referring to FIG. 2D, after forming a gate oxide layer 26 and a polysilicon layer on the epitaxial silicon layer 25, a gate electrode 27 is formed by patterning the polysilicon layer and an oxide spacer 28 is formed on the sidewalls of the gate electrode 27. A source/drain 29 is formed on the semiconductor substrate 21 using the gate electrode 27 and an oxide spacer 28 as an ion-implantation mask. In the case where a thermal oxide layer is used as a gate oxide layer and an ultra-thin device is required to have the thermal oxide layer with a thickness of 40 Å or less, a conventional device formed without the above-mentioned laser treatment may not achieve a stable operation because the tunneling leakage current.
  • [0020]
    However, since the epitaxial silicon layer 25 is formed on the semiconductor substrate 21, in which the impurities such as oxygen are reduced, and thereafter a thermal oxide layer is formed as a gate oxide layer, the tunneling leakage current decreases by up to 50%. Accordingly, in the case where the laser thermal treatment is applied to the semiconductor substrate 21 before the epitaxial silicon layer 25 is formed, the decrease of the leakage current may be maximized by the removal of impurities, such as oxygen.
  • [0021]
    [0021]FIG. 3 is a plot showing the doping profile of the boron ions according to the present invention. As shown in FIG. 3, a sharp doping profile is maintained at a specific depth after the thermal treatment for forming the epitaxial silicon layer 25 and the source/drain 29. That is, the delta doping layer 23 maintains such a sharp doping profile (Z) at a specific depth, the thickness (X) of the epitaxial silicon layer 25, by performing the laser treatment.
  • [0022]
    [0022]FIG. 4 is a plot showing threshold voltage and a variation of the threshold voltage in a 0.70 μm-nMOS. As shown in FIG. 4, if the LTP is not carried out, the low threshold voltage in the epitaxial channel region is caused by the loss of the boron ions. In the case of the LTP with a power of 0.38 J/cm2, although the absolute value of the threshold voltage increases, the variation of the threshold voltage between the chips in a wafer increases because the boron ions are lost at the following RTP (rapid thermal processing) due to the weak strength of the laser treatment. In the case of the LTP with a sufficient power of 0.42 J/cm2, the variation of the threshold voltage decreases with a high threshold voltage because the loss of the boron ions is restrained at the time of the following thermal processes.
  • [0023]
    As apparent from the above, the disclosed method improves current drivability of the semiconductor device by increase the ion activity to adjust the threshold voltage through the laser thermal treatment. Furthermore, the disclosed method maximizes the delta doping effect through the low energy ion-implantation.
  • [0024]
    Although the preferred embodiments of the disclosed method have been disclosed for illustrative purpose, those skilled in the art will appreciate that various modifications, additions and substitutes are possible, without departing from the scope and spirit of the present invention as described in the accompanying claims.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6380013 *Jun 22, 2001Apr 30, 2002Hyundai Electronics Industries Co., Ltd.Method for forming semiconductor device having epitaxial channel layer using laser treatment
US6743291 *Jul 9, 2002Jun 1, 2004Chartered Semiconductor Manufacturing Ltd.Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth
US7846803May 31, 2007Dec 7, 2010Freescale Semiconductor, Inc.Multiple millisecond anneals for semiconductor device fabrication
US8778786May 29, 2012Jul 15, 2014Suvolta, Inc.Method for substrate preservation during transistor fabrication
US8858818 *Sep 30, 2010Oct 14, 2014Suvolta, Inc.Method for minimizing defects in a semiconductor substrate due to ion implantation
US20040007170 *Jul 9, 2002Jan 15, 2004Chartered Semiconductor Manufacturing Ltd.Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth
US20080299750 *May 31, 2007Dec 4, 2008Spencer Gregory SMultiple millisecond anneals for semiconductor device fabrication
US20120083132 *Sep 30, 2010Apr 5, 2012Pushkar RanadeMethod for minimizing defects in a semiconductor substrate due to ion implantation
DE102008056195B4 *Nov 6, 2008May 23, 2013Infineon Technologies Austria AgVerfahren zum Herstellen einer Epitaxieschicht und Verfahren zum Herstellen eines Halbleiterbeuelements
WO2008150683A1 *May 19, 2008Dec 11, 2008Freescale Semiconductor Inc.Multiple millisecond anneals for semiconductor device fabrication
WO2008157067A1 *Jun 5, 2008Dec 24, 2008The Regents Of The University Of CaliforniaSolid solution lithium alloy cermet anodes
Classifications
U.S. Classification438/184, 257/E29.254, 257/E21.347, 257/E21.102
International ClassificationH01L21/265, H01L21/205, C23C14/48, H01L21/336, H01L29/772, H01L21/20, H01L21/268, H01L29/78, C23C16/24
Cooperative ClassificationH01L21/02532, H01L29/7725, H01L29/6659, H01L21/268, H01L21/02381, H01L21/0262
European ClassificationH01L29/66M6T6F11B3, H01L29/772C
Legal Events
DateCodeEventDescription
Sep 10, 2001ASAssignment
Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, R
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, JUNG-HO;REEL/FRAME:012155/0117
Effective date: 20010618
Oct 7, 2005FPAYFee payment
Year of fee payment: 4
Sep 30, 2009FPAYFee payment
Year of fee payment: 8
Aug 28, 2013FPAYFee payment
Year of fee payment: 12