|Publication number||US20020001900 A1|
|Application number||US 08/940,897|
|Publication date||Jan 3, 2002|
|Filing date||Sep 30, 1997|
|Priority date||Sep 30, 1997|
|Also published as||CN1125486C, CN1213172A, EP0905771A2, EP0905771A3, US6383864|
|Publication number||08940897, 940897, US 2002/0001900 A1, US 2002/001900 A1, US 20020001900 A1, US 20020001900A1, US 2002001900 A1, US 2002001900A1, US-A1-20020001900, US-A1-2002001900, US2002/0001900A1, US2002/001900A1, US20020001900 A1, US20020001900A1, US2002001900 A1, US2002001900A1|
|Inventors||Gerd Scheller, Martin Gall, Reinhard J. Stengl|
|Original Assignee||Gerd Scheller, Martin Gall, Reinhard J. Stengl|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (6), Classifications (7), Legal Events (10)|
|External Links: USPTO, USPTO Assignment, Espacenet|
 This invention relates to memory cells for use in a dynamic random access memory (DRAM) and, more particularly, to a memory cell that uses a dielectrically-filled vertical trench as a storage node and a vertical transistor as a switch located over the trench.
 DRAMS have become among the most important of the integrated circuit devices and are the source of continuing research and development which, in particular, aims to increase their storage capacity and writing and reading speeds. This has necessitated the use of smaller and more closely spaced memory cells for use in the memory arrays. Of increasing significance are memory cells in which the storage node is provided by a polysilicon-filled trench in a silicon chip and the switching transistor is a vertical transistor located in the chip over the trench. It is known that a DRAM that uses a MOSFET as the switching transistor. The two output current terminals of the transistor alternate between source and drain roles as the storage node is charged and discharged. As such, each of these terminals can be described as a source/drain and a drain/source, as is appropriate for the particular role. For purposes of discussion, these terminals are simply referred to as a source/drain. The vertical transistor is located over the storage node in a manner which renders the surface area of the chip used by the cell to be essentially the same as that used by the vertical trench. Ideally, a cell using a vertical transistor can provide higher packing densities than a cell that uses a horizontal switching transistor that is positioned adjacent to the trench that provides the storage node. One type of a vertical transistor over a vertical trench cell is described in U.S. patent application Ser. No. 08/770,962, filed on Dec. 20, 1996, in which Norbert Arnold is the inventor and the assignee is the same as that of the present application.
 A memory cell of the present invention has a unique structure fabricated by a novel process. In one embodiment, a semiconductor chip is first provided with a vertical trench to be used in forming the storage capacitor of the cell. After the trench is made, the dielectric of the capacitor is formed by coating its walls with a dielectric material. The storage node of the capacitor is provided by a doped polysilicon fill of the trench. The top portion of the trench is provided with essentially monocrystalline silicon, suitable for forming one source/drain of the vertical transistor. An additional silicon layer, intermediately placed between two dielectric layers, is subsequently deposited over the chip. The three layers are apertured in the region over the trench to expose the top of the fill. Typically, this layer is polysilicon. The walls of the additional polysilicon layer that were exposed in the aperturing operation are oxidized to form the gate dielectric of the transistor. The aperture is then filled with silicon that is appropriate to form the intermediate layer of the transistor in which there is to be created during operation the inversion layer that forms the channel between the source/drain regions of the transistor. Ultimately an additional silicon layer is formed that will form with this intermediate layer the second source/drain region of the transistor. A bit line connection is made to this last-mentioned layer, and a word line is provided by the apertured polysilicon layer.
 Another embodiment of the present invention is directed to a memory cell that is for use in a memory array of rows and columns of memory cells within a monocrystalline bulk portion of a silicon chip and that is addressed by word lines and bit lines. The memory cell comprises a capacitor, a vertical transistor, a word line, and a bit line. The capacitor comprises a vertical trench filled with silicon and having a layer of dielectric along its wall that isolates the silicon fill from the bulk portion of the chip. The vertical transistor is superposed over the trench and has a first source/drain merged with the silicon at the top of the trench, an intermediate silicon layer that is merged with the silicon fill at the top of the trench to form the first source/drain region, and in which an inversion layer is to be created to form a conductive channel, a second source/drain region overlying the intermediate silicon layer, a gate dielectric layer surrounding the intermediate silicon layer, and a gate surrounding the gate dielectric layer and extending along the surface of the chip and dielectrically insulated therefrom and being coupled to a word line. The bit line is in electrical contact with the second source/drain and otherwise extends over the surface of the trench and is electrically insulated from the word line and from the chip.
 In another embodiment, the invention is a novel process of fabricating the cell that includes imparting seed information to the polysilicon deposited in the trench. This seed information makes it possible to provide a semiconductor intermediate layer wherein the channel of the transistor can be created.
 In another embodiment, the present invention is directed to a process for making a memory cell. The process comprises the steps of forming a trench in a semiconductor chip of one conductivity type; forming a dielectric layer over the walls of the trench; filling the trench with polysilicon of a conductivity type opposite that of the chip; growing an epitaxial silicon layer over the surface of the chip of sufficient thickness for forming over the top of the trench a layer of essentially monocrystalline silicon of a conductivity that is opposite that of the chip for serving as a first source/drain; forming a first dielectric layer over the surface of the chip; forming a polysilicon layer of the conductivity type opposite that of the chip over the surface of the first dielectric layer; forming a second dielectric layer over the surface of said polysilicon layer; etching an opening through the first and second dielectric layers and said polysilicon layer to bare the essentially monocrystalline silicon over the top of the trench; forming a silicon oxide layer selectively along the sidewall of the opening in the polysilicon layer; growing monocrystalline silicon of the one conductivity type in the opening for forming an intermediate layer in which there will be formed the channel of a vertical transistor in which the silicon oxide layer over the sidewall of said polysilicon layer of the opening serves as the gate dielectric; and depositing a conductive layer of the opposite conductivity type over the top surface of the chip that contacts the intermediate silicon layer for serving as a second source/drain and bit line of the cell.
 The invention will be better understood from the following more detailed description taken in conjunction with the accompanying drawing.
FIG. 1 is an electrical circuit schematic of a standard memory cell that includes a transistor and a capacitor of the kind used in DRAMS;
FIG. 2 is a cross section of a portion of a silicon chip including a memory cell that has the electrical schematic of the cell of FIG. 1 and comprises a vertical trench for a capacitor and a superposed vertical transistor, in accordance with the present invention;
FIG. 3 is a top of a memory array using vertical transistors superposed over vertical trenches, in accordance with the present invention; and
 FIGS. 4-10 show a portion of a silicon chip in various stages of the formation therein of a memory cell of the kind shown in FIG. 2 by one process in accordance with the present invention.
FIG. 1 shows an electrical circuit schematic of a memory cell 10. Such a cell is employed, for example, in a random access memory (RAM) integrated circuit (IC) or chip. Such a cell can also be used in a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), or other memory chip. The cell includes a MOS transistor 12 in series with a capacitor 14. Transistor 12 has first and second output current electrodes 12A and 12B, respectively, and a gate electrode 12C. Gate electrode 12C of the switching transistor is connected to a word line of the DRAM array. Electrode 12A serves as the drain of the transistor when positive current flows therefrom through transistor 12 and into electrode 12B, which then serves the source. This occurs when logic information (data, signal bits, i.e., a “1” or a “0”) is read into or refreshed into memory cell 10. Electrode 12B serves as the drain when information is read out of memory cell 12 as current flows from electrode 12B through transistor 12 to electrode 12A which serves as the source. However, as mentioned earlier, for simplicity, each will be described as a source/drain of transistor 12. Capacitor 14 has first (14A) and second (14B) plates. Plate 14B is typically coupled to a reference voltage, which is shown as ground 17 in the drawing. In some instances, it may be desirable to use some other reference voltage on plate 14B, such as Vpp/2. Transistor 12 is switched on to facilitate current flow from a bit line 18, which is connected to electrode 12A, to capacitor 14. It is switched off to isolate capacitor 14 from the bit line 18. A signal corresponding to a bit of information (logic information) is stored as charge on capacitor 14. When appropriate signals are applied to the word line 19 and to the bit line 18, data (“1” or a “0”) is stored as charge on the capacitor 14 where it is held for a useful time. Because of leakage from storage node 16, it is generally necessary to refresh the stored data periodically.
FIG. 2 shows a structure of a memory cell 11 in accordance with the invention. A plurality of memory cells are interconnected to form an array or arrays. Such arrays are used to form memory integrated circuits such as DRAMs, synchronous DRAMs (SDRAMs), or other memory ICs. The memory cell 11 is shown formed in a portion of a semiconductive chip 20, such as a semiconductor wafer. The wafer comprises, for example, silicon. Other semiconductor wafers, including silicon on insulator (SOI) or gallium arsenide, are also useful. The wafer can be undoped or doped lightly or heavily with dopants having a first conductivity. In one embodiment, the chip includes a bulk portion that is advantageously a p-type monocrystalline silicon. Memory cell has the electrical schematic as that shown in FIG. 1. The chip 20, which includes a bulk monocrystalline portion 21, comprises a trench 22. In one embodiment, the trench includes a substantially square cross section filled with, for example, heavily doped n+ type polycrystalline silicon 23 that serves as the storage node 16 (FIG. 1) of memory cell 11. Trenches with other shaped cross section are also useful. The n+polysilicon fill also corresponds to one plate 14A (FIG. 1) of the capacitor 14 merged with a source\drain 12B of the transistor 12.
 A dielectric layer 24 surrounds the sidewalls and bottom of the trench 22 and serves as the dielectric of the capacitor 14. Optionally, a heavily doped n+type layer 26 surrounds the outside of the trench 22 insulated from its fill 23 by the dielectric layer 24. Layer 26 serves as the other plate 114B (FIG. 1) of the capacitor 14. The p-type bulk 21 of the chip 20 typically is maintained at a reference potential, typically ground, as discussed above. Other reference potentials, such as Vpp/2, are also useful.
 Located over the trench 22 is a vertical transistor that corresponds to transistor 12. The vertical MOSFET transistor includes n+type layers 34 and 37, each generally circular in cross section, that correspond to source/drain 12B and source/drain 12A of FIG. 1 and so form the two output current terminals of the transistor. Intermediate between these extend the p-type layer 30 within which there will be created the n-type inversion layer (not shown) to serve as the conductive channel between the layers 34 and 37 when the gate voltage is such as to put the transistor in its closed switch conductive state. The gate dielectric of the transistor is provided by a silicon oxide layer 32 that surrounds layer 30. Layer 34 will merge with a conductive layer 36 that serves as a bit line 52 of the DRAM and runs over the surface of the trench in the direction normal to the plane of the drawing. Layer 37 corresponds to the storage node 16 (FIG. 1) of the memory cell 10.
 A word line 50 is provided by the segmented n+ type layer, shown as portions 38A, 38B, that also runs over the top surface of the chip 20 orthogonal to a bit line 36, as will appear from the discussion of FIG. 3 below. Layer portions 38A and 38B serve as the gate electrode 12C of transistor 12. The p+ type intermediate region 30 and the gate dielectric layer 32 essentially are stitched in between the two segments 38A and 38B of the word line 50. An oxide layer 40 insulates a bottom surface of the word line 50 from a top surface of the silicon chip 20.
 It is desirable that the intermediate region 30 be of high mobility for the charge carriers, such as electrons in the NMOS-type transistor, because of its potential for higher switching speed. For this reason, it is desirable that the intermediate region comprises essentially monocrystalline. In accordance with one embodiment of the invention, a substantially monocrystalline intermediate region 30 is provided between the polycrystalline fill 23 of the trench 22 that serves as one source/drain 12A (FIG. 1) of the switching transistor and the silicon layer 34 over the region 30 that serves as the other source/drain 12B (FIG. 1) of the switching transistor. As shown, the intermediate region merges with the bit line 36 of the cell.
 In FIG. 3, there is shown a top view of a two dimensional rectangular array of memory cells 11 of FIG. 2. As seen in FIG. 3, the columns of word lines 50 are running vertically, and the rows of bit lines 52 are running horizontally. Insulated crossovers are provided where the two sets of lines would otherwise intersect. The larger tilted squares 54 represent the outline of the vertical trenches 22, and the smaller squares 56 enclosed within the larger tilted square 54 are the outlines of the vertical transistors.
 Referring to FIGS. 4-10, the various steps for forming a memory cell in accordance with one embodiment are shown.
 Typically a plurality of memory ICs are fabricated in parallel on a wafer. After the parallel processing, the wafer is subsequently diced into a number of chips. Each chip typically houses a single IC, each of which contain many thousands of cells and the associated auxiliary circuitry for writing in, reading out, and refreshing. For the sake of simplicity, the discussion of the processing will be limited to that involved with a single memory cell.
 As shown, a trench is formed in a slice of a semiconductor substrate or wafer that serves as the workpiece 60. In one embodiment, the wafer comprises a silicon lightly doped with p-type dopants (p−). As is shown in FIG. 4, one typically begins by forming over the surface of a silicon workpiece (chip) 60, a thin layer 62 of silicon oxide, generally referred to as the PAD oxide. This layer primarily serves to protect the surface of the slice 60 during the processing and is removed in the course of the processing. The PAD oxide 62 is generally covered with a layer 64 of silicon nitride, generally described as the PAD nitride, that primarily serves as an etch stop in some of the subsequent processing steps.
 Next there is formed in the silicon workpiece 60 a trench 66 that will subsequently be filled with polysilicon. The polysilicon is heavily doped with n-typed dopants (n+) and serves as the storage node of the cell. This can be done in the usual fashion that requires providing a properly patterned mask layer 65 over the surface of the slice and using anisotropic reactive ion etching (RIE) to form a trench in the silicon. The mask, for example, comprises TEOS. Other types of hard mask for etching the trench are also useful. Next, if a heavily doped plate region, as represented by n+ type layer 26 in FIG. 2, is to be included, which is optional, it would be formed by, for example, introducing a suitable dopant in the trench and diffusing it out into the substrate. There are a variety of techniques available to this end, as by coating the interior of the trench with an arsenic-rich coating and heating to diffuse the arsenic into the silicon wall of the trench for doping it n+ type. To simplify the drawing, this layer is being omitted in this and subsequent figures.
 After the n+ type plate is formed, the walls of the trench 66 are precleaned prior to the formation a dielectric layer 70. The dielectric layer is formed on the trench walls and over the mask layer 65. The dielectric layer serves as the dielectric of the capacitor. The dielectric layer comprises, for example, silicon oxide, silicon nitride, silicon nitrideoxide, or silicon oxynitride formed by conventional techniques Next, the trench is filled with n+ type doped polycrystalline silicon 72 (polysilicon). To get a good fill, the polysilicon is built up on a top surface of the workpiece 60 until the trench 22 is filled, as is shown in FIG. 4. After this, the top surface is subjected to chemical mechanical polishing (CMP) to planarize the surface of the workpiece 60. In this operation, the dielectric layer 64 serves as an etch stop to achieve planarization, as shown in FIG. 4.
 The dielectric layer 70 on the surface and the hard mask layer (not shown) are then removed, leaving the pad nitride and residual polysilicon. Removal of the dielectric and hard mask layer is achieved by, for example, wet chemical etch such as HF. Other etch processes for removing the layers are also useful. A CMP is employed to planarize the surface, removing the poly to result in a planar top surface.
 Optionally, the top portion of the trench is recessed by RIE. The RIE is selective to the pad nitride and dielectric layers. The result is shown in FIG. 5. Recess 74 improves the quality of the epitaxially grown silicon over the polysilicon trench. In one embodiment, the recess is sufficiently deep so as to enable the trench to be substantially monocrystalline at about the plane of the top surface of the silicon workpiece. As such, the recess improves the quality of the epitaxially grown silicon above the trench.
 Referring to FIG. 6, the pad nitride and oxide layers are stripped away to bare the monocrystalline silicon surface of the workpiece 60 in preparation for the epitaxial growth of silicon over the trench to form the vertical transistor. The removal of the pad layers is achieved by, for example, wet chemical etch. The bare silicon surface imparts seed information for growing silicon thereon.
 A silicon layer 98 is grown epitaxially over the surface of the workpiece 60. In one embodiment, the epitaxial silicon layer is heavily doped with n-type dopants. The n+ silicon layer, for example, is insitu doped during epitaxial growth. Growth of epitaxial silicon is described in, for example, U.S. Ser. Nos. 08/667,541 and 08/605,622 which are herein incorporated by reference for all purposes. The epitaxial layer 98 is grown sufficiently thick and sufficiently crystalline such that recrystallization by heating can make it sufficiently monocrystalline for use as the intermediate layer of the vertical NMOS transistor that is formed thereof, as is shown in FIG.
 The top surface of the workpiece is now masked so that the epitaxial layer 98 can be removed except where it overlies the polysilicon filled trench. After this removal, there remains a mesa 100, as is shown in FIG. 7, located over the polysilicon filled trench 66A.
 Then over the exposed surface of the mesa 100, there is formed an oxide layer 102 that is suitable for use as the gate dielectric of the vertical transistor being formed.
 After this oxide layer 102 is formed over the entire exposed surface of the mesa, it becomes necessary to remove the oxide 102 selectively from the top surface of the mesa 100. Typically this is done by first forming a silicon nitride layer 104 over the surface of the mesa 100, removing it selectively from the top surface of the mesa, while leaving only nitride spacers over the side wall of the mesa, and then etching away selectively the exposed oxide on the top surface of the mesa and the exposed oxide overlying the remainder of the workpiece 60A.
 Next it is desirable, although not necessary, to etch the silicon at the top of the mesa to form a shallow recess 106 at the top of the mesa, as is shown in FIG. 8. There may also be removed silicon at the surface of the workpiece 60A not protected by the mesa. This permits the gate oxide to provide source/drain overlap. This overlap is a factor known to be desirable for high speed switching of the transistor.
 As is shown in FIGS. 9 and 10, essentially there remains only to provide the drain/source region and the word and bit lines. To this end, there is first deposited the first oxide layer 80 that insulates the surface of the workpiece from the word line layer 82 that will subsequently be deposited over it.
 Before deposit of the word line layer, there needs to be removed the nitride spacers 102 on the sides of the mesa 100, so that the polysilicon word line can make physical contact to the gate oxide 102. This is advantageously done by a wet etch that attacks only the nitride spacer. After the nitride spacers have been removed, there are deposited in turn the n+ type conductivity polysilicon layer 82 and the second oxide layer 84 to arrive at the structure shown in FIG. 9.
 After the deposition of these two layers, CMP is used to remove the excess of such layers and to arrive at the structure shown in FIG. 9, leaving exposed the bared epitaxial silicon at the top surface of the mesa.
 Referring to FIG. 10, there is deposited over the exposed surface of the silicon mesa a layer of n+ type conductivity polysilicon 90 to form the drain/source region and a layer of a metallic silicide 92 to form a highly conductive bit line.
 There now results a cell that corresponds in essential details to the cell shown in FIG. 2.
 It is to be understood that the specific embodiments described are merely illustrative of the general principles of the invention and various modifications will be possible without departing from the spirit and scope of the invention. For example, the monocrystalline silicon in which the memory cell is formed may be a layer of silicon that has been grown epitaxially on a suitable crystal of a foreign material, such as sapphire. Still further, the particular conductivity types can be reversed and the conductivity of the various silicon layers varied as is known to workers in the art. Still further, the various processing steps involved, such as etching and depositions, may be varied. Furthermore, while the invention has been described in terms of silicon as the semiconductor, which presently is the preferred choice other types of substrates are also useful. The scope of the invention should therefore be determined not with reference to the above description but with reference to the appended claims along with their full scope of equivalents.
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7238568||May 25, 2005||Jul 3, 2007||Advanced Analogic Technologies, Inc.||Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same|
|US7276411 *||May 25, 2005||Oct 2, 2007||Advanced Analogic Technologies, Inc.||Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same|
|US7282412||May 25, 2005||Oct 16, 2007||Advanced Analogic Technologies, Inc.||Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same|
|US20050215012 *||May 25, 2005||Sep 29, 2005||Advanced Analogic Technologies, Inc.|
|US20050215013 *||May 25, 2005||Sep 29, 2005||Advanced Analogic Technologies, Inc.||Trench semiconductor device having gate oxide layer with mulitiple thicknesses and processes of fabricating the same|
|US20050215027 *||May 25, 2005||Sep 29, 2005||Advanced Analogic Technologies, Inc.|
|U.S. Classification||438/244, 257/E21.652, 438/245|
|International Classification||H01L21/8242, H01L27/108|
|Mar 17, 1998||AS||Assignment|
Owner name: SIEMENS MICROELECTRONICS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GALL, MARTIN;REEL/FRAME:009043/0854
Effective date: 19980305
|Jul 16, 1998||AS||Assignment|
Owner name: SIEMENS AKTIENGESELLSCHAFT, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SIEMENS MICROELECTRONICS, INC.;REEL/FRAME:009324/0302
Effective date: 19980707
|Nov 3, 2005||FPAY||Fee payment|
Year of fee payment: 4
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|May 26, 2010||AS||Assignment|
Owner name: SIEMENS MICROELECTRONICS, INC.,CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SCHELLER, GERD;STENGL, REINHARD J.;SIGNING DATES FROM 19980226 TO 19980302;REEL/FRAME:024474/0849
|Jun 9, 2010||AS||Assignment|
Owner name: INFINEON TECHNOLOGIES AG,GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SIEMENS AKTIENGESELLSCHAFT;REEL/FRAME:024505/0274
Effective date: 19990331
|Jun 14, 2010||AS||Assignment|
Owner name: QIMONDA AG,GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:024626/0001
Effective date: 20060425
|Dec 13, 2013||REMI||Maintenance fee reminder mailed|
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|Jun 24, 2014||FP||Expired due to failure to pay maintenance fee|
Effective date: 20140507