US 20020002573 A1 Abstract A reconfigurable processor includes at least three (3) MacroSequencers (
10)-(16) which are configured in an array. Each of the MacroSequencers is operable to receive on a separate one of four buses (18) an input from the other three MacroSequencers and from itself in a feedback manner. In addition, a control bus (20) is operable to provide control signals to all of the MacroSequencers for the purpose of controlling the instruction sequence associated therewith and also for inputting instructions thereto. Each of the MacroSequencers includes a plurality of executable units having inputs and outputs and each for providing an associated execution algorithm. The outputs of the execution units are input to an output selector which selects the outputs for outputs on at least one external output and on at least one feedback path. An input selector (66) is provided having an input for receiving at least one external output and at least the feedback path. These are selected between for input to select ones of the execution units. An instruction memory (48) contains an instruction word that is operable to control configurations of the datapath through the execution units for a given instruction cycle. This instruction word can be retrieved from the instruction memory (48), the stored instructions therein sequenced through to change the configuration of the datapath for subsequent instruction cycles. Claims(6) 1. A method of floating point mantissa multiplication during two pipeline operations comprising the steps of:
generating partial product signals from a plurality of arithmetic data signals representing mantissas of numbers to be multiplied; adding the partial product signals using a multiple-level adder tree to generate a product signal representing the product of the arithmetic data signals at an output level of the adder tree; accumulating in first pipeline registers intermediate level signals output from one level of the adder tree for input to a subsequent level of the adder tree; wherein a first pipeline operation comprising generating said partial product signals and accumulating said intermediate level signals in said first pipeline registers is carried out in one clock cycle; accumulating in second pipeline registers output signals from a further adder comprising local carry propagate adder cells; selectively feeding back to an input of said further adder signals representing a constant or the contents of at least some of said second pipeline registers; and supplying said product signal as another input to said further adder; wherein said inputs to said further adder are aligned with the precision components of a output signal from said further adder stored by said second pipeline registers; and wherein the signal alignment, storage of said output signal from said further adder in said second pipeline registers, and said selective feedback are effected during a single clock cycle subsequent to said one clock cycle. 2. A method according to claim 29, wherein said arithmetic data signals comprise sets of signals representing modular components of relatively small moduli, and multiplication of two or more of said sets of signals are effected during the same clock cycle. 3. A method according to claim 29, wherein single precision floating point mantissa multiplication of two m-bit arithmetic data signals is effected in the same clock cycle. 4. A method according to claim 29, wherein double precision floating point mantissa multiplication of two m-bit arithmetic data signals is effected in the same clock cycle. 5. A method according to claim 29, wherein the arithmetic data signals represent a p-bit number and a q-bit number, respectively, where p and q are sub-multiples of m, and wherein multiplication of two m-bit mantissas is effected during a sequence of clock cycles. 6. A method according to claim 29, wherein the arithmetic data signals represent two floating point numbers, and wherein the mantissa of one of said numbers may selectively be replaced by a constant or by a further floating point mantissa derived from the second pipeline registers.Description [0001] This application claims priority in Provisional Application Serial No. 60/010317, filed Jan. 22, 1996. [0002] The present invention pertains in general to dual processors and, more particularly, to a digital processor that has a plurality of execution units that are reconfigurable and which utilizes a multiplier-accumulator that is synchronous. [0003] Digital single processors have seen increased use in recent years. This is due to the fact that the processing technology has advanced to an extent that large fast processors can be manufactured. The speed of these processors allows a large number of computations to be made, such that a very complex algorithms can be executed in very short periods of time. One use for these digital single processors is in real-time applications wherein data is received on an input, the algorithm of the transformer function computed and an output generated in what is virtually real-time. [0004] When digital single processors are fabricated, they are typically manufactured to provide a specific computational algorithm and its associated data path. For example, in digital filters, a Finite Impulse Response (FIR) filter is typically utilized and realized with a Digital Single Processor (DSP). Typically, a set of coefficients is stored in a RAM and then a multiplier/accumulator circuit is provided that is operable to process the various coefficients and data in a multi-tap configuration. However, the disadvantage to this type of application is that the DSP is “customized” for each particular application. The reason for this is that a particular algorithm requires a different sequence of computations. For example, in digital filters, there is typically a multiplication followed by an accumulation operation. Other algorithms may require additional multiplications or additional operations and even some shift operations in order to realize the entire function. This therefore requires a different data path configuration. At present, the reconfigurable DSPs have not been a reality and they have not provided the necessary versatility to allow them to be configured to cover a wide range of applications. [0005] The present invention disclosed and claimed herein comprises a reconfigurable processing unit. The reconfigurable unit includes a plurality of execution units, each having at least one input and at least one output. The execution units operate in parallel with each other, with each having a predetermined executable algorithm associated therewith. An output selector is provided for selecting one or more of the at least one outputs of the plurality of execution units, and providing at least one output to an external location and at least one feedback path. An input selector is provided for receiving at least one external input and the feedback path. It is operable to interface to at least one of the at least one inputs of each of the execution units, and is further operable to selectively connect one or both of the at least one external input and the feedback path to select ones of the at least one inputs of the execution units. A reconfiguration register is provided for storing a reconfiguration instruction. This is utilized by a configuration controller for configuring the output selector and the input selector in accordance with the reconfiguration instruction to define a data path configuration through the execution units in a given instruction cycle. [0006] I another embodiment of the present invention, an input device is provided for inputting a new reconfiguration instruction into the reconfiguration register for a subsequent instruction cycle. The configuration controller is operable to reconfigure the data path of data through the configured execution units for the subsequent instruction cycle. An instruction memory is provided for storing a plurality of reconfiguration instructions, and a sequencer is provided for outputting the stored reconfiguration instructions to the reconfiguration register in subsequent instruction cycles in accordance with a predetermined execution sequence. [0007] In yet another aspect of the present invention, at least one of the execution units has multiple configurable data paths therethrough with the execution algorithm of the one execution unit being reconfigurable in accordance with the contents of the instruction register to select between one of said multiple data paths therein. This allows the operation of each of said execution units to be programmable in accordance with the contents of the reconfiguration register such that the configuration controller will configure both the data path through and the executable algorithm associated with the one execution unit. [0008] For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying Drawings in which: [0009]FIG. 1 illustrates a data flow diagram of a reconfigurable arithmetic data path processor in accordance with present invention; [0010]FIG. 2 illustrates a top level block diagram of the MacroSequencer; [0011]FIG. 3 illustrates a more detailed block diagram of the MacroSequencer; [0012]FIG. 4 illustrates a logic diagram of the input register; [0013]FIG. 5 illustrates a logic diagram of the input selector; [0014]FIG. 6 illustrates a block diagram of the multiplier-accumulator; [0015]FIG. 7 illustrates a logic diagram of the adder; [0016]FIG. 8 illustrates a block diagram of the shifter; [0017]FIG. 9 illustrates a block diagram of the logic unit; [0018]FIG. 10 illustrates a block diagram of the one port memory; [0019]FIG. 11 illustrates a block diagram of the three port memory; [0020]FIG. 12 illustrates a diagram of the 3-port index pointers; [0021]FIG. 13 illustrates a logic diagram of the output selector; [0022]FIG. 14 illustrates a logic diagram of the I/O interface; [0023]FIG. 15 illustrates a block diagram of the MacroSequencer data path controller; [0024]FIG. 16 illustrates a block diagram of the dual PLA; [0025]FIG. 17 illustrates a block diagram of basic multiplier; [0026]FIG. 18 illustrates an alternate embodiment of the MAC; [0027]FIG. 19 illustrates an embodiment of the MAC which is optimized for polynomial calculations; [0028]FIG. 20 has an additional four numbers generated in the multiplier block; [0029]FIG. 21 illustrates a basic multiplier-accumulator; [0030]FIG. 22 illustrates an extended circuit which supports optimal polynomial calculation steps; [0031]FIG. 23 illustrates a block diagram of a multiplier block with minimal support circuitry; [0032]FIG. 24 is illustrates a block diagram of a multiplier-accumulator with Basic Core of Adder, one-port and three-port Memories; and [0033]FIG. 25 illustrates a block diagram of a Multiplier-Accumulator with Multiplicity of Adders, and one-port and three-port Memories. [0034] Referring now to FIG. 1, there is illustrated a block diagram of the Reconfigurable Arithmetic Datapath Processor (RADP) of the present invention. The RADP is comprised of four (4) MacroSequencers, [0035] Each of the MacroSequencers [0036] Each MacroSequencer is designed with a Long Instruction Word (LIW) architecture enabling multiple operations per clock cycle. Independent operation fields in the LIW control the MacroSequencer's data memories, 16-bit adder, multiplier-accumulator, logic unit, shifter, and I/O registers so they may be used simultaneously with branch control. The pipe-lined architecture allows up to seven operations of the execution units during each cycle. [0037] The LIW architecture optimizes performance allowing algorithms to be implemented with a small number of long instruction words. Each Macro-Sequencer may be configured to operate independently, or can be paired for some 32-bit arithmetic operations. [0038] The Dual PLA [0039] The MacroSequencers may be used individually for 16-bit operations or in pairs for standard 32-bit addition, subtraction, and logic operations. When pairing, the MacroSequencers are not interchangeable. MacroSequencers [0040] The five global data buses consisting of data buses [0041] The Control Bus [0042] Initiate one of two available LIW sequences, [0043] Continue execution of the LIW sequence, or [0044] Acknowledge the MacroSequencer status flags by resetting the send and await state bits. [0045] Two status signals, Await and Send, are sent from the MacroSequencer which are described in more detail with respect to the MacroSequencer Datapath Controller hereinbelow and indicate: [0046] the Program Counter is sequencing; [0047] the MacroSequencer is in the send state it has executed a specific LiW; [0048] the Program Counter is continuing to sequence; [0049] the MacroSequencer is in the await state and it has executed a specific LIW; and [0050] the Program Counter is not continuing to sequence, and it is awaiting further commands before resuming. [0051] Two output enable signals for each MacroSequencer are described with reference to an Output Selection operation described hereinbelow and allow for output enable to be: [0052] from the Dual PLA [0053] always output; [0054] Always input (the power up condition); or [0055] Optionally inverted. [0056] Five input clocks are provided to allow the RADP to process multiple data streams at different transmission speeds. There is one clock for each Macro-Sequencer, and a separate clock for the PLA [0057] Referring now to FIG. 2, there is illustrated a overall block diagram of each of MacroSequencers [0058] The control signals may initiate one of two programmed LIW sequences in instruction memory [0059] Referring now to FIG. 3 is illustrated a block diagram of the MacroSequencer datapath for MacroSequencers [0060] There are nine (9) basic elements in the MacroSequencer Arithmetic Datapath. Six (6) of these are data processing elements and six (6) are data steering functions, of which the input selector [0061] The input register block [0062] Each of the four (4) parallel data processing units, the MAC [0063] The 16-bit input registers in register block [0064] The Constant introduces 16-bit constants into any calculation. The constant of the MacroSequencer shares internal signals with the MacroSequencer Controller as well as the MAC [0065] Referring now to FIG. 5, there is illustrated a block diagram of the input selector block [0066] InRegA and InRegB from the Input Register [0067] OutRegA and OutRegB from the Output Register [0068] mem [0069] mem [0070] Constant ‘0’ which is generated in the Input Selector [0071] Control signals from the MacroSequencer Controller (not shown) determine which three of the eight possible inputs are used and whether InBusB is inverted or not. The Input Selector [0072] Referring now to FIG. 6, there is illustrated a block diagram of the MAC [0073] The input to the MAC [0074] 1) They align the high or low bytes from Operand B for the multiplier which allows 16 by 8 or 16 by 16 multiply operations; and [0075] 2) They allow each operand to be selected from three different sources: [0076] Operand A is selected from the One-Port Memory [0077] Operand B is selected from the high byte of OutRegB [0078] The Multiplier Stage [0079] The number of cycles required for Multiplies and MACs are shown in Tables 1 and 2.
[0080]
[0081] The MAC internal format is converted to standard integer format by the Adder [0082] If a 16- by 8-bit MAC [0083] Referring now to FIG. 7, there is illustrated a block diagram of the Adder [0084] The input multiplexers [0085] The Adders [0086] Adder Status Bits—The Equal, Sign, Overflow, and Carry flags are set two cycles after an addition operation (add [0087] The Equal flag is set two cycles later when the two operands are equal during an addition operation; [0088] The Overflow flag is set when the result of an addition or subtraction results in a 16-bit out-of-range value; [0089] When the adder [0090] When the adder is configured for signed integer arithmetic, Overflow=Carry XOR Sign. Range=−32768 to +32767; [0091] The Sign flag is set when the result of an addition or subtraction is a negative value; [0092] The Carry flag indicates whether a carry value exists. [0093] The Adder [0094] Shift Mode signals control which Shifter functions are performed: [0095] Logical Shift Left by n bits (shift low order bits to high order bits). The data shifted out of the Shifter is lost, and a logical ‘0’ is used to fill the bits shifted in. [0096] Logical Shift Right by n bits (shift high order bits to low order bits). The data shifted out of the Shifter is lost, and a logical ‘0’ is used to fill the bits shifted in. [0097] Arithmetic Shift Right by n bits. This is the same as logical shift right with the exception that the bits shifted in are filled with Bit[ [0098] This is equivalent to dividing the number by 2 [0099] Rotate Shift Left by n bits. The bits shifted out from the highest ordered bit are shifted into the lowest ordered bit. [0100] Normalized Shift Right by 1 bit. All bits are shifted one lower in order. The lowest bit is lost and the highest bit is replaced by the Overflow Register bit of the Adder. This is used to scale the number when two 16-bit words are added to produce a 17-bit result. [0101] Logical, Arithmetic and Rotate shifts may shift zero to fifteen bits as determined by the Shift Length control signal. [0102] Referring now to FIG. 9, there is illustrated a block diagram of the Logic Unit [0103] Referring now to FIG. 10, there is illustrated a block diagram of the One-Port Memory [0104] Referring now to FIG. 11, there is illustrated a block diagram of a Three-Port Memory [0105] Referring now to FIG. 12, there is illustrated a block diagram of the Three-Port Memory Index Pointers. Smart Indexing operates multiple memory addresses to be accessed. This is particularly useful when the data is symmetrical. Symmetrical coefficients are accessed by providing the Write Offset from the center of the data and aligning both Read Indices to the Write Offset. The Read Indices may be separated by a dummy read. Additional simultaneous reads with one index incrementing and the other decrementing allows for addition or subtraction of data that uses the same or inverted coefficients. Each index has separate controls to control its direction. Each index may increment or decrement, and/or change its direction. The change in each index register's address takes place after a read or write operation on the associated port. Smart Indexing is ideal for Filter, and DCT applications where pieces of data are taken from equal distance away from the center of symmetrical data. The Smart Indexing method used in the Data Memory allows symmetrical data to be multiplied in half the number of cycles that would have normally been required. Data from both sides can be added together and then multiplied with the common coefficient. For example, a 6-tap filter which would normally take 6 multiplies and 7 cycles, can be implemented with a single MacroSequencer and only requires 3 cycles to complete the calculation. An 8-point DCT which normally requires 64 multiplies and 65 cycles can be implemented with a single Macro-Sequencer and only requires 32 clock cycles to complete the calculation. [0106] Referring now to FIG. 13, there is illustrated a block diagram of the output selector [0107] Referring now to FIG. 14, there is illustrated a block diagram of the MacroSequencer I/O interface. The contents of the output register [0108] The input data on the buses [0109] Output Enable to the MSnI/O pins is controlled by configuration bit selections. Inputs to the output enable control circuitry include the MSnOE pin for MacroSequencer(n) and the oepla[n] signal from the PLA [0110] Referring now to FIG. 15, there is illustrated a block diagram of the MacroSequencer Datapath Controller [0111] The Datapath Controller [0112] The LIW register [0113] The controller [0114] The Datapath Controller [0115] The Adder status signals, Stack [0116] the Adder status bits report the value of the Equal, Overflow, and Sign, for use in branch operations; [0117] the Stack [0118] counter [0119] The five index registers [0120] The MSn Direct Control and Status pins illustrated in FIG. 2 are the control and status interface signals which connect directly between the pins and each MacroSequencer. The direct control signals are MSnCTRL[ [0121] The four control commands include: [0122] SetSequence [0123] SetSequence [0124] SetSequence [0125] SetSequence [0126] Run [0127] Run permits normal operation of the Datapath Controller [0128] Continue [0129] Continue resets both the Send and Await status signals and permits normal operation. If the Await State was asserted, the Program Counter [0130] If an await operation is encountered while the Continue control command is in effect, the Continue control command will apply, and the await operation will not halt the program counter [0131] The following table summarizes the four control command options for Controln[
[0132] By allowing two sequence starting points, each MacroSequencer can be programmed to perform two algorithms without reloading the sequences. The two PLA Controln signals are synchronized within the MacroSequencer. The two MSnCTRL pin signals are not synchronized within the Macro-Sequencer; therefore, consideration for timing requirements is necessary. [0133] There are two single-bit registered status signals that notify the external pins and the PLA [0134] SetSequence [0135] When an await operation is asserted from the LIW register, the MacroSequencer executes the next instruction, and repeats execution of that next instruction until a Continue or SetSequence control command is received. The await operation stops the program counter from continuing to change and sets the Await status signal and register to ‘1’. A Continue control command resets the Await status signal and register to ‘0’ allowing the program counter [0136] The Adder status bits, Equal, Overflow, and Sign are provided for conditional jumps. [0137] The purpose of the 48-bit LIW Register [0138] One-Port Memory access [0139] Three-Port Memory access [0140] Input Register multiplexers [0141] Input Mux A, B, C [0142] Output multiplexers [0143] Adder [0144] Adder [0145] These operational fields are available on every cycle except when a Constant is required by an in operation: [0146] Multiplier [0147] Multiplier-Accumulator [0148] These operational fields conflict with each other. Only one is allowed in each LIW: [0149] Shifter [0150] Logic Unit [0151] Datapath Controller (if parameters are required) [0152] The Program Counter [0153] Branch Operations, [0154] SetSequence [0155] Await status operations. [0156] The Program Counter [0157] During power-on Reset, [0158] During Active configuration of any part of the RADP, [0159] During the SetSequence [0160] When the Program Counter [0161] Upon the execution of a branch operation to address ‘0’. [0162] The Controln[ [0163] The Await status register is set to ‘1’ and the Program Counter [0164] The LIW register may contain one Branch Operation at a time. Conditional Branches should not be performed during the SetSequence control commands to insure predictable conditions.
[0165] The Instruction memory 0 and Counter1 [0166] The counters [0167] The Stack [0168] The LIW Register [0169] In each MacroSequencer there are nine programmable configuration bits. They are listed in the table below. The three signed/unsigned related bits are set with directives when programming the MacroSequencer. The others are set by the software design tools when the configuration options are selected.
[0170] The configuration bits are configured with the instruction memory [0171] Referring now to FIG. 16, there is illustrated a block diagram of the dual PLA [0172] The Dual PLA [0173] Registered control outputs, CtrlReg[ [0174] Initiation of LIW sequences; and [0175] Control response to Send and Await status signals. [0176] Combinatorial outputs, oepla[ [0177] The PLA [0178] The RADP is configured by loading the configuration file into the device. [0179] There are three memories in each of the four MacroSequencers and a Dual PLA configuration memory. Within each of the MacroSequencers, there is an: [0180] LIW memory with the nine configuration bits, [0181] One-Port data memory, and [0182] Three-Port data memory. [0183] The nine programmable configuration bits within each MacroSequencer are configured as additional configuration data words in the LIW configuration data packet. The LIW memory, configuration bits, and Dual PLA memory may only be loaded during Active Configuration Mode. The One-Port and Three-Port data memories for each MacroSequencer may be loaded during Active Configuration and accessed during normal operating mode as directed by each MacroSequencer's LIW Register. [0184] The configuration is to be loaded into the RADP during Active Configuration Mode. The RADP may be in one of three operating modes depending on the logic states of PGM [0185] In the Normal Operation mode, the RADP MacroSequencers concurrently execute the LIWs programmed into each LIW memory. [0186] The RADP is configured during the Active Configuration mode which allows each MacroSequencer's instruction memory and Data Memories and the Dual PLA to be programmed. [0187] Passive Configuration mode disables the device I/O pins from operating normally or being configured which allows other RADPs in the same circuit to be configured. [0188] Four configuration pins, named PGM [0189] The Multiplier-Accumulator (MAC) [0190] The first pipe stage is composed of a network of a multiplicity small bit multipliers, a multiplicity of local carry propagate adders forming a multiplicity of trees and a pipeline register circuit for holding the results of the roots of each adder tree. The leaves of these adder trees are from the multiple digit output of the small bit multiplier circuits. The second pipe stage is composed of a multiplicity of local carry propagate adders of which all but one of which comprise a tree taking the synchronized results of the multiplicity of adder trees of the first pipe stage and forming a single sum of all adder tree results from the first pipe stage. An interface circuit operates on this resulting sum and on a possibly selected component of the accumulator register(s) contents of this pipe stage. The interface circuit either: may zero the feedback from the accumulator register(s) [0191] For the purpose of describing the MAC [0192] Wire [0193] A wire is a means of connecting a plurality of communicating devices to each other through interface circuits which will be identified as transmitting, receiving or bi-directional interfaces. A bi-directional interface will consist of a transmitter and receiver interface. Each transmitter may be implemented so that it may be disabled from transmitting. This allows more than one transmitter may be interfaced to a wire. Each receiver may be implemented so that it may be disabled from receiving the state of the wire it is interfaced to. A wire will be assumed to distribute a signal from one or more transmitters to the receivers interfaced to that wire in some minimal unit of time. This signal can be called the state of the wire. A signal is a member of a finite set of symbols which form an alphabet. Often this alphabet consists of a 2 element set, although use of multi-level alphabets with more than 2 symbols have practical applications. The most common wire is a thin strip of metal whose states are two disjoint ranges of voltages, often denoted as ‘0’ and ‘1’. This alphabet has proven extremely useful throughout the development of digital systems from telegraphy to modern digital computers. Other metal strip systems involving more voltages ranges, currents and frequency modulation have also been employed. The key similarity is the finite, well defined alphabet of wire states. An example of this is multiple valued current-mode encoded wires in VLSI circuits such as described in “High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits” by Kawhito, et. al. Wires have also been built from optical transmission lines and fluidic transmission systems. The exact embodiment of the wires of a specific implementation can be composed of any of these mechanisms, but is not limited to the above. Note that in some high speed applications, the state of a wire in its minimal unit of time may be a function of location within the wire. This phenomena is commonly observed in fluidic, microwave and optical networks due to propagation delay effects. This may be a purposeful component of certain designs and is encompassed by this approach. [0194] Signal Bundle and Signal Bus [0195] A signal bundle and a signal bus are both composed of a plurality of wires. Each wire of a signal bundle is connected to a plurality of communicating devices through interface circuitry which is either a transmitter or a receiver. The direction of communication within a signal bundle is constant with time, the communication devices which are transmitting are always transmitting. Those which are receiving are always receiving. Similarly, each wire of a signal bus is also connected to a plurality of communicating devices. The communicating devices interfaced to a signal bus are uniformly attached to each wire so that whichever device is transmitting transmits on all wires and whichever device(s) are receiving are receiving on all wires. Further, each communicating device may have both transmitters and receivers, which may be active at different time intervals. This allows the flow of information to change in direction through an succession of intervals of time, i.e., the source and destinations(s) for signals may change over a succession of time intervals. [0196] Pipeline Register and Stage [0197] The circuitry being claimed herein is based upon a sequential control structure known as a pipeline stage. A pipeline stage will be defined to consist of a pipeline register and possibly a combinatorial logic stage. The normal operational state of the pipeline stage will be the contents of the memory components within the pipeline register. Additional state information may also be available to meet testability requirements or additional systems requirements outside the intent of this patent. Typical implementations of pipeline stage circuits are found in synchronous Digital Logic Systems. Such systems use a small number of control signals known as clocks to synchronize the state transition events within various pipeline stages. One, two and four phase clocking schemes have been widely used in such approaches. See the references listed in the section entitled Typical Clocking Schemes for a discussion of these approaches applied to VLSI Design. These typical approaches face severe limitations when clocks must traverse large distances and/or large varying capacitive loads across different paths within the network to be controlled. These limitations are common in sub-micro CMOS VLSI fabrication technologies. The use of more resilient timing schemes has been discussed in the Alternative Clocking Scheme references. It will be assumed that a pipeline stage will contain a pipeline register component governed by control signals of either a traditional synchronous or a scheme such as those mentioned in the Alternative Clocking Scheme References. [0198] K-ary Trees, K-ary and Uniform Trees with Feedback [0199] For the purposes of this document, a directed graph G(V,E) is a pair of objects consisting of a finite, non-empty set of vertices V={v[ [0200] p-adic Number Systems [0201] A p-adic number system is based upon a given prime number p. A p-adic representation of an unsigned integer k is a polynomial—k=a [0202] Two's Complement Number System [0203] Two's complement Numbers is a signed [0204] Redundant Number Systems and Local Carry Propagation Adders [0205] A redundant number system is a number system which has multiple distinct representations for the same number. A common redundant number system employs an entity consisting of two components. Each component possesses the same bit length. The number represented by such an entity is a function (often the difference) between the two components. A local carry propagation adder will be defined as any embodiment of an addition and/or subtraction function which performs its operation within a constant time for any operand length implementation. This is typically done by propagating the carry signals for any digit position only to a small fixed number of digits of higher precision. This phenomena is called local carry propagation. A primary application of redundant number systems is to provide a notation for a local carry propagation form of addition and subtraction. Such number systems are widely used in the design of computer circuitry to perform multiplication. In the discussion that follows, Redundant Binary Adder Cells are typically used to build implementations such as those which follow. The local carry propagate adder circuits discussed herein may also be built with Carry-Save Adder schemes. There are other local or limited carry propagation adder circuits which might be used to implement the following circuitry. However, for the sake of brevity and clarity, only redundant adder schemes will be used in the descriptions that follow. Many of the references hereinbelow with respect to the High Speed Arithmetic Circuitry discuss or use redundant number systems. [0206] Modular Decomposition Number Systems [0207] Modular Decomposition Number Systems are based upon the Chinese Remainder Theorem. This theorem was first discovered and documented for integers twenty centuries ago in China. The Chinese Remainder Theorem states that: Let m[ [0208] Standard Floating Point Notations [0209] Standard Floating Point Notation is specified in a document published by ANSI. Floating point arithmetic operations usually require one of four rounding mode to be invoked to complete the generation of the result. The rounding modes are used whenever the exact result of the operation requires more precision in the mantissa than the format permits. The purpose of rounding modes is to provide an algorithmic way to limit the result to a value which can be supported by the format in use. The default mode used by compiled programs written in C, PASCAL, BASIC, FORTRAN and most other computer languages is round to nearest. Calculation of many range limited algorithms, in particular the standard transcendental functions available in FORTRAN, C, PASCAL and BASIC require all of the other three modes: Round to positive infinity, Round to negative infinity and round to zero. Round to nearest looks at the bits of the result starting from the least significant bit supported and continuing to the least significant bit in the result. The other three rounding modes are round to 0, round to negative infinity and round to positive infinity, which are well documented in IEEE-ANSI specification for standard floating point arithmetic. [0210] Extended Precision Floating Point Notations [0211] Extended Precision Floating Point Notations are a proposed notational and semantic extension of Standard Floating Point to solve some of its inherent limitations. Extended Precision Floating Point requires the use of accumulator mantissa fields twice as long as the mantissa format itself. This provides for much more accurate multiply-accumulate operation sequences. It also minimally requires two accumulators be available, one for the lower bound and one for the upper bound for each operation. The use of interval arithmetic with double length accumulation leads to significantly more reliable and verifiable scientific arithmetic processing. Long Precision Floating Point Notations involve the use of longer formats. For example, this could take the form of a mantissa which is 240 bits (including sign) and an exponent of 16 bits. Extended Long Precision Floating Point Notations would again possess accumulators supporting mantissas of twice the length of the operands. These extensions to standard floating point have great utility in calculations where great precision is required, such as interplanetary orbital calculations, solving non-linear differential equations, performing multiplicative inverse calculations upon nearly singular matrices. [0212] p-adic Floating Point Systems [0213] P-adic arithmetic can be used as the mantissa component of a floating point number. Current floating point implementations use p=2. When p>2, rounding to nearest neighbor has the effect of converging to the correct answer, rather than often diverging from it in the course of executing a sequence of operations. The major limitation of this scheme is that a smaller subset of the real numbers than can be represented compared with the base [0214] The mantissa field size must be a multiple of the number of bits it takes to store p. [0215] The mantissa field size must be at least as big as the standard floating point notation. [0216] The exponent field will be treated as a signed [0217] The mantissa sign bit is an explicit bit in the format. [0218] The following Table 6 summarizes results based upon these assumptions for Word Length
[0219] The following table summarizes results based upon these assumptions for Word Length
[0220] One may conclude from the above two tables that p-adic floating point formats based upon p=7 and p=31 offer advantages in dynamic range with at least as good mantissa accuracy for both single and double precision(32 and 64 bit) formats. It seems reasonable that p=7 has distinct advantages over p=31 in terms of inherent implementation complexity. The mantissa component of a floating point number system can also be composed of two components, known here as MSC and LSC, for Most Significant Component and Least Significant Component, respectively. The MSC can be constructed as a binary or 2-adic system and the LSC can be constructed from a p-adic system where p>2. Such an arrangement would also converge to the correct answer in round to nearest neighbor mode and would have the advantage of making full use of the bits comprising the MSC. If the LSC occupies the “guard bits” of the floating point arithmetic circuitry, then the visible effect upon the subset of floating point numbers which can be represented is the consistent convergence of resulting operations. This would aid standard Floating Point notation implementation. If p is near a power of two, then p-adic number based mantissa calculations would be efficiently stored in memory . Particularly for p=3 and 7, the modular arithmetic multiplier architecture could amount to specializing the redundant binary adder chain in each adder strip and slightly changing the Booth encoding algorithms discussed in the following implementation discussions. If the MSC represented all but 2, 3 or 5 bits of the mantissa, then p=3, 7 or 31 versions of p-adic arithmetic could respectively be used with minimal impact on how many numbers could be represented by such notations. Note that for this kind of application, p need not be restricted to being prime. As long as p was odd, the desired rounding convergence would result. It will be general assumed throughout this document that p=3, 7, 15 and 31 are the most optimal choices for p-adic floating point extensions, which are “mostly” prime. Both the number systems discussed in the previous paragraphs will be designated as p-adic floating point systems with the second version involving the MSC and LSC components being designated the mixed p-adic floating point system when relevant in what follows. Both of these notations can be applied to Extended Precision Floating Point Arithmetic. [0221] The basic operation of a multiplier [0222] This description starts with a basic block diagram of a multiplier-accumulator and one basic extension of that multiplier/accumulator which provides significant cost and performance advantages over other approaches achieving similar results. These circuit blocks will be shown advantageous in both standard fixed and floating point applications, as well as long precision floating point, extended precision floating point, standard p-adic fixed and floating point and modular decomposition multiplier applications. [0223] Optimal performance of any of these multiplier-accumulator circuits in a broad class of applications requires that the multiplier-accumulator circuit receive a continuous stream of data operands. The next layer of the claimed devices entail a multiplier-accumulator circuit plus at least one adder and a local data storage system composed of two or more memories combined in a network. The minimum circuitry for these memories consists of two memories, the one-port memory [0224] Extension to support various floating point schemes requires the ability align one mantissa resulting from an arithmetic operation with a second mantissa. This alignment operation is best performed by a specialized circuit capable of efficient shifting, Shifter [0225] Support for p-adic arithmetic systems requires that the multiplier-accumulator implementation support p-adic arithmetic. Similar requirements must be made of at least one adder in an implementation. The p-adic mantissa alignment circuitry also makes similar requirements upon the shifter. Modular arithmetic applications are typically very long integer systems. The primary requirement becomes being able to perform high speed modular arithmetic where the modular decomposition may change during the execution of an algorithm. The focus of such requirements is upon the multiplier-accumulator and adder circuitry. 142 and Its Components [0226] Referring now to FIG. 17, there is illustrated a block diagram of basic multiplier. A very fast way to sum 2 [0227] The circuitry in the stage-one pipeline registers E [0228] Transform circuitry J [0229] An example of the above can be seen in implementing a redundant binary notation as follows:
[0230] This notation turns out to be optimal for certain CMOS logic implementations of an 8 by 16-bit multiplier based upon FIG. 17. Conversion by a standard two's complement adder required conversion from the Non-standard Signed Magnitude notation to a Standard Notation. This was done by implementing the logic transformation: [0231] St[ [0232] St[ [0233] Optimal implementations of redundant p-adic notations to carry propagate p-adic notation conversion may also require this. [0234] With the above noted structure, the following operations can be realized: [0235] Signed and Unsigned 8 by 16 bit multiplication and multiply-accumulate Signed and Unsigned 16 by 16 bit multiplication and multiply-accumulate [0236] Signed and Unsigned 24 by 16 multiplication and multiply-accumulate [0237] Signed and Unsigned 24 by 24 bit multiplication and multiply-accumulate [0238] Signed and Unsigned 24 by 32 bit multiplication and multiply-accumulate [0239] Signed and Unsigned 32 by 32 bit multiplication and multiply-accumulate [0240] Optimal polynomial calculation step [0241] Fixed point versions of the above: [0242] Standard Floating Point Single Precision Mantissa Multiplication [0243] Extended Precision Floating Point Single Precision Mantissa Multiplication [0244] P-Adic Floating Point Single Precision Mantissa Multiplication [0245] P-Adic Fixed Point Multiplication and Multiplication/accumulation. [0246] These operations can be used in various applications, some of which are as follows: [0247] 1. 8 by 16 multiplication/accumulation is used to convert between 24 bit RGB to YUV color encoding. YUV is the standard broadcast NTSC color coding format. The standard consumer version of this requires 8 bit digital components to the RGB and/or YUV implementation. [0248] 2. 16 bit arithmetic is a very common form of arithmetic used embedded control computers. [0249] 3. 16 by 24 bit multiplication/accumulation with greater than 48 bits accumulation is capable of performing 1024 point complex FFTs on audio data streams for Compact Disk Applications, such as data compression algorithms. The reason for this is that the FFT coefficients include numbers on the order PI/512, which has an approximate magnitude of {fraction (1/256)}. Thus a fixed point implementation requires accumulation of 16 by 24 bit multiplications to preserve the accuracy of the input data. [0250] 4. 24 by 24 bit multiplication/accumulation is also commonly used in audio signal processing requirements. Note that by a similar argument to the last paragraph, 24 by 32 bit multiplications are necessary to preserve the accuracy of the data for a 1024 point complex FFT. [0251] 5. 32 bit arithmetic is considered by many to be the next most common used form of integer arithmetic after 16 bit. It should be noted that this arithmetic is required for implementations of the long integer type by C and C++ computer language execution environments. [0252] 6. Polynomial calculation step operations, particularly fixed point versions, are commonly used for low degree polynomial interpolation. These operations are a common mechanism for implementing standard transcendental functions, such as sin, cos, tan, log, etc. [0253] 7. Standard Floating Point Arithmetic is the most widely used dynamic range arithmetic at this time. [0254] 8. Extended Precision Floating Point arithmetic is applicable wherever Standard Floating Point is currently employed and resolves some serious problems with rounding errors or slow convergence results. Tne major drawback to this approach is that it will run more slowly the comparable Standard Floating Point Arithmetic. It is important to note that with this approach, there is no performance penalty and very limited additional circuit complexity involved in supporting this significant increase in quality. [0255] 9. P-Adic Floating Point and Fixed Point arithmetic are applicable where Standard Floating point or fixed point arithmetic are used, respectively. The advantage of these arithmetics is that they will tend to converge to the correct answer rather than randomly diverging in round to nearest mode and can take about the same amount of time and circuitry as standard arithmetic when implemented in this approach. It should be noted that in the same number of bits as Standard Floating Point, implementations of p=7 p-adic floating point have greater dynamic range and at least the same mantissa precision, making these numeric formats better than standard floating point. [0256] Referring further to FIG. 17, the operation of the various components will be described in more detail. The multipliers in a small bit multiplier block [0257] The signal bundles C [0258] Referring now to FIG. 18, there is illustrated an alternate embodiment of the MAC [0259] Referring now to FIG. 19, there is illustrated an embodiment of the MAC [0260] Note that in the circuits represented by FIGS. 18 and 19, the presence of at least two accumulators is highly desirable, such that two polynomial calculations can then be performed in approximately the same time as one is performed. This is due to the 2 pipe stage latency in the multiplier. [0261] Adders D [0262] Adders D [0263] The circuitry in E [0264] Adders D [0265] G [0266] In FIGS. 17 and 18, Adder D [0267] H [0268] If H [0269] Embodiments of this architecture support high-speed multiple-precision operations, which is not possible in typical integer or fixed-point arithmetic circuits. The performance of multiple- precision operations lowers throughput, but preserves the exactness of result. These are not possible at anything approaching the throughput and size of circuitry based upon this block diagram. Embodiments of this architecture can support standard single-precision floating point mantissa multiplications with significantly less logic circuitry than previous approaches. Embodiments of this architecture appear to be the only known circuits to support small p-adic mantissa multiplications. The authors believe that this is the first disclosure of such a floating point representation. Embodiments of this architecture provide a primary mechanism for implementing Extended precision Floating Point Arithmetic in a minimum of logic circuitry. Embodiments of this architecture also provide implementations of efficient high speed modular arithmetic calculators. 17 [0270] In this discussion, A [0271] Multipliers [0272] The following Table
1 to D7 [0273] Adders D [0274] Table
[0275] Table 11 illustrates Capability Versus Size Comparison with N=24 based upon FIG.
[0276] The Modified 3-2 bit Booth Multiplication Coding Scheme in multiplier block [0277] The primary distinction between the 8 by N implementation and this implementation is in the multiplier block [0278] The following algorithm is based upon examining 3 successive bits, determining whether to perform an add or subtract, then processing over 2 bit positions and repeating the process. This is known as the 3-2 bit coding scheme. There is a one bit overlap, the least significant bit of one examination is the most significant bit of its predecessor examination. [0279] Table 12 of 3-2 bit Booth Multiplication Coding Scheme:
[0280] Table 13 of C
[0281] Implementation Parameters to achieve various requirements are summarized in the following table 14 that illustrates performance evaluation with (3,2) Booth Encoder Small Bit Multipliers Cells is shown in the following table of Capability versus size comparison (N=16) based upon FIG. 1. The typical adder cell count in this table is based upon using a 3-2 bit Modified Booth Coding scheme similar in Table 12.
[0282] The following table 15 illustrates a Capability versus size comparison (N=24) based upon FIG. 17. The typical adder cell count in this table is based upon using a 3-2 bit Modified Booth Coding scheme similar in Table 12.
[0283] Use of a Modified 4-3 bit Booth Multiplication Coding Scheme [0284] This embodiment primarily differs from its predecessors in the multiplier block [0285] Table 16 illustrates a Modified 4-3 Bit Booth Multiplication Coding Scheme:
[0286] Optimal Double Precision Floating Point Mantissa Multiplication [0287] An implementation based upon 24- by 32-bit multiplication would be capable of performing a standard 56-bit precision floating point mantissa multiplication every two cycles. The 56-bit length comes from the inherent requirement of IEEE Standard Double Precision numbers, which require a mantissa of 64-10 bits, plus two guard bits for intermediate rounding accuracy. Such an implementation would require only two alignment slots. An implementation of 16- by 24-bit multiplication would be capable of supporting the 56-bit floating point mantissa calculation, but with the liability of taking more clock cycles to complete. More alignment slots would be required. Such an implementation would however much less logic circuitry as the application dedicated multiplier. Implementation of a p-adic mantissa for either p=3 or 7 would be readily optimized in such implementations. [0288] Table 17 of C
[0289] The following table 18 illustrates the performance evaluation of Capability versus size comparison (N=24) based upon FIG. 17. The typical adder cell counts in the above table are based upon a multiplier design using a 4-3 bit Modified Booth Encoding Algorithm.
18 300 Circuitry [0290] Table 19 illustrates coefficient generation for multipliers
[0291] Examination of Table 19 shows that Adder D [0292] Fixed point arithmetic polynomial step calculations would not need Adder D [0293] Table 20 illustrates Performance versus Size for N=16.
[0294] The basic difference in the MAC of FIG. 20 and the above MAC of FIG. 19 is that there are an additional four numbers generated in multiplier block [0295] An implementation of 28 by N bit multiplication would be sufficient with the use of D [0296] Implementations of either of the last two implementations which contained four accumulation registers in H [0297] As in the initial Multiplier/Accumulator architecture of FIG. 17, the inputs of Adder D [0298] Adder D [0299] Table 21 illustrates a Trimmed adder tree supporting 32 by 32 Multiplication (Performance versus Size for N=32).
[0300] Referring now to FIGS. 21 and 22, there are illustrated two additional embodiments of the MAC [0301] Use of 4-3 Modified Booth Multiplication Encoding will be assumed for multiplier block [0302] Starting from the left, the first layer of adders (D [0303] With further reference to FIG. 21, the major item to note is that there are an additional six numbers generated in multiplier block [0304] The adder chains D [0305] Register Block H [0306] The following Table 22 describes the performance analysis of Multipliers with two accumulators capable of supporting Extended Scientific Double Precision Standard and p=7 p-adic multiplication-accumulation on every cycle.
[0307] Referring now to FIG. 23, there is illustrated a block diagram of a Multiplier Block with minimal support Circuitry. A Multiplier-Accumulator Block [0308] The K [0309] Referring now to FIG. 24, there is illustrated a block diagram of a Multiplier-Accumulator with Basic Core of Adder, one-port and three-port Memories. This circuit incorporates all the functional blocks of FIG. 23 [0310] The one-port memory block [0311] The three-port memory block [0312] Referring now to FIG. 25, there is illustrated a block diagram of a Multiplier-Accumulator with Multiplicity of Adders, and one-port and three-port Memories. This circuit incorporates all the functional blocks of FIG. 24 plus one or more additional Adder blocks, each containing a multiplicity of Accumulators [0313] The basic Advantages of Circuit represented by FIGS. [0314] Convolutions are characterized by acting upon a stream of data. Let x[−n], . . . , x[ [0315] C[ [0316] C[ [0317] . . . [0318] C[n+m]=A[n]*B[m]+Most Significant Word of C[n+m−1] [0319] These calculations can also be performed with very few lost cycles for the multiplier. Circuitry built around FIG. 25 has the advantage in that bounds checking (which requires at least two adders) can be done in a single cycle, and symmetric Matrix Linear Transformations can simultaneously be adding or subtracting vector elements while another adder is converting the multiplier's accumulator(s). [0320] Although the preferred embodiment has been described in detail, it should be understood that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended Referenced by
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