US20020008315A1 - Semiconductor package and method of fabricating the same - Google Patents
Semiconductor package and method of fabricating the same Download PDFInfo
- Publication number
- US20020008315A1 US20020008315A1 US09/858,408 US85840801A US2002008315A1 US 20020008315 A1 US20020008315 A1 US 20020008315A1 US 85840801 A US85840801 A US 85840801A US 2002008315 A1 US2002008315 A1 US 2002008315A1
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- Prior art keywords
- semiconductor package
- package according
- pattern
- fabricating
- forming
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052737 gold Inorganic materials 0.000 claims abstract description 35
- 239000010931 gold Substances 0.000 claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 239000011521 glass Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 229910000679 solder Inorganic materials 0.000 claims abstract description 16
- 239000003566 sealing material Substances 0.000 claims abstract description 11
- 238000007789 sealing Methods 0.000 claims abstract description 7
- 229910052738 indium Inorganic materials 0.000 claims description 12
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 239000002952 polymeric resin Substances 0.000 claims description 6
- 229920003002 synthetic resin Polymers 0.000 claims description 6
- 239000003822 epoxy resin Substances 0.000 claims description 5
- 229920000647 polyepoxide Polymers 0.000 claims description 5
- 239000004593 Epoxy Substances 0.000 claims description 4
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- 238000007906 compression Methods 0.000 claims description 4
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- 239000000463 material Substances 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 238000007650 screen-printing Methods 0.000 claims description 2
- 230000006835 compression Effects 0.000 claims 2
- 229920006336 epoxy molding compound Polymers 0.000 description 14
- 239000000919 ceramic Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract
Description
- The present invention relates to a semiconductor package, and more particularly to a semiconductor package which is minimized and thinned while having reliability and a method of fabricating the same.
- As is well known, microelectronic devices have a tendency to be minimized and thinned with its functional development and a semiconductor package mounted on a mother board is also following the tendency in order to realize a mounting of high integration.
- Most of these semiconductor packages have a structure that the semiconductor chips are sealed with a sealing material such as Epoxy Molding Compound (EMC) and a plurality of leads are fetched/formed outwardly from the sealing material.
- However, some devices such as Charge Coupled Device (CCD) have a characteristic that an active area thereof should be open, thereby it is difficult to be sealed with EMC. This is because the contact between the open active area of CCD and the EMC causes the CCD to have a defect.
- Therefore, it is suggested a packaging method using a base mold and a cover for packaging the semiconductor chip such as the CCD. A conventional semiconductor package according to the method using the base mold and cover will be described accompanying with FIGS. 1 and 2.
- FIG. 1 is a cross-sectional view of a conventional ceramic package using a base mold being consist of ceramic and a cover being consist of glass.
- As shown in FIG. 1, a semiconductor chip (5) such as CCD is mounted on a ceramic base mold (1) and the upper part of the ceramic base mold (1) is sealed with a glass (8) in order to prevent the semiconductor chip (5) from being contaminated. The ceramic base mold (1) has a rectangular shape as a whole having a cavity (2) of step i type therein and a plurality of leads (4) are fetched/formed outwardly from a step surface (3) of one side and the other sides. The semiconductor chip (5) is attached on the bottom of a cavity (2) by using an adhesive (6) of an epoxy type. A bonding pad (5 a) of the semiconductor chip (5) is electrically connected to one terminal, that is, electrode pad (4 a) of the lead (4) by an aluminum or a gold wire (7).
- FIG. 2 is a cross-sectional view of a conventional plastic package using EMC and glass. The same codes are used for the same parts as those of FIG. 1.
- As shown in FIG. 2, a semiconductor chip (5) is adhered on a die pad (11) of a conventional lead frame (20) composed of a die pad (11), an inner lead (12), and an outer lead (13) by an adhesive (6). The bonding pad (5 a) of the semiconductor chip (5) is electrically connected to the inner lead (12) of the lead frame (20) by aluminum or gold wire (7). The lower part of the semiconductor chip (5) and a selected part of the lead frame (20) are molded with EMC in order to prevent the upper part of the semiconductor chip (5) and the inner lead part which is wire-bonded thereto from being covered. The
code 21 is a EMC base mold composed of EMC. The upper part of the EMC base mold (21) is sealed with a glass (8) in order to prevent the semiconductor chip (5) from being contaminated. - However, it is difficult to minimize and lighten the above-mentioned packages because of the structural characteristics thereof. And, it is also difficult to be applied to packaging of highly integrated device since there is a limitation on the number of applicable leads.
- And, ceramic package is very expensive, thereby difficult to use. Moreover, a micro-gab between EMC and glass, that is, a difference in characteristics between EMC, an organic matter and glass, an inorganic matter degrades a quality and reliability of the plastic package. Contamination of the semiconductor chip due to alpha i particle from the EMC is also a cause to degrade a quality i and reliability.
- Therefore, the present invention was a proposal in order to solve the problem, it is an object of the present invention to provide a semiconductor package which is minimized and thinned while having reliability and the method of fabricating the same.
- According to one embodiment of the present invention, a semiconductor chip having bonding pads respectively arranged in a line adjacent to four sides of the upper surface; gold bumps formed on each bonding pad; a glass substrate which is made by forming metal patterns corresponding to the bonding pads on one side, the metal pattern consists of an inner pattern electrically connected to the bonding pad of the semiconductor chip through the gold bump, an outer pattern separated from the inner pattern and connecting pattern between the inner pattern and the outer pattern, and then forming Dam in a frame-shape on the connecting pattern and on the one side to surround the inner patterns; sealing material sealing the space between the glass substrate around the semiconductor chip to the Dam except for the outer pattern of the metal pattern; and solder balls attached on the outer patterns of each metal pattern.
- According to another embodiment of the present invention, a method of fabricating a semiconductor package comprises the steps of preparing a semiconductor chip having bonding pads arranged in a line adjacent to four sides of the upper surface and glass substrate which has formed metal patterns consisting of an inner pattern, an outer pattern and a connecting pattern on the position corresponding to the bonding pads; forming gold bumps on each bonding pad; forming a Dam in a frame-shape surrounding the inner patterns on the connecting patterns and the one side of the glass substrate; bonding the semiconductor chip and the glass substrate by using the gold bump to electrically connect the bonding pad and the inner pattern; sealing a space between the glass substrate around the semiconductor chip to the Dam except for the outer pattern; and attaching solder balls on the outer patterns of each metal pattern.
- The above objects, and other features and advantages of the present invention will become more apparent after reading the following detailed description when taken in conjunction with the drawings, in which:
- FIG. 1 is a cross-sectional view of a conventional ceramic package.
- FIG. 2 is a cross-sectional view of a conventional plastic package.
- FIG. 3 is a cross-sectional view of a semiconductor package according to the present invention.
- FIG. 4 is a floor plan of a glass substrate according to the present invention. FIGS. 5A to5D are process flows to show a method of fabricating a semiconductor package according to the present invention.
- FIG. 3 is a cross-sectional view illustrating a semiconductor package according to the embodiments of the present invention.
- As illustrated, there are provided a semiconductor chip (30) having bonding pads (30 a) dan a glass substrate (40) having formed metal patterns (35) thereon corresponding to the bonding pads (30 a). Here, the semiconductor chip (30) and the glass substrate (40) are arranged so that the bonding pads (30 a) and the metal pattern (35) are put opposite each other. One side (31: hereinafter, referred as inner pattern) of the bonding pad (30 a) and the metal pattern is bonded and electrically connected by the gold bump (41) formed on the bonding pad 10 (30 a). A solder ball (43) is attached on the other side (33: hereinafter, referred as outer pattern) of the metal pattern, thereby functioning as a mounting means on a mother board. The space between the glass substrate (40) around the semiconductor chip (30) to the Dam (36) except for the outer pattern (33) of the metal pattern (35) is sealed with sealing material(42) composed of epoxy or resin of polymer type.
- As the semiconductor chip is CCD, a color filter is formed on an active area of the upper surface thereof. Although it is not shown, the bonding pads (30 a) are respectively arranged in a line adjacent to four sides of upper surface of the semiconductor chip (30). The gold bump (41) if has a height of 50˜175 μm and a diameter of 50˜100 μm. The sealing material (42) has a characteristic of curing at a temperature of 70˜120° C., such as epoxy or resin of polymer type. A composition rate of tin to lead is 60˜80 to 40˜20 wt % in the solder ball (43) and silver, gold, chrome or cobalt is used as a dopant to increase reliability. The size of the dopant is about 10 to 40 mil.
- As shown in FIG. 4, the metal patterns (35) are formed on the position corresponding to each bonding pad of semiconductor chip and have a frame-shape, that is, the Dam (36) surrounds the inner pattern (31) of the metal pattern (35).
- The metal pattern (35) comprises an inner pattern (31), an outer pattern (33) and an connecting pattern between them. The metal pattern (35) is made of one compound selected from indium+tin, indium+tin+copper, indium+tin+gold or indium+tin+copper+gold. Alternatively, metals having a similar electric characteristic to these compounds are also used. The metal pattern (35) has a thickness over 1 μm, preferably 1 to 3 μm and a width over 50 μm, preferable 50 to 70 μm. In consideration of a contact with the gold bump (41), the inner pattern (31) has a size over 50 μm×50 μm, preferably 50 μm×50 μm to 100 μm×100 μm. And, in consideration of attachment of the solder ball (43), the outer pattern (33) has a size over 75 μm×75 μm, preferably 75 μm×75 μm to 100 μm×100 μm.
- The Dam (36) has a structure that it surrounds the inner patterns (31), that is, a frame-shape and it is formed on the connecting pattern (32) and the glass substrate (40). The Dam (36) is composed of opaque resin having no solvent such as epoxy or polymer resin. And, the width is about 30 to 100 μm and the height is 10 to 70 μm.
- The semiconductor package of the above structure has an economical advantage since high-priced ceramic base mold is not used. Moreover, it has reliability since EMC generating alpha particles is not used.
- A method of fabricating the semiconductor package according to the present invention will be described referring to FIGS. 5A to5D.
- Referring to FIG. 5A, there is provided a semiconductor chip (30) having bonding pads (30 a) arranged in a line adjacent to each four side. And, gold bumps (41) are formed on each bonding pad (30 a). The gold bump (41) is preferably formed by Stud Bump Bonding (SSB) at a temperature of 150 to 280° C. under a pressure of 20 to 250 and a power of 30 to 150 mW. And, the gold bump(41) has a height of 50 to 175 μm and diameter of 50 to 100 μm. Here, the height can be controlled by the method such as tearing, pulling or coining.
- Referring to FIG. 5B, the metal patterns (35) are formed corresponding to the bonding pads (30 a), and subsequently, there is provided a glass substrate having formed a Dam (36) therein. The metal pattern (35) comprises an inner pattern (31), a connecting pattern (32) and outer pattern (33) and the Dam (36) is formed in a frame-shape to surround the inner patterns (31) on the connecting pattern (32) and the glass substrate (40). The Dam is formed on the connecting pattern approximately 20 μm separated from the inner pattern (31) by screen printing or dispensing to have a height of 10 to 70 μm and a width of 30 to 100 μm.
- Referring to FIG. 5C, the semiconductor chips (30) are arranged on the upper portion of the glass substrate (40) so that the gold bumps (41) on the bonding pad(30 a) are arranged on the upper portion of the inner pattern (31) Subsequently, the semiconductor chip (30) is bonded on the glass substrate (40) in accordance with a thermal compression process. Here, the bonding pad (30 a) and the inner pattern (31) are electrically connected by the gold bump(41). The thermal compression process is conducted at a temperature of 100 to 150° C. under a pressure of 50 gf/Bump and for 2 to 5 seconds.
- Referring to FIG. 5D, the areas around the semiconductor chip (30), that is, four sides of semiconductor chip (30) except for the outer pattern (33) are sealed to the Dam (36) with sealing material (42). The object of sealing is to have reliability of semiconductor chip (30) and the metal pattern (35). The materials curing at a temperature of 70 to 120-C. are used as a sealing material, for example, epoxy or polymer resin.
- Subsequently, as shown in FIG. 3, a solder ball functioning as mounting means on the mother board is attached on the outer pattern (33) of the metal pattern (35), thereby obtaining a semiconductor package according to the present invention. The solder ball (43) has a size of about 10 to 40 mil.
- As described above, a semiconductor package according to the present invention has advantages of reducing cost and improving reliability since it does not use ceramic base mold and EMC. And, a semiconductor package according to the present invention can be minimized and thinned more easily since it has a structure that the chip and substrate are electrically connected by a gold bump.
- Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of the present invention.
Claims (30)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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KR00-42377 | 2000-07-24 | ||
KR2000-42377 | 2000-07-24 | ||
KR1020000042377A KR100343432B1 (en) | 2000-07-24 | 2000-07-24 | Semiconductor package and package method |
Publications (2)
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US20020008315A1 true US20020008315A1 (en) | 2002-01-24 |
US6441478B2 US6441478B2 (en) | 2002-08-27 |
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US09/858,408 Expired - Fee Related US6441478B2 (en) | 2000-07-24 | 2001-05-16 | Semiconductor package having metal-pattern bonding and method of fabricating the same |
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Country | Link |
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US (1) | US6441478B2 (en) |
JP (1) | JP2002118207A (en) |
KR (1) | KR100343432B1 (en) |
TW (1) | TW498508B (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004034476A2 (en) * | 2002-10-08 | 2004-04-22 | Freescale Semiconductor, Inc. | Flip chip imaging sensor |
EP1672693A1 (en) * | 2003-09-25 | 2006-06-21 | Hamamatsu Photonics K.K. | Semiconductor device |
US20070272997A1 (en) * | 2003-09-25 | 2007-11-29 | Hiroya Kobayashi | Semiconductor Device and Method for Manufacturing the Same |
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Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1243026A1 (en) * | 1999-12-21 | 2002-09-25 | Advanced Micro Devices, Inc. | Organic packages with solders for reliable flip chip connections |
US6528857B1 (en) | 2000-11-13 | 2003-03-04 | Amkor Technology, Inc. | Chip size image sensor bumped package |
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US20060043513A1 (en) * | 2004-09-02 | 2006-03-02 | Deok-Hoon Kim | Method of making camera module in wafer level |
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JP2007048976A (en) * | 2005-08-10 | 2007-02-22 | Toshiba Corp | Printed circuit board and electronic instrument equipped therewith |
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JP2011243612A (en) | 2010-05-14 | 2011-12-01 | Sony Corp | Semiconductor device and its manufacturing method and electronic apparatus |
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CN103474364B (en) * | 2013-09-04 | 2016-11-09 | 惠州硕贝德无线科技股份有限公司 | A kind of novel method for packaging semiconductor |
JP6570728B2 (en) * | 2016-02-18 | 2019-09-04 | 三菱電機株式会社 | Electronic device and manufacturing method thereof |
KR102589281B1 (en) * | 2020-06-26 | 2023-10-16 | 주식회사 네패스 | Semiconductor package |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6013946A (en) * | 1996-09-11 | 2000-01-11 | Samsung Electronics Co., Ltd. | Wire bond packages for semiconductor chips and related methods and assemblies |
US6060340A (en) * | 1998-07-16 | 2000-05-09 | Pan Pacific Semiconductor Co., Ltd. | Packing method of semiconductor device |
US6165816A (en) * | 1996-06-13 | 2000-12-26 | Nikko Company | Fabrication of electronic components having a hollow package structure with a ceramic lid |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4999699A (en) | 1990-03-14 | 1991-03-12 | International Business Machines Corporation | Solder interconnection structure and process for making |
KR100248792B1 (en) | 1996-12-18 | 2000-03-15 | 김영환 | Chip size semiconductor package using single layer ceramic substrate |
US6091140A (en) | 1998-10-23 | 2000-07-18 | Texas Instruments Incorporated | Thin chip-size integrated circuit package |
-
2000
- 2000-07-24 KR KR1020000042377A patent/KR100343432B1/en not_active IP Right Cessation
-
2001
- 2001-04-26 TW TW090110050A patent/TW498508B/en not_active IP Right Cessation
- 2001-05-16 US US09/858,408 patent/US6441478B2/en not_active Expired - Fee Related
- 2001-07-24 JP JP2001222515A patent/JP2002118207A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6165816A (en) * | 1996-06-13 | 2000-12-26 | Nikko Company | Fabrication of electronic components having a hollow package structure with a ceramic lid |
US6013946A (en) * | 1996-09-11 | 2000-01-11 | Samsung Electronics Co., Ltd. | Wire bond packages for semiconductor chips and related methods and assemblies |
US6060340A (en) * | 1998-07-16 | 2000-05-09 | Pan Pacific Semiconductor Co., Ltd. | Packing method of semiconductor device |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004034476A2 (en) * | 2002-10-08 | 2004-04-22 | Freescale Semiconductor, Inc. | Flip chip imaging sensor |
WO2004034476A3 (en) * | 2002-10-08 | 2004-05-27 | Motorola Inc | Flip chip imaging sensor |
US7696595B2 (en) | 2003-09-25 | 2010-04-13 | Hamamatsu Photonics K.K. | Semiconductor device and method for manufacturing the same |
US20070272998A1 (en) * | 2003-09-25 | 2007-11-29 | Hamamatsu Photonics K.K. | Semiconductor Device |
EP1672693A4 (en) * | 2003-09-25 | 2008-09-10 | Hamamatsu Photonics Kk | Semiconductor device |
US7605455B2 (en) | 2003-09-25 | 2009-10-20 | Hamamatsu Photonics K.K. | Semiconductor device |
US7612442B2 (en) | 2003-09-25 | 2009-11-03 | Hamamatsu Photonics K.K. | Semiconductor device |
EP1672693A1 (en) * | 2003-09-25 | 2006-06-21 | Hamamatsu Photonics K.K. | Semiconductor device |
US20070272997A1 (en) * | 2003-09-25 | 2007-11-29 | Hiroya Kobayashi | Semiconductor Device and Method for Manufacturing the Same |
US10510719B2 (en) | 2014-07-08 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company | Methods of packaging semiconductor devices and packaged semiconductor devices |
US9847317B2 (en) | 2014-07-08 | 2017-12-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of packaging semiconductor devices and packaged semiconductor devices |
US10043778B2 (en) | 2014-07-08 | 2018-08-07 | Taiwan Semiconductor Manufacturing Company | Methods of packaging semiconductor devices and packaged semiconductor devices |
US11877044B2 (en) | 2016-02-18 | 2024-01-16 | Ningbo Sunny Opotech Co., Ltd. | Integral packaging process-based camera module, integral base component of same, and manufacturing method thereof |
CN105977225A (en) * | 2016-07-04 | 2016-09-28 | 苏州晶方半导体科技股份有限公司 | Packaging structure and packaging method |
TWI698968B (en) * | 2016-07-04 | 2020-07-11 | 大陸商蘇州晶方半導體科技股份有限公司 | Packing structure and packing method |
US20190259634A1 (en) * | 2016-07-04 | 2019-08-22 | China Wafer Level Csp Co., Ltd. | Packaging structure and packaging method |
US20210098517A1 (en) * | 2019-09-27 | 2021-04-01 | Powertech Technology Inc. | Semiconductor package structure and manufacturing method thereof |
US11522000B2 (en) * | 2019-09-27 | 2022-12-06 | Powertech Technology Inc. | Semiconductor package structure and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
KR100343432B1 (en) | 2002-07-11 |
TW498508B (en) | 2002-08-11 |
JP2002118207A (en) | 2002-04-19 |
KR20020009087A (en) | 2002-02-01 |
US6441478B2 (en) | 2002-08-27 |
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