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Publication numberUS20020011889 A1
Publication typeApplication
Application numberUS 09/961,070
Publication dateJan 31, 2002
Filing dateSep 24, 2001
Priority dateFeb 2, 1999
Also published asUS6472924
Publication number09961070, 961070, US 2002/0011889 A1, US 2002/011889 A1, US 20020011889 A1, US 20020011889A1, US 2002011889 A1, US 2002011889A1, US-A1-20020011889, US-A1-2002011889, US2002/0011889A1, US2002/011889A1, US20020011889 A1, US20020011889A1, US2002011889 A1, US2002011889A1
InventorsTetsuro Takenaka
Original AssigneeTetsuro Takenaka
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor integral circuit
US 20020011889 A1
Abstract
In a semiconductor integral circuit having a transistor or an inverter, a leak current of the transistor or a through current of the inverter, respectively, or the like is reduced. The semiconductor integral circuit has an analog circuit which changes linearly the voltage of an input signal and causes the amount of a current flowing through the analog circuit to change in accordance with the change in the voltage of the input signal. The semiconductor integral circuit also has a logic circuit to which an input signal having a first or second voltage is input. This logic circuit outputs an output signal having the first or second voltage in response to the first or second voltage of the input signal. The absolute value of the threshold value of the MOS transistor of the analog circuit is set smaller than the absolute value of the threshold value of the MOS transistor of the logic circuit.
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Claims(10)
What is claimed is:
1. A semiconductor integral circuit comprising:
an analog circuit which changes linearly a voltage of an input signal and causes an amount of a current flowing through said analog circuit to change in accordance with said change in said voltage of said input signal, said analog circuit having a MOS transistor; and
a logic circuit to which an input signal having a first or second voltage is input and which outputs an output signal having said first or second voltage in response to said first or second voltage of said input signal, said logic circuit having a MOS transistor,
wherein an absolute value of a threshold value of said MOS transistor of said analog circuit is set smaller than an absolute value of a threshold value of said MOS transistor of said logic circuit.
2. A semiconductor integral circuit as claimed in claim 1, wherein said analog circuit has a first N-channel type MOS transistor and a first P-channel type MOS transistor, and said logic circuit has a second N-channel type MOS transistor and a second P-channel type MOS transistor, said semiconductor integral circuit satisfying relations Vtn1+|Vtp1|<Vcc, Vcc<Vtn2+|Vtp2|<2Vcc, Vtn2<Vcc, and |Vtp2|<Vcc, where Vtn1, Vtp1, Vtn2, and Vtp2 denote threshold values of said first N-channel MOS transistor, said first P-charmel MOS transistor, said second N-channel MOS transistor and said second P-channel MOS transistor, respectively, and Vcc and GND denote said first voltage and said second voltage, respectively.
3. A semiconductor integral circuit as claimed in claim 2, wherein said threshold value of each of said transistors is set by controlling an amount of ions injected into a semiconductor substrate in which each of said transistors is formed.
4. A semiconductor integral circuit as claimed in claim 2, wherein said first N-channel type MOS transistor, said second N-channel first type MOS transistor, said first P-channel type MOS transistor, and said second P-channel type MOS transistor are formed in a first P-type semiconductor substrate, a second P-type semiconductor substrate, a first N-type semiconductor substrate, and a second N-type semiconductor substrate, respectively,
and wherein each of said semiconductor substrates is biased to a prescribed voltage such that said first P-type semiconductor substrate is biased to a first prescribed voltage that is higher than a second prescribed voltage to which said second P-type semiconductor substrate is biased and such that an absolute value of a third prescribed voltage to which said first N-type semiconductor substrate is biased is smaller than an absolute value of a fourth prescribed voltage to which said second N-type semiconductor substrate is biased.
5. A semiconductor integral circuit as claimed in claim 4, satisfying relations VBB1≧GND, VPP1≦Vcc, VBB2≦GND, and VPP2≧Vcc, where VBB1, VBB2, VPP1, and VPP2 denote voltages biased to said first P-type semiconductor substrate, said second P-type semiconductor substrate, said first N-type semiconductor substrate, and said second N-type semiconductor substrate, respectively.
6. A semiconductor integral circuit driven by a first voltage and a second voltage, comprising:
an analog circuit to which an analog input signal having a voltage that changes continuously between said first voltage and said second voltage is input and which outputs an analog output signal in response to said analog input signal, said analog circuit having a MOS transistor; and
a logic circuit to which a first logic level input signal having said first voltage or a second logic level input signal having said second voltage is input and which outputs a first logic level output signal in response to said first logic level input signal or a second logic level output signal in response to said second logic level input signal, said logic circuit having a MOS transistor,
wherein an absolute value of a threshold value of said MOS transistor of said analog circuit is set smaller than an absolute value of a threshold value of said MOS transistor of said logic circuit.
7. A semiconductor integral circuit as claimed in claim 6, wherein said analog circuit has a first N-channel type MOS transistor and a first P-channel type MOS transistor and said logic circuit has a second N-channel type MOS transistor and a second P-channel type MOS transistor, said semiconductor integral circuit satisfying relations Vtn1+|Vtp1|<Vcc, Vcc<Vtn2+|Vtp2|<2Vcc, Vtn2<Vcc, and |Vtp2|<Vcc, where Vtn1, Vtp1, Vtn2, and Vtp2 denote threshold values of said first N-channel MOS transistor, said first P-channel MOS transistor, said second N-channel MOS transistor and said second P-channel MOS transistor, respectively, and Vcc and GND denote said first voltage and said second voltage, respectively.
8. A semiconductor integral circuit as claimed in claim 7, wherein said threshold value of each of said transistors is set by controlling an amount of ions injected into a semiconductor substrate in which each of said transistors is formed.
9. A semiconductor integral circuit as claimed in claim 7, wherein said first N-channel type MOS transistor, said second N-channel first type MOS transistor, said first P-channel type MOS transistor, and said second P-channel type MOS transistor are formed in a first P-type semiconductor substrate, a second P-type semiconductor substrate, a first N-type semiconductor substrate, and a second N-type semiconductor substrate, respectively,
and wherein each of said semiconductor substrates is biased to a prescribed voltage such that said first P-type semiconductor substrate is biased to a first prescribed voltage that is higher than a second prescribed voltage to which said second P-type semiconductor substrate is biased and such that an absolute value of a third prescribed voltage to which said first N-type semiconductor substrate is biased is smaller than an absolute value of a fourth prescribed voltage to which said second N-type semiconductor substrate is biased.
10. A semiconductor integral circuit as claimed in claim 9, satisfying relations VBB1≧GND, VPP1≦Vcc, VBB2≦GND, and VPP2≧Vcc, where VBB1, VBB2, VPP1, and VPP2 denote voltages biased to said first P-type semiconductor substrate, said second P-type semiconductor substrate, said first N-type semiconductor substrate, and said second N-type semiconductor substrate, respectively.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor integral circuit that operates with a low voltage.

[0003] 2. Description of Related Art

[0004] In recent years, semiconductor integral circuits that operate with a low voltage are being developed. In this type of circuit, the threshold values of P channel type MOS transistors (PMOS hereafter) and N channel type MOS transistors (NMOS hereafter), which constitute the semiconductor integral circuits, are adjusted so as to achieve low voltage operation.

[0005] In other words, the threshold value of each of the PMOS transistors that constitutes a semiconductor integral circuit that operates with a low voltage is set higher than the threshold value of PMOS transistors that constitutes a semiconductor integral circuit that operates with a high voltage. In the case of a PMOS transistor, the threshold value is negative. Therefore, the absolute value of the threshold value of a PMOS that constitutes a semiconductor integral circuit that operates with a low voltage is set smaller than the absolute value of the threshold value of a PMOS that constitutes a semiconductor integral circuit that operates with a high voltage. In the case of an NMOS transistor, the threshold value is positive. Therefore, the threshold value of an NMOS transistor that constitutes a semiconductor integral circuit that operates with a low voltage is set smaller than the threshold value of an NMOS transistor that constitutes a semiconductor integral circuit that operates with a high voltage.

[0006] In a semiconductor integral circuit that operates with a low voltage having PMOS transistors and NMOS transistors, the threshold values of the PMOS transistors are large and the threshold values of the NMOS transistors are small. Therefore, in such a semiconductor integral circuit, the leak current of the transistor increases, and the through current of an inverter or the like increases.

SUMMARY OF THE INVENTION

[0007] Given these problems, in a semiconductor integral circuit that operates with a low voltage having PMOS transistors and NMOS transistors, it is an object of the present invention to reduce the leak current of the transistors and the through current of the inverters.

[0008] To achieve the above-stated objectives, a semiconductor integral circuit according to the present invention has an analog circuit which changes linearly the voltage of an input signal and causes the amount of a current flowing through the analog circuit to change in accordance with the change in the voltage of the input signal. This semiconductor integral circuit also has a logic circuit to which an input signal having a first or second voltage is input. This logic circuit outputs an output signal having the first or second voltage in response to the first or second voltage of the input signal. The absolute value of the threshold value of each MOS transistor of the analog circuit is smaller than the absolute value of the threshold value of each MOS transistor of the logic circuit.

[0009] According to the present invention, in the semiconductor integral circuit, highly sensitive operation of the analog circuit is guaranteed, and the leak current and through current in the logic circuit can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is a block diagram showing a semiconductor integral circuit according to an embodiment of the present invention.

[0011]FIG. 2 is a partial circuit diagram showing an exemplary configuration of an analog circuit and a logic circuit according to the embodiment of the present invention.

[0012]FIG. 3(a) shows an exemplary diode-connected NMOS transistor according to the embodiment of the present invention.

[0013]FIG. 3(b) shows an exemplary diode-connected PMOS transistor according to the embodiment of the present invention.

[0014]FIG. 4 shows an exemplary configuration of a charge pump circuit according to the embodiment of the present invention.

[0015]FIG. 5 shows an exemplary configuration of a decoder circuit as the logic circuit according to the embodiment of the present invention.

[0016]FIG. 6 shows an exemplary configuration of a counter circuit as the logic circuit according to the embodiment of the present invention.

[0017]FIG. 7 shows a first method for setting the absolute value of each of the transistors of the analog circuit smaller than the absolute value of each of the transistors of the logic circuit.

[0018]FIG. 8 shows a second method for setting the absolute value of each of the transistors of the analog circuit smaller than the absolute value of each of the transistors of the logic circuit.

[0019]FIG. 9 shows a third method for setting the absolute value of each of the transistors of the analog circuit smaller than the absolute value of each of the transistors of the logic circuit.

[0020]FIG. 10 is a partial cross sectional view for explaining another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0021] In what follows, embodiments of the present invention will be explained with reference to the attached drawings. The following explanation will be focused on parts that are directly related to the present invention. The other parts will not be explained.

[0022]FIG. 1 shows a semiconductor integral circuit 100, and an analog circuit 200 and a logic circuit 300 that are formed in prescribed regions of this semiconductor integral circuit 100. The analog circuit 200 and the logic circuit 300 are electrically connected to each other. This semiconductor integral circuit 100 is driven by a power source voltage Vcc supplied from a power source and a ground voltage GND supplied from the ground.

[0023] In the analog circuit 200, the voltage of an input signal changes linearly and the amount of a current that flows inside the analog circuit 200 changes in accordance with the change in the voltage of the input signal.

[0024] An input signal having the power source voltage Vcc or the ground voltage GND is input to the logic circuit 300. in response to the voltage of this input signal, the logic circuit 300 outputs an output signal having the power source voltage Vcc or the ground voltage GND.

[0025]FIG. 2 shows an exemplary configuration of a circuit that constitutes a portion of the analog circuit 200 and logic circuit 300.

[0026] As shown in FIG. 2, the analog circuit 200 has a differentiating amplifier circuit 210 and an analog output circuit 220 that outputs an output signal in response to a signal output from the differentiating amplifier circuit 210. The logic circuit 300 has a first inverter 310 which receives the output signal from the analog output circuit 220 and outputs an inverted signal and a second inverter 320 which receives the inverted signal from the first inverter 310 and outputs an inverted signal.

[0027] The differentiating amplifier circuit 210 has a first PMOS transistor 211, a second PMOS transistor 212, a first NMOS transistor 213, a second NMOS transistor 214, and a third NMOS transistor 215.

[0028] The first PMOS transistor 211 is connected between the power source Vcc and the node N1. The gate electrodes of the first PMOS transistor 211 are connected to the node N1 and the gate electrodes of the second PMOS transistor 212. The second PMOS transistor 212 is connected between the power source Vcc and the node N2. The first NMOS transistor 213 is connected between the node N1 and the node N3. An input signal IN is supplied to the gate electrodes of the first NMOS transistor 213. This input signal IN is an analog signal whose voltage level changes linearly.

[0029] The second NMOS transistor 214 is connected between the node N2 and the node N3. The inverted signal /IN of the input signal IN is supplied to the gate electrodes of the second NMOS transistor 214.

[0030] The third NMOS transistor 215 is connected between the node N3 and the ground GND. A control signal EN is supplied to the gate electrodes of the third NMOS transistor 215. When this control signal EN becomes a high level signal (power source voltage level) and the third NMOS transistor 215 is turned on, the differentiating amplifier circuit 210 is activated.

[0031] The analog output circuit 220 is constituted of a PMOS transistor 221 and an NMOS transistor 222. The PMOS transistor 221 is connected between the power source Vcc and the output node N4. The NMOS transistor 222 is connected between the output node N4 and the ground GND. The gate electrodes of the PMOS transistor 221 and NMOS transistor 222 are connected to the node N2.

[0032] The inverter 310 is constituted of a PMOS transistor 311 and an NMOS transistor 312. The PMOS transistor 311 is connected between the power source Vcc and the output node N5. The NMOS transistor 312 is connected between the output node N5 and the ground GND. The gate electrodes of the PMOS transistor 311 and NMOS transistor 312 are connected to the node N4.

[0033] The inverter 320 is constituted of a PMOS transistor 321 and an NMOS transistor 322. The PMOS transistor 321 is connected between the power source Vcc and output node N6. The NMOS transistor 322 is connected between the output node N6 and the ground GND. The gate electrodes of the PMOS Transistor 321 and NMOS transistor 322 are connected to the node N5. The output node N6 is connected to the output terminal OUT of the logic circuit 300.

[0034] The operation of these circuits will now be explained in a comprehensive manner.

[0035] First, when the control signal EN is inout to the third NMOS transistor 215, the third NMOS transistor 215 becomes conductive. When the input signal IN and the inverted signal /IN are input to the first NMOS transistor 213 and second NMOS transistor 214, respectively, a current flows through the differentiating amplifier circuit 210 in accordance with the voltage level of the input signal IN. The voltage at the node N2 also changes in accordance with the amount of this current.

[0036] When the voltage at this node N2 exceeds a prescribed level, the analog output circuit 220 outputs a low level (ground voltage level) signal. That is, the voltage at the node N4 becomes equal to the ground voltage level GND. On the other hand, when the voltage at this node N2 drops below another prescribed level, the analog output circuit 220 outputs a high level (power source voltage level) signal. That is, the voltage at the node N2 becomes equal to the power source voltage level Vcc.

[0037] The high level (power source voltage level) signal or the low level (ground voltage level) signal output from the analog output circuit 220 is input to the first stage inverter 310 of the logic circuit 300. The inverter 310 then inverts this input signal and outputs from the output node N5 the inverted high level (power source voltage level) signal or the inverted low level (ground voltage level) signal.

[0038] The inverted high level (power source voltage level) signal or the inverted low level (ground voltage level) signal output from the node N5 is input to the inverter 320. The inverter 320 then inverts the input signal and outputs from the output node N6 the inverted high level (power source voltage level) signal or the inverted low level (ground voltage level) signal.

[0039] In the above-provided explanation of the circuits and the operations of the circuits, exemplary analog circuits and logic circuits to which the present invention is applicable are described. Since the circuits used in the explanation are typical ones, it should be easy to understand the operations of these circuits.

[0040] In what follows, the characteristics of the present invention will be explained.

[0041] In the present invention, the absolute value of the threshold value of each of the MOS transistors that constitute the analog circuit 200 is set smaller than the absolute value of the threshold value of each of the MOS transistors that constitute the logic circuit 300.

[0042] In other words, if the threshold value of each of the PMOS transistors that constitute the analog circuit 200 is denoted by Vtpl, if the threshold value of each of the NMOS transistors that constitute the analog circuit 200 is denoted by Vtnl, if the threshold value of each of the PMOS transistors that constitute the logic circuit 300 is denoted by Vtp2, and if the threshold value of each of the NMOS transistors that constitute the logic circuit 300 is denoted by Vtn2, then these threshold values satisfy the following inequalities (1).

Vtn1<Vtn2, |Vtp1|<|Vtp2|  (1)

[0043] In other words, the threshold value of each of the NMOS transistors that constitute the analog circuit 200 is set smaller than that of each of the NMOS transistors that constitute the logic circuit 300. The threshold value of each of the PMOS transistors that constitute the analog circuit 200 is set larger than that of each of the PMOS transistors that constitute the logic circuit 300. Since the threshold values of PMOS transistors are negative, the absolute value of the threshold value of each of the PMOS transistors that constitute the analog circuit 200 is set smaller than that of each of the PMOS transistors that constitute the logic circuit 300.

[0044] Moreover, if the power source voltage is denoted by Vcc, then the following inequality (2) is also satisfied in the analog circuit 200.

Vtn1+Vtp1<Vcc  (2)

[0045] In other words, the sum of the threshold value of any of the NMOS transistors and the absolute value of the threshold value of any of the PMOS transistors is smaller than the power source voltage Vcc.

[0046] Moreover, the following inequalities (3a), (3b) and (3c) are satisfied in the logic circuit 300.

Vcc<Vtn2+|Vtp2|<2Vcc  (3a)

Vtn2<Vcc  (3b)

51 Vtp2|<Vcc  (3c)

[0047] In other words, in the logic circuit 300, the sum of the threshold value of any of the NMOS transistors and the absolute value of the threshold value of any of the PMOS transistors is set larger than the power source voltage Vcc and smaller than 2Vcc, that is, twice the power source voltage. Moreover, both the threshold value of any of the NMOS transistors and the absolute value of the threshold value of any of the PMOS transistors are smaller than the power source voltage Vcc.

[0048] In this embodiment, the power source voltage Vcc and the ground voltage GND are set to 1.8V and 0V, respectively. The threshold value Vtp1 of any of the PMOS transistors that constitute the analog circuit 200 is set to a value between 0.5V and −0.7V. The threshold value Vtn1 of any of the NMOS transistors that constitute the analog circuit 200 is set to a value between 0.5V and 0.7V. The threshold value Vtp2 of any of the PMOS transistors that constitute the logic circuit 300 is set to a value between −0.7V and −1.5V. The threshold value Vtn2 of any of the NMOS transistors that constitute the logic circuit 300 is set to a value between 0.7V and 1.5V. All of these threshold values are set so as to satisfy the inequalities (1), (2), (3a), (3b), and (3c).

[0049] In practice, the design engineers can determine the threshold value of each of the transistors taking into consideration the relation between the above-provided inequalities and the power source voltage and the margin of circuit operation and the like.

[0050] By setting the threshold value of each of the transistors in the above-described manner, not only highly sensitive operation of the analog circuit 200 is guaranteed but also the leak current and the through current in the logic circuit can be reduced.

[0051] In other words, as the threshold voltage values of the transistors are made lower, the range of transition of the input signal, that is, the range of voltage variation of the input signal becomes narrow. Therefore, by setting the absolute value of the threshold value of each of the transistors that constitute the analog circuit smaller than the absolute value of the threshold value of each of the transistors that constitute the logic circuit, a circuit configuration capable of responding to a micro change in the input signal is realized.

[0052] On the other hand, if transistors having a small threshold value are installed in the logic circuit also as in the case of the conventional circuit, the leak current in each of the transistors increases and the through current in each of the inverters increases. Therefore, the absolute value of the threshold value of each of the transistors that constitute the logic circuit is set larger than the absolute value of the threshold value of each of the transistors that constitute the analog circuit. Hence, the leak current in each of the transistors and the through current in each of the inverters can be reduced inside the logic circuit.

[0053] The present invention solves the mutually compromising problems of improving the operation sensitivity of the analog circuit and reducing the leak current and the through current in the logic circuit. Therefore, the power consumption of the semiconductor integral circuit can be reduced while improving the sensitivity of the semiconductor integral circuit.

[0054] In many cases, semiconductor integral circuits that operate with a low voltage are driven using cells such as batteries or the like as a power source. Therefore, being able to reduce the power consumption of the semiconductor integral circuit is a very significant advantage. In other words, the present invention extends the life of the cells that drive the semiconductor integral circuits.

[0055] In the above-explained embodiment, a differentiating amplifier circuit is used as the analog circuit and an inverter circuit is used as the logic circuit. However, the range of technical applications of the present invention is not limited to these circuits.

[0056] Any circuit may be used for the analog circuit provided that the circuit changes linearly the voltage of an input signal and that the circuit causes the amount of the current flowing through the circuit to change in accordance with the change in the voltage of the input signal. Various configurations can be considered for the analog circuit such as a diode-connected MOS transistor, a charge pump circuit, a bias voltage generator circuit, an AD converter, and the like. Moreover, various kinds of specific configurations can be selected for each of these circuits.

[0057]FIG. 3(a) shows an exemplary diode-connected NMOS transistor. FIG. 3(b) shows an exemplary diode-connected PMOS transistor. In this case, the amount of a current flowing through the transistor changes in accordance with the change in the voltage of the input signal IN. The output is then supplied to the output terminal OUT in accordance with the change in the amount of the current flowing through the transistor.

[0058]FIG. 4 shows an exemplary configuration of a charge pump circuit. This charge pump circuit has NMOS transistors 401 and 402, and a capacitor 403.

[0059] An input signal is supplied to one electrode of the NMOS 401, and the ground voltage is supplied to the other electrode of the NMOS 401. The one electrode of the NMOS 401 is connected to the gate electrode of the NMOS 401. The input signal is also supplied to one electrode of the NMOS 402, and the other electrode of the NMOS 402 is connected to the capacitor 403 and the output terminal OUT. The other electrode of the NMOS 402 is connected to the gate electrode of the NMOS 402.

[0060] In this charge pump circuit also, the amount of the current that flows through each of the transistors changes in accordance with the change in the voltage of the input signal IN. The voltage is charged in accordance with the change in the amount of the current that flows through each of the transistors and the output is supplied to the output terminal OUT.

[0061] Any circuit may be used for the logic circuit 300 provided that an input signal having the power source voltage or the ground voltage is input to the circuit and that the circuit outputs an output signal having the power source voltage or the ground voltage in response to the voltage of the input signal. Various configurations can be considered for the logic circuit, such as an inverter, a NOR circuit, an NAND circuit, a decoder circuit (an exemplary decoder circuit is shown in FIG. 5), a flip flop circuit (an exemplary flip flop circuit is shown in FIG. 6), a counter circuit, an oscillator circuit, and the like. Moreover, various kinds of specific configurations can be selected for each of these circuits.

[0062] Methods for setting the threshold values of MOS transistors in the above-described manner will now be explained. In other words, methods for setting the absolute value of each of the transistors of the analog circuit smaller than the absolute value of each of the transistors of the logic circuit will be explained.

[0063] First, with reference to FIG. 7, a method for forming two N-type wells in a P-type semiconductor substrate and a P-type well in one of the two N-type wells will be explained. In this case, ions are injected into each well so as to adjust the concentration in the well in forming the well.

[0064] To be more specific, boron ions of prescribed concentration are injected into the P-type well P2 so that the concentration in the P-type well P2 will be higher than that in the P-type semiconductor substrate P1. As a result, the threshold value of an NMOS transistor to be formed later inside the P-type well P2 will be increased. Thus, NMOS transistors of the analog circuit are formed in the P-type semiconductor substrate P1, and NMOS transistors of the logic circuit are formed in the P-type well P2.

[0065] Moreover, phosphorus ions having a first prescribed concentration are injected into the N-type well N1 and phosphorus ions having a second prescribed concentration are injected into the N-type well N2 so that the concentration in the N-type well N2 will be higher than that in the N-type well N1. As a result, the threshold value of a PMOS transistor to be formed later inside the N-type well N2 will be increased. Thus, PMOS transistors of the analog circuit are formed in the N-type well N1, and PMOS transistors of the logic circuit are formed in the N-type well N2.

[0066]FIG. 8 shows a second method for setting the absolute value of each of the transistors of the analog circuit smaller than the absolute value of each of the transistors of the logic circuit. In this second method, a field oxide film is first formed as shown in FIG. 8, and then ions are injected into an active region AC in which a transistor is to be formed.

[0067] To be more specific, after the field oxide film is formed, all the regions but the predetermined active region AC are covered with a resist, and then ions are injected into the active region AC. In this case, the threshold value of an NMOS transistor to be formed later will be decreased if phosphorus ions are injected into a region in which the NMOS transistor is to be formed. The threshold value of the NMOS to be formed later will be increased if boron ions are injected into the region. Similarly, the absolute value of the threshold value of a PMOS to be formed later will be increased if phosphorus ions are injected into a region in which the PMOS transistor is to be formed. The absolute value of the threshold value of the PMOS to be formed later will be decreased if boron ions are injected into the region.

[0068]FIG. 9 shows a third method for setting the absolute value of each of the transistors of the analog circuit smaller than the absolute value of each of the transistors of the logic circuit. In this third method, gate electrodes are first formed, and then ions are injected into a predetermined active region from above the gate electrodes.

[0069] In these methods, the design engineers can determine what ions to be injected and the concentration of the ions, while taking into consideration the relation between the above equations and the power source voltage, the margin of circuit operation, and the like.

[0070] Next, another embodiment of the present invention will be explained with reference to FIG. 10. In the example shown in FIG. 7, the threshold value of each of the MOS transistors to be formed later is adjusted by injecting ions in forming the wells. In contrast, in the embodiment to be shown, the threshold value of each of the MOS transistors, is adjusted by a bias voltage to be supplied to the substrate or well (sometimes wells are collectively referred to as substrates also) in which the MOS transistor is formed. This embodiment will be explained using the analog output circuit 220 in the analog circuit 200 and the inverter 310 in the logic circuit 300. FIG. 10 is a cross sectional view of these circuits. In FIG. 10, the “N+” indicate regions in which an N-type concentration is high and the “P+” indicate regions in which a P-type concentration is high.

[0071] The NMOS transistor 222 of the analog output circuit 220 is formed in the P-type semiconductor substrate P1, and the PMOS transistor 221 of the analog output circuit 220 is formed in the N-type well N1.

[0072] The NMOS transistor 312 of the logic circuit 310 is formed in the P-type semiconductor substrate P2, and the PMOS transistor 311 of the logic circuit 310 is formed in the N-type well N2.

[0073] The characteristic of this embodiment is that the P-type well P2 is biased with a bias voltage VBB that is sufficiently lower than the ground voltage GND, and that the N-type well N2 is biased with a bias voltage VBB that is sufficiently higher than the power source voltage Vcc.

[0074] The P-type semiconductor substrate P1 is biased with the ground voltage GND and the N-type well N1 is biased with the power source voltage Vcc. However, the present embodiment is not limited to this configuration.

[0075] In other words, any other setup is admissible provided that the bias voltage for the substrate or each well is set to satisfy the following inequalities. Denoting the bias voltages for the P-type semiconductor substrate P1, P-type well P2, Ntype well N1, and N-type well N2 by VBB1, VBB2, VPP1, and VPP2, respectively, the following inequalities are satisfied in the present embodiment.

VBB1>GND, VPP1≦Vcc, VBB2≦GND, VPP2≧Vcc  (4)

[0076] By setting the bias voltages in this way, the threshold value of each transistor can be easily controlled. That is, since a bias supply circuit is installed to each substrate, the ion injection process in the above-described manufacture process can be simplified.

[0077] Such bias voltages VBB1, VBB2, VPP1, and VPP2 can be supplied using a conventional bias supply circuit. For example, the bias supply circuits disclosed in the Japanese Patent Application Laid-Open No. H2-350, the Japanese Patent Application Laid-Open No. 62-178013, and the Japanese Patent Application Laid-Open No. 61-64148 can be used.

[0078] By setting the threshold value of each transistor in this manner, highly sensitive operation is guaranteed for the analog circuit, and the leak current and through current in the logic circuit can be reduced.

[0079] According to the present invention, highly sensitive operation is guaranteed for the analog circuit, and the leak current and through current in the logic circuit can be reduced. If the present invention is applied to low voltage operation semiconductor integral circuits that are driven using cells such as batteries or the like as a power source, the life of the cells can be extended.

[0080] So far, the present invention has been explained using embodiments. However, the range of technical applications of the present invention is not limited to these embodiments. Other variations and modifications of the above-described embodiments should be evident to those skilled in the art. Accordingly, it is intended that such alterations and modifications be included within the scope and spirit of the present invention as defined by the following claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7866798 *Sep 2, 2008Jan 11, 2011Canon Kabushiki KaishaHead cartridge, printhead, and substrate having downsized level conversion elements that suppress power consumption
Classifications
U.S. Classification327/333
International ClassificationH01L21/42, H03K5/08, H01L21/822, H01L21/8234, H03M1/34, H01L27/088, H01L27/04, H03K19/0948, H01L21/265, G06G7/25
Cooperative ClassificationG06G7/25
European ClassificationG06G7/25