Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20020012158 A1
Publication typeApplication
Application numberUS 09/961,499
Publication dateJan 31, 2002
Filing dateSep 25, 2001
Priority dateOct 29, 1999
Also published asDE60017172D1, DE60017172T2, EP1224504A1, EP1224504B1, EP1515183A1, US6348991, US6388798, WO2001033293A1
Publication number09961499, 961499, US 2002/0012158 A1, US 2002/012158 A1, US 20020012158 A1, US 20020012158A1, US 2002012158 A1, US 2002012158A1, US-A1-20020012158, US-A1-2002012158, US2002/0012158A1, US2002/012158A1, US20020012158 A1, US20020012158A1, US2002012158 A1, US2002012158A1
InventorsRonald Smith, Kannan Raj
Original AssigneeSmith Ronald D., Kannan Raj
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Integrated circuit with opposed spatial light modulator and processor
US 20020012158 A1
Abstract
An integrated circuit may have a spatial light modulator formed on one side of a semiconductor support and a microprocessor formed on the opposite side. The microprocessor and the spatial light modulator may communicate with one another through electrical connections which extend completely through the semiconductor support. The microprocessor may be contacted using bump packaging techniques.
Images(3)
Previous page
Next page
Claims(26)
What is claimed is:
1. An integrated circuit comprising:
a support having opposed sides;
a spatial light modulator formed on one side of said support;
a processor formed on the opposite side of said support; and
a conductor electrically coupling said modulator and said processor through said support.
2. The circuit of claim 1 wherein said spatial light modulator is formed using liquid crystal on silicon technology.
3. The circuit of claim 1 wherein said support is formed of a semiconductor material.
4. The circuit of claim 1 wherein said support is formed of a n electrical insulator.
5. The circuit of claim 1 wherein said integrated circuit includes a plurality of conductors formed as di electric insulated vias which extend from one opposed side to the other opposed side of said support.
6. The circuit of claim 1 including an external heat sink coupled to one of said sides of said support.
7. The circuit of claim 1 including a plurality of conductive vias which extend through said support, a plurality of mirror pads in said modulator and a plurality of conductive pads in said processor, each of said vias contacting a mirror pad in said spatial light modulator on one side of said support, and a metal pad on the other side of said support.
8. The circuit of claim 1 including a plurality of solder bumps on said processor for making electrical contact to external devices.
9. The circuit of claim 1 including a transparent conductive layer and a liquid crystal layer, an electrical contact being formed through said spatial light modulator to said conductive layer.
10. The circuit of claim 1 including a hole formed completely through said support forming a tubular wall, a dielectric layer formed on said wall and a conductive layer formed within said hole such that said dielectric layer is sandwiched between said conductive layer and said support, a mirror pad being formed in electrical contact with said conductive layer, said mirror pad forming part of said spatial light modulator.
11. The circuit of claim 1 wherein capacitors are formed from insulated, metallic vias which extend completely through said support.
12. The circuit of claim 11 wherein one of said vias is a solid metallic plug.
13. An integrated circuit comprising:
a die having opposed sides;
a spatial light modulator formed on one side of said die;
a processor formed on the opposite side of said die; and
an insulated conductor extending from one opposed side to the other opposed side and forming a capacitor for said spatial light modulator.
14. The circuit of claim 13 wherein said integrated circuit includes a plurality of conductors formed as dielectric insulated vias which extend from one opposed side to the other opposed side of said die.
15. The circuit of claim 13 including a plurality of metal vias which extend through said die, a plurality of mirror pads in said modulator and a plurality of conductive pads in said processor, each of said vias electrically contacting a mirror pad in said spatial light modulator, on one side of said die, and a conductive pad on the other side of said die.
16. The circuit of claim 13 including a hole formed completely through said die forming a tubular wall, a dielectric layer formed on said wall and a metallic layer formed within said hole such that said dielectric layer is sandwiched between said metallic layer and said die, a mirror pad being formed over said metallic layer, said mirror pad forming part of said spatial light modulator.
17. The circuit of claim 13 wherein the support includes a semiconductor.
18. The circuit of claim 13 wherein the support includes an insulator.
19. A method comprising:
forming a microprocessor on one side of an integrated circuit die;
forming a spatial light modulator on the opposite side of said integrated circuit die; and
electrically coupling said modulator and said processor through said die.
20. The method of claim 19 wherein electrically coupling includes forming holes which extend completely through said die.
21. The method of claim 20 including forming said holes through said die by forming a first hole on one side of said die and a second hole that joins said first hole, said second hole being formed from the other side of said die.
22. The method of claim 20 including insulating said holes.
23. The method of claim 22 including forming conductors in said holes and electrically coupling said conductors to act as capacitors for said spatial light modulator.
24. The method of claim 20 including forming insulated conductive vias which couple a metal layer in said microprocessor with the mirror pads of the spatial light modulator.
25. The method of claim 20 including forming a conductive coating in said holes.
26. The method of claim 20 including filling said holes with conductive material.
Description
BACKGROUND

[0001] This invention relates generally to spatial light modulators and to microprocessors.

[0002] There is an increasing demand for relatively compact digital displays for a wide variety of electronic devices. For example, cellular telephones and a variety of other appliances have a need for a relatively compact display and in some cases an entire device may be sufficiently compact to be handheld. These devices have processor-based systems for running a variety of applications as well as the display. Conventionally, a printed circuit board is utilized to organize a variety of integrated circuit chips to implement the processor and the circuitry for a spatial light modulator. This tends to spread the size of the device laterally increasing the minimum possible device size.

[0003] A number of emerging display technologies make it possible to provide relatively compact displays. For example, reflective light valves may be based on liquid crystal on silicon (LCOS) technology to merge mature silicon technology with liquid crystal optics technology. Micro displays as are used in handheld mobile phones and rear projection displays for personal computers and home entertainment are applications of hybrid reflective light modulator technology. In addition, grating light valves from Silicon Light Machine and the Digital Micro-Mirror Device (DMMD) from Texas Instruments may also be used to create displays.

[0004] The spatial light modulator modulates the optical properties of a medium to allow an image to be displayed when the medium is exposed to light. The nature of the spatial light modulator is essentially inconsistent with the nature of the microprocessor. The microprocessor is an entirely silicon device and can be formed on a die and packaged with a variety of different contacts for connecting to the outside world. The spatial light modulator involves the use of a liquid crystal layer which is confined between a pair of spaced plates. Conventionally, the requirements for packaging liquid crystal based devices and microprocessors have been considered to be substantially different.

[0005] Thus, there is a continuing need for ways to better integrate microprocessors and spatial light modulators to achieve processor-based systems with more compact display arrangements.

SUMMARY

[0006] In accordance with one aspect, an integrated circuit includes a support having opposed sides. A spatial light modulator is formed on one side of the support. A processor is formed on the opposite side of the support. A conductor electrically couples the modulator and the processor through the support.

[0007] Other aspects are set forth in the accompanying detailed description and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is an enlarged cross-sectional view of a semiconductor support which has been etched to form an array of trenches on the top side of the support;

[0009]FIG. 2 is an enlarged cross-sectional view after the trenches formed in FIG. 1 have been oxidized;

[0010]FIG. 3 is an enlarged cross-sectional view after the oxidized trenches shown in FIG. 2 have been metallized and covered with interlayer dielectric and metallization layers;

[0011]FIG. 4 is an enlarged cross-sectional view of the support shown in FIG. 3 after the support has been penetrated to form a plurality of holes which extend completely through the support;

[0012]FIG. 5 is an enlarged cross-sectional view of the embodiment shown in FIG. 4 after the traversing holes have been oxidized;

[0013]FIG. 6 is an enlarged cross-sectional view of the embodiment shown in FIG. 5 after the holes have been metallized;

[0014]FIG. 7 is an enlarged cross-sectional view of the embodiment shown in FIG. 6 after the metallized holes have been surface metallized and polished; and

[0015]FIG. 8 is an enlarged cross-sectional view of the finished integrated circuit in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION

[0016] An integrated circuit may include a spatial light modulator on one surface and a microprocessor on an opposite surface. The spatial light modulator and the microprocessor may be electrically coupled by one or more conductive interconnections that extend completely through the integrated circuit.

[0017] Referring to FIG. 1, initially a support 10 may be etched to form a plurality of discrete holes or trenches 12 on the top side 13 of the support 10. The support 10, in one embodiment of the present invention, may be formed by a P-type silicon semiconductor substrate. Alternatively, the support may include sapphire, for example in a semiconductor over insulator (SOI) technology.

[0018] The trenches 12 may be oxidized to form an oxide 14, as shown in FIG. 2. The trenches 12 that have now been oxidized, may be relatively deep trenches extending a substantial distance through the support 10. For example, the trenches 12 may extend, after oxidation, through more than half the thickness of the support 10 from the top side 13 to the back side 11. Alternatively, the oxide 14 may be deposited. As still another alternative, a dielectric such as silicon nitride may be used in place of the oxide 14.

[0019] The trenches 12 may be covered by a layer of metallization which forms the so-called metal one metallization as indicated at 16 in FIG. 3. The metal one metallization 16 may be covered by an interlayer dielectric (ILD) and additional metallization layers 18. The additional metallization layers may include second, third and fourth or even higher layers of metallization with intervening dielectric layers. The metallization layers may implement the desired structure and function for a conventional microprocessor.

[0020] Thereafter, trenches 20 are formed from the back side 11 of the support 10 to mate up with the array of trenches 12 previously formed in the top side 13. As a result, the holes or trenches 20 extend completely through the support 10. The trenches 20 may be formed by chemical or laser ablation from the back side 11. Advantageously, they do not adversely affect the metal one layer 16.

[0021] Thereafter, the exposed surfaces of the trench 20 are oxidized to form a trench oxide 14 which covers the interior surface of the trench 20. The oxide 14 may also be a deposited oxide. In addition, other dielectric materials such as silicon nitride may be deposited in place of or in addition to oxide. The trenches may be formed in a circular cross-sectional shape, in one embodiment of the invention.

[0022] Next, as shown in FIG. 6, the trenches 20 may be metallized, as indicated at 24, to form conductive vias 24 that extend from the top side 13 through to the back side 11 of the support 10. At the top side 13, the conductive vias 24 electrically contact the metal one layer 16 and on the bottom the vias electrically contact the mirror pads 26. A variety of conventional materials may be utilized to form the vias 24 including aluminum, copper and gold. In addition, it may be possible to use other conductive materials such as silicides. Instead of forming the vias 24 by a coating process, the vias 24 may be formed of a solid conductive plug substantially filling the trenches 20.

[0023] Thereafter, the backside 11 is metallized and a plurality of metal pads 26 are patterned and defined. The metal pads 26 form the so-called metal zero layer or mirror pads for the spatial light modulator. The metal pads 26 may be formed using liquid crystal over silicon (LCOS) technology. An alignment layer 28 may be formed over the mirror pads 26. The alignment layer 28 may be formed, for example, of an indium tin oxide. A liquid crystal material 30 is sandwiched between an alignment layer 32 coated on a transparent top plate 34 and the layer 28. The layer 32 may also be formed of indium tin oxide. Spacers (not shown) may be provided between the alignment layer 28 and the top plate 34 to maintain the desired spacing.

[0024] A heat sink 36 may be peripherally secured to the support 10 to remove heat generated by the microprocessor and/or the spatial light modulator without interfering with photon access, indicated by double arrows, to the modulator. An electrical contact 38 may be provided to electrical couple to the alignment layers 32 and 28. A seal 40 may be provided to maintain the liquid crystal material 30 between the alignment layers 28 and 32.

[0025] The support 10 may be made of P-type silicon semiconductor material and N-plus type diffusions 50 may be formed between the metal interconnects 24. The diffusions 50 may form the transistors which control the operation of the spatial light modulator.

[0026] A plurality of metal contacts 42 may be patterned and defined on top of the microprocessor for allowing input and output connections to the microprocessor. In one embodiment of the invention the contacts 42 may be formed from a metal five metallization layer. In one embodiment of the present invention, solder balls or bumps 44 may be utilized to implement a flip chip type package that couples the microprocessor inputs and outputs to a printed circuit board 46. The bumps 44 may also implement the input/output connections for the spatial light modulator through the vias 24. In another embodiment, a tape automated bonding (TAB) system may be used in place of the bumps 44.

[0027] The mirror pads 26 define the mirrors for the spatial light modulator. Potentials applied to the liquid crystal material 30 modulates the incoming light to create images. These images can be directly viewed or projected onto a projection screen. Commonly, the metal pads 26 may be rectangular or square and together form a rectangular array of mirrors. The mirror array may define an array of pixel elements in conjunction with the liquid crystal material positioned over the mirrors. The transmissivity of the liquid crystal material 30 may be controlled by the LCOS active elements formed in the support 10.

[0028] Since both sides of a die or support 10 may be utilized, some embodiments may increase the utilization of a single silicon die. In addition, the microprocessor and the spatial light modulator may be positioned in close juxtaposition. Pixel storage capacitors, that normally consume the bulk of the area in silicon liquid crystal device backplane displays, are naturally formed by the metal vias 24 and the mirror pads 26 over oxide 14 b on the back side 13. This may reduce the need for large electrical devices and may allow for additional pixel plane processing transistors or the integration of other functions, such as a graphics display control or processor functions. Some embodiments may be particularly amenable for use in micro displays and rear projection displays, by making the optical system very compact, both in frame sequential and multi-channel applications.

[0029] When an insulator is used to form the support 10, it is unnecessary to insulate the conductive vias 24 using an oxide or other insulative layer.

[0030] While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6814445 *Jul 1, 2002Nov 9, 2004Texas Instruments IncorporatedDMD heat sink socket assembly
US6897148Apr 9, 2003May 24, 2005Tru-Si Technologies, Inc.Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby
US7521360Oct 10, 2006Apr 21, 2009Tru-Si Technologies, Inc.Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby
Classifications
U.S. Classification359/290, 359/292, 359/291
International ClassificationG02F1/13, G02F1/1333, G02F1/1362, G02F1/1345, H01L27/15
Cooperative ClassificationG02F2201/42, G02F1/13452, G02F1/13454, G02F1/1333, G02F1/136277, G02F1/1345, G02F1/136213
European ClassificationG02F1/1345D, G02F1/1345E, G02F1/1345, G02F1/1362C, G02F1/1333
Legal Events
DateCodeEventDescription
Oct 16, 2013FPAYFee payment
Year of fee payment: 12
Nov 12, 2009FPAYFee payment
Year of fee payment: 8
Nov 14, 2005FPAYFee payment
Year of fee payment: 4