BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to micro-gyroscope in particular to surface/bulk micromachined single-crystalline silicon micro-gyroscopes.
2. Description of the Related Art
Microelectromechanical systems include component structures with typical minimum dimensions on the order of a micron where the component structures can have elaborate shapes and perform a variety of complex functions. The component structures of microelectromechanical systems are formed on a semiconductor or glass substrate. Microelectromechanical systems include devices such as accelerometers that sense the acceleration of a moving object, gyroscopes that sense the angular rate of a rotating object and mirror arrays that deflect light in fiber optic communication and display applications. Micromachining techniques are used to fabricate the very small structures that are integrated with electrical parts on the semiconductor or glass substrate. The techniques used to fabricate these microelectromechanical systems are largely based on semiconductor device fabricating technology, including photolithography, thin film deposition, etching, impurity doping by diffusion and ion implantation, electroplating and wafer bonding.
Micro-gyroscopes for measuring the rate and/or angle of rotation have received much attention. Application areas include navigation systems, automotive safety and stability control systems, video camera stabilization, and 3-D input devices for computers and personal data assistance (PDA) systems.
Gyroscope measures the rate and/or angle of rotation by a Coriolis force which is generated at from a vibrating part. Structure of a gyroscope basically has a mass for driving the vibrating part and a mass for sensing the motion generated by the Coriolis force, which are respectively supported by springs. These springs should be aligned with each other at a 90° angle. A micro-gyroscope includes electrodes that are electrically isolated to allow, for example, to measure electrical signals flowing in the sensing part of the system. Other example of electrodes are used to apply electrical signals to the vibrating parts of the system. Groscopes with separate sets of suspensions for the driving and sensing mode are called “decoupled” gyroscope. It is well known that the resolution of a coupled gyroscope is relatively lower than that of a decoupled gyroscope, because of the cross-axis mode coupling.
Firstly, conventional various micro-gyroscopes are explained as follows.
Researchers at the Charles Stark Draper Laboratory demonstrated one of the first silicon gyroscopes in 1991, using the p++ etch stop technique, and a resolution of 4°/sec was achieved with a 1 Hz bandwidth as discussed in P. Greiff, B. Boxenhom, T. King, and L. Niles, “Silicon monolithic micromechanical gyroscope,” in Tech. Dig. 6th Int. Conf. Solid-State Sensors and Actuators (Transducers '91), San Francisco, Calif., June 1991, pp. 966-968. In 1996, researchers at Berkeley reported a surface micromachined polysilicon gyroscope integrated with a transresistance amplifier on a single die as discussed in W. A. Clark, R. T. Howe, and R. Horowitz, “Surface micromachined z-axis vibratory rate gyroscope,” in Tech. Dig. Solid-State Sensor & Actuator Workshop, Hilton Head Island, S.C., June 1996, pp. 299-302. This device was fabricated by the Analog Devices BiMEMS process, and showed a resolution of 1°/sec with a 1 Hz bandwidth.
To achieve an improved resolution, increasing the thickness of structures and using single-crystalline silicon as a structural material have been an active research topic in more recent years. High-aspect-ratio structures (HARS) provide a large lateral capacitance, which in turn, allows realizing high-sensitivity sensors or high-force actuators. Furthermore, a reduced cross-axis coupling is possible with HARS. Since the availability of deep silicon etchers, many process techniques for fabricating HARS have been developed as discussed in K. A. Shaw, Z. L. Zhang, and N. C. MacDonald, “SCREAM I: a single mask, single-crystal silicon, reactive ion etching process for microelectromechanical structures,” Sensors and Actuators A, vol. 40, pp. 63-70, 1994. Other HARS fabrication methods are discussed in J. Muchow, H. Muenzel, M. Offenberg, W. Waldvogel, “Method of fabricating a micromechanical sensor,” U.S. Pat. No. 5, 616, 514, Apr. 1997 and B. Diem, M. T. Delaye, F. Michel, S. Renard, and G. Delapoerre, “SOI(SIMOX) as a substrate for surface micromachining of single crystalline silicon sensors and actuators,” in Tech. Dig. 7th Int. Conf Solid-State Sensors and Actuators (Transducers'93), Yokohama, Japan, June 1993, pp. 233-236.
In 1997, researchers at HSG-IMIT reported a 10 □-thick, x-axis gyroscope using epitaxially-grown polysilicon as a structural material as discussed in W. Geiger, B. Folkmer, J. Merz, H. Sandmaier, and W. Lang, “A new silicon rate gyroscope,” in Proc. IEEE Workshop on Microelectromech. Syst. (MEMS'98), Heidelberg, Germany, February 1998, pp. 615-620. The device showed a 0.096% sec resolution with a 50 Hz bandwidth. Researchers at Samsung also reported a gyroscope using the SOI(Silicon on Insulator) process which showed a resolution of 0.015% sec with a 25 Hz bandwidth as discussed in K. Y. Park, H. S. Jeong, S. An, S. H. Shin, and C. W. Lee, “Lateral gyroscope suspended by two gimbals through high aspect ratio ICP etching,” in Tech. Dig. 10th Int. Conf Solid-State Sensors and Actuators (Transducers'99), Sendai, Japan, June 1999, pp. 972-975 and an other gyroscope using an anodically bonded wafer which showed a resolution of 0.01°/sec at a 5 Hz angular-rate input as discussed in S. S. Baek, Y. S. Oh, B. J. Ha, S. D. An, B. H. An, H. Song, and C. M. Song, “A symmetrical z-axis gyroscope with a high aspect ratio using simple and new process,” in Proc. IEEE Workshop on Microelectromech. Syst. (MEMS'99), Orlando, Fla., Jan. 1999, pp. 612-617.
The epi-poly process utilizes a polycrystalline-phase film for the structural material, and similar to the LPCVD polysilicon films, it can have problems of residual stress or stress gradient. In the SOI process, the structural material is single-crystalline silicon, but the high cost of wafers and the residual stress resulting from the bonding process are the main disadvantages. Furthermore, the sacrificial gap thickness is limited by the buried oxide layer thickness. Another major drawback of the SOI and epi-poly processes is the footing effect. An uncontrollable undercutting phenomenon occurs at the boundary between silicon and oxide layer in deep RIE processes. The footing effect can significantly alter the stiffness properties and reduce reproducibility.
As a new alternative of silicon HARS micromachining techniques, D. Cho et al. have developed the single-wafer Surface/Bulk Micromachining (SBM) technology as discussed in S. Lee, S. Park, and D. Cho, “A new micromachining technique with (111) silicon,” Japanese Journal of Applied Physics, vol. 38, pp. 2699-2703, May 1999; S. Park, S. Lee, S. Yi, and D. Cho, “Mesa-supported, single-crystal microstructures fabricated by the surface/bulk micromachining (SBM) process”, Japanese Journal of Applied Physics, vol. 38, pp. 4244-4249, July 1999. S. Lee, S. Park, and D. Cho; “The surface/bulk micromachining (SBM) process: a new method for fabricating released microelectromechanical systems in single crystal silicon,” IEEE/ASME J. Microelctromech. Syst., vol. 8, no. 4, pp. 409-416, Dec. 1999; S. Lee, S. Park, and D. Cho, “Surface/bulk micromachining (SBM) process and deep trench oxide isolation method for MEMS,” in Tech. Dig. IEEE Electron Devices Meeting (IEDM'99), Washington, D.C., December 1999, pp. 701-704; and D. Cho, S. Lee, S. Park, “Micromachanical System Fabrication Method Using (111) Single Crystalline Silicon,” U.S. Pat. No. 6,150,275, November 2000. The SBM technology can fabricate released structures of single-crystalline silicon without using the intermediate oxide layer or wafer bonding. In addition, the footing phenomenon does not occur in this process.
Secondly, conventional isolation methods used in a micromechanical system are as follows.
FIG. 1 shows process steps in the conventional isolation process known as the single crystalline reactive etching and metallization (SCREAM) process. The SCREAM isolation process is performed on a structure fabricated by the SCREAM micromachining technique in the manner discussed in U.S. Pat. Nos. 5,563,343; 5,198,390; and K. A. Shaw, Z. L. Zhang, and N. C. MacDonald, “SCREAM I: A Single Mask, Single-Crystal Silicon, Reactive Ion Etching Process for Microelectromechanical Structures,” Sensors and Actuators A, Vol. 40, pp. 63, 1994. Plasma enhanced chemical vapor deposition (PECVD) covers all surfaces of a micromachined structure with an oxide film. Selective deposition of metal film on the structure forms electrodes and electrically conducting paths on top of the PECVD oxide film so that the PECVD oxide film separates the electrodes from the silicon substrate. In this SCREAM process, electrical isolation of the electrodes is achieved by depositing the metal film only on the top and the side surfaces of microelectromechanical structures that are covered by the PECVD oxide film.
The SCREAM isolation process has the advantage of being relatively simple in not requiring separate photolithography and etching steps once the structure is fabricated using the SCREAM micromachining technique. On the other hand, the coverage achieved in the deposition of the metal film is generally poor and hence the SCREAM isolation process typically cannot be applied. to tall structures having a high aspect ratio. It should be noted that, if a metal or other material is deposited that has good step coverage, such as metal films deposited by low pressure chemical vapor deposition (LPCVD), all electrodes and microelectromechanical parts are electrically connected, and hence, electrical isolation is not achieved.
FIG. 2 shows the silicon on oxide insulator (SOI) wafer method, used in forming the microelectromechanical systems described in the following references: B. Diem, et al., “SOI(SIMOX) as a Substrate for Surface Micromachining of Single Crystalline Silicon Sensors and Actuators,” Tech. Dig. 7th Int. Conf Solid-State Sensors and Actuators (Transducers '93), Yokohama, Japan, 1993, pp. 233-236; and C. Marxer, et al., “Vertical Mirrors Fabricated by Deep Reactive Ion Etching for Fiber-Optic Switching Applications,” IEEE/ASME Journal of Microelectromechanical Systems, Vol. 6, No. 3, pp. September 1997. In the SOI wafer method, the portion of the wafer on top of the buried oxide layer (device layer) is highly doped, conducting silicon. Since all structures and electrodes are fabricated in the device layer and are defined by etching the device layer down to the buried oxide layer, electrical isolation of the resulting electrodes is achieved automatically. On the other hand, SOI wafers are generally expensive and the residual stress created by the buried oxide layer can warp and change the shape of microelectromechanical structures made on the device layer. In addition, the micromachined portions of the device layer silicon near the oxide interface can have roughened features (produced by the “footing” effect) when the structures and electrodes are formed in a deep plasma etching process. Another disadvantage of the SOI process is that the as-manufactured wafer has an established thickness of the oxide film and the device layer and these thicknesses cannot be modified once a wafer is manufactured.
FIG. 3 shows a scanning electron microscope (SEM) photograph of a micromachined comb-drive structure fabricated from single crystal silicon. The electrodes of the illustrated comb-drive structure are isolated using the junction isolation method. The junction isolation method is described, for example, in S. Lee, S. Park and D. Cho, “The Surface/Bulk Micromachining (SBM) Process: A New Method for Fabricating Released Microelectromechanical Systems in Single Crystal Silicon,” IEEE/ASME J. Microelectromechanical Systems, Vol. 8, No. 4, December 1999. The junction isolation method forms a junction diode on a lightly doped N-type or P-type wafer. Applying a reverse biased voltage to the junction diode isolates the junction electrode from the substrate. Referring to FIG. 3, the silicon substrate is lightly doped P-type and the lighter parts, including the comb-drive structure, are highly doped N-type with phosphorus, so that a PN junction between the silicon substrate (P-type) and the electrode (N-type) is formed. In this case, if a reverse bias voltage is applied to the PN junction, the electrodes are electrically isolated from the silicon substrate. This method has the advantage that the isolation steps are done before the micromechanical structure is fabricated, so that the structure can be fabricated in a relatively easy manner and with relatively little of the stress created by the isolation method. On the other hand, the method has disadvantage that the depth of the PN junction often cannot be made sufficiently deep, so that this process usually is not readily applied to a tall structure having a high aspect ratio.
FIG. 4 is a structure formed by yet another conventional isolation method, the trench oxide isolation method, described in the following references: U.S. Pat. No. 5,930,595; U. Sridhar et al., “Trench Oxide Isolated Single Crystal Silicon Micromachined Accelerometer,” IEEE IEDM, San Francisco Calif., Dec. 6-9, 1998. pp. 475-478; and S. Lee, S. Park, D. Cho and Y. Oh “Surface/Bulk Micromachining (SBM) Process and Deep Trench Oxide Isolation Method for MEMS”, IEEE IEDM, Washington, D.C., December 5-8, 1999. pp.701-704. This trench isolation method includes forming U-shaped trenches 14 on a silicon substrate 16, forming thermal oxide layers 18 and depositing oxide layers 20 on all sides of the structure where the trenches are formed. The oxide films 18, 20 filling the trenches attach the electrode structures 22, 24 to the silicon substrate 16 through the respective sidewalls so that the oxide films support the electrodes and tethered structures. The oxide films electrically isolate the electrodes from each other and from the substrate.
This trench isolation method has the advantage that the method can be applied to a tall structure having a high aspect ratio. On the other hand, separate photolithography and etching steps are required to form a metal layer on the electrode to allow wire bonding the electrode to a package. Two different release processes are required: one to separate the electrode component from the substrate and a second to separate the structure part from the substrate. The trenches between the sidewalls of the electrode and the sidewalls of the substrate generally cannot be made arbitrarily large, as would be desired to achieve a small parasitic capacitance, without sacrificing the structural rigidity of the trench filled oxide layers that support the structure and electrodes. Additionally, the conventional trench isolation method deposits the insulation layers on the sides of the electrode to support the structure and electrodes. Therefore, the electrode and the substrate need to be supported by means other than the insulating layers during manufacturing, which limits the electrode shapes that can be made. In particular, it is difficult to fabricate an electrode in an “island” shape or in a complicated electrode arrangement like that used in a micro-gyroscope. Those skilled in the art can appreciate the need for a simpler isolation method.
FIG. 5 illustrates aspects of a surface/bulk micromachining technique, as described in co-pending U.S. patent application Ser. No. 09/756,981, filed Jan. 9, 2001 and entitled “Isolation Micromachined Single Crystal Using Deep Trench Insulation,” which patent application is hereby incorporated by reference in its entirety. This application describes an alternate strategy for electrically isolating microstructures. It should be noted that the present triple layer isolation can be used in conjunction with the isolation strategy described in the above-referenced surface/bulk micromachining application.
FIG. 5 shows an isolation process employing a deep trench insulation layer. First, a trench deeper than the thickness of the electrode to be formed is etched at an intermediate position of the electrode to be formed on a single crystalline silicon substrate. The trench is filled with an insulation material such as silicon oxide. The moving structure and the electrode portion 51 are then released and separated from the silicon substrate. As shown in FIG. 5, the oxide or other insulation is stripped from the surface of the silicon workpiece. The process then forms a mask on the surface of the workpiece establishing the lateral extents of the electrodes to be formed. Deep etching proceeds deeper than the height of the electrode. The sidewalls of the electrode are passivated and then the trenches are etched deeper to expose sidewalls beneath the electrodes. Lateral release etching is conducted to form the electrode structures. Finally, metal is sputtered over the electrodes to make them more conductive so that contacts can readily be formed.
The insulation layer 52 filled in the deep trench is fixed in the silicon substrate and supports the electrode portion from the interior of the electrode. According to the process illustrated in FIG. 5, the insulation material filled in the deep trench is fixed to the silicon substrate and passes through the interior of the electrode to support the electrode. Consequently, an insulation layer is not necessary on the side of the electrode. Therefore, electrodes having an “island” shape and separated from the silicon substrate on all sides can be formed. This process has the advantage that the metal layer is vapor-deposited on the electrode structure and the electrode structure is formed in a single release process. The metal layer can be formed without separate photolithography and etching processes. The process illustrated in FIG. 5, however, cannot be applied to a microstructure having high aspect ratio features.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to single-crystalline-silicon, single-wafer gyroscope fabricated using a new isolation method.
The new isolation method includes providing a microstructure comprising silicon, the microstructure having at least one released surface opposite and spaced from an underlying surface of a substrate comprising silicon. An insulation layer is formed over surfaces of the microstructure, including over the released surface, a conductive layer is formed over surfaces of the insulation layer, and a metal layer is formed over at least a top surface of the conductive layer on at least a portion of the microstructure.
Another preferred isolation method forms an insulation layer on the exposed surfaces of a microstructure after the microstructure has been formed by micromachining and released from the surface of an underlying substrate. The isolation method forms a conductive layer over the entire insulation layer and forms a metal layer over the conductive layer on top portions of the microstructure. Partially etching of the conductive layer forms electrical isolation between parts of the microstructure.
The conductive layer preferably may be a heavily-doped polycrystalline silicon layer having good step coverage formed by low pressure chemical vapor deposition (“LPCVD”). Etching of the conductive layer preferably may be accomplished by anisotropic dry etching. The insulation layer preferably may be a thermal oxide layer formed on the surface of a preferred single crystalline silicon by thermal oxidization. Alternatively, the insulation layer may be an oxide layer or a nitride layer formed by plasma enhanced chemical vapor deposition (“PECVD”) or LPCVD having good step coverage, or a composite insulation layer of a thermal oxide layer, an LPCVD oxide layer, an LPVCD nitride layer, a PECVD oxide layer and/or a PECVD nitride layer. Other insulators are apparent.
Another aspect of the invention provides a silicon microstructure having released structures and a layer structure for electrically isolating portions of the silicon microstructure. The layer structure comprises an insulation layer formed over released surfaces of the silicon microstructure, a conductive layer formed over the insulation layer including over sidewalls of the released structures, conductive layer having gaps electrically isolating portions of the silicon microstructure, and a metal layer formed over portions of the released structures.
An aspect for the present invention provides a micro-gyroscope comprising of oxide/polysilicon/metal triple layer for electrical isolation, in which the polysilicon layer is partially etched to accomplish the electrical isolation in the microstructure of the micro-gyroscope. The thickness of the layers also serve to compensate for the undercutting phenomenon inherent in deep silicon reactive ice etching (“RIE”), which can alter the stiffness characteristics.
An aspect of the present invention provides a micro-gyroscope fabricated by an isolation method which dose not require a separate photolithography process for isolation, there for can be applied to microstructures having high aspect ratios and narrow trenches.
An aspect of the present invention provides a micro-gyroscope comprising a new type of spring which has a node with a hole in the middle of spring to reduce the release etch time for spring.