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Publication numberUS20020017647 A1
Publication typeApplication
Application numberUS 09/915,584
Publication dateFeb 14, 2002
Filing dateJul 27, 2001
Priority dateJan 21, 1997
Also published asDE69805982D1, EP0968549A1, EP0968549B1, US5853298, WO1998043322A1
Publication number09915584, 915584, US 2002/0017647 A1, US 2002/017647 A1, US 20020017647 A1, US 20020017647A1, US 2002017647 A1, US 2002017647A1, US-A1-20020017647, US-A1-2002017647, US2002/0017647A1, US2002/017647A1, US20020017647 A1, US20020017647A1, US2002017647 A1, US2002017647A1
InventorsMietek Bakowski, Ulf Gustafsson, Christopher Harris
Original AssigneeMietek Bakowski, Ulf Gustafsson, Harris Christopher I.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Junction termination for SiC schottky diode
US 20020017647 A1
Abstract
A semiconductor diode structure comprising a Schottky junction, where a metal contact and a silicon carbide semiconducting layer of a first conducting type form said junction and where the edge of the junction exhibits a Junction Termination Extension (JTE) laterally surrounding the junction, said JTE having a charge profile with a stepwise or uniformly decreasing total charge or effective sheet charge density from an initial value to a zero or almost zero total charge at the outermost edge of the termination following a radial direction from the centre part of the JTE towards the outermost edge of the termination. The object of the junction termination extension is to control the electric field at the periphery of the diode.
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Claims(11)
1. A semiconductor device comprising a first conducting type layer (9) and a metal contact layer (2) forming a Schottky junction, where the first conducting type layer is made of silicon carbide (SiC), characterized in that said first conducting type layer (9) is immersed into a second lower doped first conducting type layer (7), whereby said junction is provided with a Junction Termination Extension (JTE).
2. A semiconductor device according to claim 1, characterized in that the first conducting type layer (9) of the Schottky junction is formed as a trench (8) in the second layer (7) of the first conducting type.
3. A semiconductor device according to claim 1, characterized in that the first conducting type layer (9) is formed as a region established by ion implantation into the second layer (7) of the first conducting type.
4. A semiconductor device according to claim 1, characterized in that said second layer (7) of the first conducting type is a top layer of a highly doped substrate of the first conducting type.
5. A semiconductor device according to claim 1, characterized in that the first conducting type layer of the Schottky junction is formed as a MESA (10) on top of a higher doped layer (6) of the first conducting type.
6. A semiconductor device according to claim 5, characterized in that a lower doped second layer (11) of the first conducting type surrounds the MESA formed first conducting type Schottky junction layer (10).
7. A semiconductor device according to claim 6, characterized in that the metal contact (8) is applied to the MESA formed first conducting type Schottky junction layer (10) through an aperture in the second layer (11) of the first conducting type.
8. Method of manufacturing a semiconductor component comprising a first conducting type layer (9) and a metal contact layer (2) forming a Schottky junction, where the first conducting type layer is made of silicon carbide (SiC), the edge of the Schottky junction to be provided with a termination extension, comprising the steps of:
etching a trench (8) at a surface of a silicon carbide wafer (6, 7) having a lower doped layer (7) of the first conducting type SiC material at said surface,
epitaxially growing an n-base region (9) in said trench (8) with a first conducting type material being of higher doping concentration than said lower doped layer (7),
applying a metal contact layer to the surface of said n-base region (9) for forming said metal Schottky contact (2).
9. Method of manufacturing a semiconductor component comprising a first conducting type layer (9) and a metal contact layer (2) forming a Schottky junction, where the first conducting type layer is made of silicon carbide (SiC), the edge of the Schottky junction to be provided with a termination extension, comprising the steps of:
implanting ions into a region of a surface of a silicon carbide wafer (6, 7) having a lower doped layer (7) of the first conducting type SiC material at said surface for
creating an n-base region (9) having a first conducting type material being of higher doping concentration than said lower doped layer (7),
applying a metal contact layer on the surface of said n-base region (9) for forming said metal Schottky contact (2).
10. Method of manufacturing a semiconductor component comprising a first conducting type layer (10) and a metal contact layer (2) forming a Schottky junction, where the first conducting type layer is made of silicon carbide (SiC), the edge of the Schottky junction to be provided with a termination extension, comprising the steps of:
epitaxially growing on a surface of a highly doped first conducting type silicon carbide wafer (6) a first SiC layer of the first conductive type having a doping concentration lower than the doping concentration of said wafer (6),
etching said first layer for forming an n-base region (10) as a MESA structure of the remainder of said first layer, epitaxially growing an edge layer (11) of the first conductive type SiC material having a lower doping concentration than said n-base region (10) around said n-base region,
etching a window in said edge layer (11) down to said n-base region (10), and
applying a metal contact layer on the surface of said n-base region (9) for forming said metal Schottky contact (2).
11. Method according to claim 8 or 9, characterized in that the implant used to form the n-base surrounding layer (9) of n-conducting type material is nitrogen.
Description
TECHNICAL FIELD

[0001] The invention is related to a metal-semiconductor junction device, known as a Schottky diode semiconductor device, with silicon carbide as base material, where the risk of voltage breakdown due to a strong electric field at the edge of the junction, i. e. the contact surface between the metal and a contacting semiconducting layer, is reduced as the junction contains an edge termination with a decreasing charge or charge density of the semiconductor layer surrounding the metal contact in a direction away from the junction.

BACKGROUND ART

[0002] Semiconductor devices based on silicon carbide as base material are continuously developed to be used in connection with high temperatures, high power applications and under high radiation conditions. Under such circumstances conventional semiconductors do not work satisfactorily. Evaluations indicate that SiC semiconductors of power MOSFET-type and diode rectifiers based on SiC would be able to operate over a greater voltage and temperature interval, e.g. up to 650-800° C., and show better switching properties such as lower losses and higher working frequencies and nevertheless have a volume 20 times smaller than corresponding silicon devices. These possible improvements are based on the favourable material properties that silicon carbide possesses in relation to silicon, such e.g. a higher breakdown field (up to 10 times higher than silicon), a higher thermal conductivity (more than 3 times higher than silicon) and a higher energy band gap (2.9 eV for 6H—SiC, one of the crystal structures of SiC).

[0003] As SiC semiconductor technology is relatively young and in many aspects immature, there are many critical manufacturing problems which are to be solved until SiC semiconductor devices may be realized experimentally and manufacturing in a large number may become a reality. This is especially true of devices intended for use in high-power and high-voltage applications.

[0004] One of the difficulties to overcome when manufacturing high voltage diodes or other types of semiconductor devices comprising a voltage absorbing pn junction is to produce a proper junction termination at the edge of the junction. The electric field at the periphery of the junction is normally enhanced compared to the electric field in the bulk of the junction. This field increase at the periphery of the junction may be further reinforced in the presence of surface charge.

[0005] A high electric field at the edge of the pn junction implies a great risk of voltage breakdown or flash-over at the edge of the junction and gives an instability of blocking voltage known as voltage drift.

[0006] To avoid the above-mentioned disadvantages it becomes very important to reduce the field concentration, where the junction reaches the surface. Combined with efforts to passivate the surface of the component, measures are taken to flatten out the electric field at the surface e.g. by acting on how the pn junction emerges at the surface. As an example it is known from silicon power components to lap (grind, sandblast, etch) the surface of the edge to a certain angle in relation to the pn junction to thereby flatten out the field. Another known technique is to gradually decrease the doping on the highly doped side of the junction, such that the doping is reduced towards the outermost edge of the junction (so called Junction Termination Extension, JTE). The methods, known from silicon technology, used to achieve a JTE of an Si component are difficult or almost impossible to apply to components based on silicon carbide due to the great hardness of the material and extremely low diffusivity of proper SiC dopants.

[0007] The above-mentioned problems have not been solved for pn junctions in SiC. Many of the problems to be solved when developing semiconductor devices from SiC are reminiscent of those prevalent at the beginning of the development of corresponding silicon components. Yet, the same techniques as hose applicable to silicon cannot be utilized when solving the specific problems related to production of SiC semiconductor devices. As an example, doping through diffusion is not feasible for SiC, as diffusion coefficients are negligible below 2270° K. Also, ion implantation of doping elements, a common technique when manufacturing Si components, is difficult to master and not yet fully developed for SiC.

[0008] Solutions for arriving at SiC components comprising pn junctions with JTEs are described in patent application U.S. Ser. No. 08/520,689 not yet published, which is hereby included in this description by reference. This application discloses MESA structure pn junctions having Junction Termination Extensions. A junction termination for a Schottky diode is disclosed in document JP, A, 06268202. The component of thsi JP document has an insulating film with an aperture for an active Schottky layer. Still, this solution is not sufficient to solve the problem with too high electric field concentration at the edge of the junction.

[0009] Junction termination using gradually diminishing doping on the highly doped side of the pn-junction at the periphery of the pn junction is an effective way to secure blocking capability for high voltage semiconcuctors. JTE techniques for SIC pn junctions have been described for mesa-structures in the above-mentioned patent application U.S. Ser. No. 08/520,689. The solutions described there involve stepwise decreasing charges of the JTE towards the edge of the JTE by use of an etch-down technique, epitaxial regrowth or ion implatation in order to control the surface doping and surface fields.

[0010] Junction terminations (JT) for high voltage Schottky diodes present an extra challenge in an effort to reach high voltage levels for said device compared to the JT for so-called PIN-diodes where a normal pn junction is provided with a high-doped p-layer, a high-doped n-layer and in between an intermediate doped n-layer for voltage blocking purposes. There are two main reasons for that. First of all the electric field maximum determining the breakdown level is situated much closer to the semiconductor surface (FIG. 1a, point A) than in the case of the PIN diode. This entails much more severe stress to the interface between the SiC surface and a passivating and severe stress to a passivating insulator layer itself during voltage blocking by the diode. A second reason is that compared to the PIN diode (FIG. 1b) provided with a JTE, there is one extra region where the crowding of the potential lines and high electric field have to be avoided. This region is at the transition between the Schottky (metal) contact and a Junction Termination area (FIG. 1c, point B), where it is illustrated that although efforts have been made by means of a resistive JTE to reduce the field maximum at the edge of the Schottky junction, thus displacing the field maximum laterally outwards to point A at the edge of the space charge region, another point B with a field maximum has appeared.

[0011] Several methods to control the electric field at the surface of the Schottky diodes have been published during the last couple of years. Most of the known methods are concerned, however, with the problem related to the electric field enhancement at point A, indicated above. This problem is identical with that encountered in all bipolar devices as well. Solutions to the problem are discussed and solved

[0012] by the use of field rings in M. Bhatnagar, P. K. Mc Larty, and B. J. Baliga, IEEE Electron Device Letter, 13, 501 (1992),

[0013] by the use of the effect of damage and doping on the effective surface charge in D. Alok, B. J. Baliga, M. Kothandaraman and P. K. Mc Larty, Proc of 6th Silicon Carbide and Related Materials Conf., Inst. Phys., Ser. 142, 565 (1995),

[0014] in A. Itoh, T. Kimoto, and H. Matsunami, Proc of 6th 6th Silicon Carbide and Related Materials Conf., Inst. Phys. Ser. 142, 689 (1995)

[0015] in T. Kimoto, T. Urushidani, S. Kobayashi and H. Matsunami, IEEE Electron Device Lett., 14, 548, (1993)

[0016] by the use of JTE termination techniques in D. Stephani, Abstracts of 1st European Conf. Silicon Carbide and Rel. Materials, 92 (1996).

[0017] Only the use of the LOCOS oxidation technique in K. Ueno, T. Urushidani, K Hashimoto and Y Seki, Proc. of 7th Int. Symp. Power Semicond. Devices and Ics, 107 (1995) is devoted to controlling the electric field enhancement at point B and is here referred to as the only prior art document adressing this problem together with other techniques known from the field of silicon devices such as the use of an oxide field plate and the use of a field ring described in Baliga, Modern Power Devices. John Wiley & sons, p 437 (1985).

[0018] The proper termination of the Schottky diode junction has to be constructed in such a way that both field enhancements in points A and B are controlled at the same time so that none of them is dominating and alone determines the behaviour of the diode at a high voltage blocking voltage applied to it.

[0019] It is a general property of the Schottky diode and as such distinct from any bipolar diode that the field enhancement at point B will always persist when known JT methods like an implanted field ring of a directly applied JTE of the type described in above mentioned patent application U.S. Ser. No. 08/520,689 are used. This is due to the fact that metal replacing one side of the pn junction in the Schottky diode does not create a space charge absorbing some of the potential and the electric field. This makes the transition between the Schottky contact area abrupt causing a field enhancement as discussed.

[0020] In the following a number of methods to realize a component as charactized in the device claims are disclosed.

[0021] The term SiC is used in the following text to refer to any of the principal crystal polytypes of this material known as 6H, 4H, 2H, 3C and 15R.

SUMMARY OF THE INVENTION

[0022] One aspect of the invention is composed of a semiconductor diode structure, which comprises a Schottky junction, where a metal contact and a silicon carbide semiconducting layer of a first conducting type form said junction and where the edge of the junction exhibits a Junction Termination Extension (JTE) laterally surrounding the junction, said JTE having a charge profile with a stepwise or uniformly decreasing total charge or effective sheet charge density from an initial value to a zero or almost zero total charge at the outermost edge of the termination following a radial direction from the centre part of the JTE towards the outermost edge of the termination. The purpose of the junction termination extension is to control the electric field at the periphery of the diode.

[0023] Other aspects of the invention further comprise methods for producing said SiC semiconductor component with said decreasing charge profile defined by the method claims.

[0024] By manufacturing an SiC Schottky diode with the features described, the concentration of the electric field, when a high reverse voltage is applied to the junction, is eliminated as the electric field is flattened out along the extended edge termination. A low electric field in the lateral direction is achieved. Hence, the risk of a voltage breakdown at the edge of the junction before a breakdown somewhere at the metal contact area of the junction is reduced. By forming the edges of a Schottky junction of SiC material according to the aspects of the invention the reverse voltage across the junction may be considerably increased (3 times and more) before a breakdown occurs.

[0025] Furthermore, the reliability and long term stability are improved. This is due to the reduction of the electric field in the SiC material at the periphery of the junction. The maximum surface electric field must be reduced by at least one order of magnitude as long as the passivation schemes known from Si technology are used. Taking the measures disclosed relieves the stress inflicted on the passivation and isolation of the junction.

[0026] A low lateral electric field at an interface between a JT surface to a passivation layer is vital to a proper function of the JT. Unnecessary electric field peaks may be detrimental to the short- and long-term stability of the component. Hence, one purpose of the invention is to establish a component with a metal-SiC Schottky junction where electric field peaks between zones of different charge contents of the JT are reduced to a minimum.

[0027] The SiC semiconductor component is manufactured according to the invention by means of one of the alternative methods described below which have in common that the metal contact is applied on top of an n-base region implanted into a lower doped n-substrate, grown epitaxially in a lower doped n-substrate or grown epitaxially on top of a high-doped n-substrate, said n-base being surrounded by an n-region having lower doping concentration where this surrounding n-regiopn acts as said junction termination.

[0028] According to a method 1° for achieving a junction termination for a Schottky diode, an n-base region is epitaxially regrown on top of a low-doped n substrate. This low-doped n substrate forms a top layer on a high-doped n+ layer of the substrate. The n-base region is grown in a truncated V-trench etched in the low-doped n substrate layer. The metal Schottky contact is then applied to the n-base layer by covering the surface of the filled trench with said metal contact. The n-base region is thus surrounded by an n substrate region with lower doping concentration, whereby the surrounding n layer acts as a Junction Termination.

[0029] As an alternative, according to a second method 2°, the n-base region can become established by means of implantation of ions into the low-doped n substrate layer, the implanted layer thus forming said n-base layer contacting the metal Schottky contact.

[0030] An alternative to method 1° is possible by use of a method 3°, where the n-base is achieved by an etching step performed on an n layer, which is earlier epitaxially grown on top of an n+ substrate, such that a MESA n layer is formed on top of the n+ substrate. All around the MESA structure an n layer is epitaxially grown. By etching a window in the n epitaxial layer down to the n base, a trench is obtained. The surfaces of said trench is then covered by a metal contact layer forming the Schottky contact. The n region of the n epitaxial layer forming the walls around the metal covered trench then acts as a junction termination as said trench surrounding n region has a lower doping concentration than the n-base contacting the metal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031]FIG. 1a schematically describes a section through a Schottky junction pointing out the maximum electric field at the edge of the space charge region with no junction termination.

[0032]FIG. 1b schematically describes a section through a p-i-n diode junction pointing out the maximum electric field at the edge of the space charge region with a stepped down Junction Termination.

[0033]FIG. 1c schematically shows a section through a Schottky junction with a resistive junction termination, where two maximum electric field points are indicated.

[0034]FIG. 2 depicts a junction termination around the edges of a metal Schottky contact applied on an implanted or epitaxially grown n-base region, where the metal contacts said n-base region having a higher doping than a Schottky contact surrounding layer of the same conductivity type with a lower doping.

[0035]FIG. 3 shows a junction termination around the edges of a metal Schottky contact applied on an n-base region epitaxially grown on a substrate, where the metal contacts said n-base region by means of a trench etched in a lower doped layer epitaxially grown on and around said n-base.

DESCRIPTION OF EMBODIMENTS

[0036] The invention will be described in a number of embodiments with reference to the drawings.

[0037] In prior art junction terminations as shown in FIGS. 1a and 1 c, M denotes a metal contact forming one contact of a Schottky junction. As for FIG. 1b, M denotes a contact layer of a pin-diode. A passivation layer, for example consisting of SiO2, is covering the unshielded area outside the edge of the respective junctions. SCR denotes the space charge region of the depleted junction. The letter R of FIG. 1c symbolises a resistive layer functioning as a junction termination. The dots denoted by Emax indicate points where the electric field is concentrated.

[0038] An embodiment of the invention is described referring to FIG. 2. A first method, 1°, for realising a component according to one aspect of the invention is described at the same time. The component of FIG. 2 is built on a substrate of SiC consisting of a highly doped n-conducting layer 6 forming a cathode of the diode. On top of this layer 6 a second layer 7 of a weakly doped n-conducting type SiC material has been epitaxially grown, whereby these layers 6 and 7 form a wafer. A truncated V-trench 8 is then etched into said second n-conducting layer 7. An n-base region 9 formed by an n-conducting type material is epitaxially grown into the trench 8 such the trench is completely filled by said n-base material. The doping concentration of this n-base region 9 material is of a level between the doping concentrations of the high-doped substrate layer 6 and the concentration of the second n-conducting layer 7. A metal Schottky contact 2 is then applied to the n-base layer 9 by covering the surface of the n-base 9 with said metal contact 2. The n-base region is in this way surrounded by an n substrate region with lower doping concentration, whereby the surrounding n layer acts as a junction termination extension exhibiting lower charge contents laterally than the n-base junction layer 9 in the direction outwards from the metal contact region.

[0039] The component of FIG. 2 may, as an alternative, be arrived, at by another method, 2°, where the same steps are performed as those described under method 1°, with the exception that the n-base layer 9 is achieved by means of an implantation step, where ions, e. g. nitrogen, are implanted into a region 8 of the second n-conducting low-doped layer 7. By use of this method it is not necessary to etch a trench 8 and also to omit the following epitaxially grown n-base layer 9 as described in method 1°.

[0040] According to a further method 3°, the invention may also be arrived at as the alternative depicted in FIG. 3, where the component is built on a substrate of SiC consisting of a highly doped n-conducting layer 6 forming the cathode of the diode. A MESA layer 10 for forming an n-base region of an n-type SiC material is then epitaxially grown on top of the substrate 6. Another layer, a MESA edge layer 11 consisting of a lowly doped n-conducting type SiC-material is epitaxially grown all around and above the MESA structure 10. A truncated trench 8 is etched down in the MESA edge layer 11 in the same way as in method 1° as well as the application of a metal contact region in the trench for forming the Schottky contact 2. The MESA edge layer 11 region of the n epitaxial layer forming the walls around the metal covered trench 8 then acts as a junction termination extension as said trench surrounding n region has a lower doping concentration than the n-base contacting the metal contact 2.

[0041] The doping concentrations of all layers in a Schottky diode established according to any of methods 1°-3° determine the electric field concentrations and thus also the breakdown voltage of the diode.

[0042] Common for all alternatives of the junction described is a passivation layer 12 covering the semiconducting material facing the surface outside the metal contact 2. The passivation layer may, for example, be made of SiO2.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7675135Sep 12, 2005Mar 9, 2010Stmicroelectronics S.R.L.Integrated high voltage power device having an edge termination of enhanced effectiveness
US8026160 *May 9, 2006Sep 27, 2011Mitsubishi Electric CorporationSemiconductor device and semiconductor device manufacturing method
EP1635397A1Sep 14, 2004Mar 15, 2006STMicroelectronics S.r.l.Integrated high voltage power device having an edge termination of enhanced effectiveness
WO2006030467A1 *Sep 12, 2005Mar 23, 2006St Microelectronics SrlIntegrated high voltage power device having an edge termination of enhanced effectiveness
Classifications
U.S. Classification257/77, 257/480, 438/379, 438/105
International ClassificationH01R13/639, H01R13/627, H01L31/0312, H01L21/00
Cooperative ClassificationH01L29/417, H01L29/66143, H01L29/872, H01L29/1608
European ClassificationH01L29/66M6D2S, H01L29/16S, H01L29/872, H01L29/417
Legal Events
DateCodeEventDescription
Aug 11, 2003ASAssignment
Owner name: CREE, INC., NORTH CAROLINA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ABB RESEARCH LTD.;ABB AB;REEL/FRAME:014363/0376
Effective date: 20030703