US20020017672A1 - Low-capacitance bonding pad for semiconductor device - Google Patents
Low-capacitance bonding pad for semiconductor device Download PDFInfo
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- US20020017672A1 US20020017672A1 US09/329,648 US32964899A US2002017672A1 US 20020017672 A1 US20020017672 A1 US 20020017672A1 US 32964899 A US32964899 A US 32964899A US 2002017672 A1 US2002017672 A1 US 2002017672A1
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Definitions
- the present invention relates to a semiconductor device. More particularly, the present invention relates to a bonding pad with low capacitance for a semiconductor device.
- FIG. 1 is a cross-sectional view, schematically illustrating a conventional bonding pad.
- a dielectric layer 12 is formed on a substrate 10 , and a metal layer 14 is formed on the dielectric layer 12 .
- a passivation layer 16 having a bonding pad opening 18 is formed on the metal layer 14 .
- a bonding pad wire 19 is formed on the metal layer 14 within the bonding pad opening 18 .
- a parasitic capacitance of the bonding pad maybe small if the distance between the substrate 10 and the metal layer 14 is large. But if the bonding pad is only formed by the uppermost metal layer to increase the distance between the substrate 10 and the metal layer 14 , the peel-off effect, denoted as a region 17 , often occurs during formation of the bonding wire 19 and chip packaging. The bonding reliability is therefore reduced due to the peel-off effect.
- the present invention provides a low-capacitance bonding pad for a semiconductor device so as to avoid a peel-off effect and reduce a parasitic capacitance of the bonding pad.
- the invention provides a low-capacitance bonding pad for a semiconductor device.
- a diffusion region is formed in a substrate at a region on which a bonding pad is to be formed.
- the bonding pad includes a stacked metal layer and a metal layer, in which the metal layer is on the stacked metal layer.
- the stacked metal layer includes several metal layers and several dielectric layers, in which the metal layers are isolated by the dielectric layers in between by alternately stacking them up.
- the metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with an adjacent metal layer by a via plug.
- the bonding pad includes several metal layers and buried deeply in the dielectric layer, the peel-off effect is effectively avoided.
- An area of the substrate overlapped by the metal layers stacked in the stacked metal layer is small because the areas of the metal layers stacked in the stacked metal layer are small.
- the parasitic capacitance of the bonding pad is also effectively reduced.
- the parasitic capacitance of the bonding pad is further reduced due to the diffusion region in the substrate, which serves as an additional capacitor coupled in series to the capacitor induced by the metal layers.
- the metal layers in the stacked metal layer can include various geometry structures.
- the metal layer includes several metal bars in one layer and crosses to each other in different layer in different bar direction so as to form a geometric structure, such as a net structure or any other overlapping structure.
- the invention provides another low-capacitance bonding pad for a semiconductor device.
- a device is formed under a bonding pad which is made from a stacked metal layer and an uppermost metal layer.
- the metal layers stacked in the stacked metal layer are formed with small area and each area of the metal layer in the stacked metal layer is smaller than the uppermost metal layer.
- the device is formed on a substrate.
- Several metal layers close to the device serve as signal lines.
- Several metal layers stacked on the metal layers as signal lines serve as power lines, and other metal layers stacked on the power lines serve as the bonding pad which consists of a stacked metal layer and an uppermost metal layer.
- the metal layers in the stacked metal layer can include various geometry structures.
- the metal layer includes several metal bars in one layer and crosses to each other in different layer in different bar direction so as to form a geometric structure, such as a net structure or any other overlapping structure.
- the device is formed between the bonding pad and the substrate, an area of the integrated circuits layout is reduced.
- the area of the substrate overlapped by the metal layers stacked in the stacked metal layer is small since areas of the metal layers are small, so that the parasitic capacitance of the bonding pad is reduced.
- the peel-off effect is avoided and the bonding reliability increases because the bonding pad includes the stacked metal layers which are buried deeply in the dielectric layer.
- FIG. 1 is a schematic drawing, illustrating a cross-sectional view of a conventional bonding pad
- FIG. 2 is a schematic drawing, illustrating a top view of a bonding pad layout according to the invention
- FIG. 3 is a schematic drawing, illustrating a cross-sectional view of FIG. 2 taken along a line II-III;
- FIG. 4 is a schematic drawing, illustrating a cross-sectional view of FIG. 2 taken along a line IV-IV;
- FIG. 5 is a schematic drawing, illustrating a cross-sectional view of FIG. 2 taken along a line V-V;
- FIG. 6 is a schematic drawing, illustrating a cross-sectional view of FIG. 2 taken along a line VI-VI;
- FIG. 7 is another schematic drawing, illustrating a top view of a bonding pad layout according to the invention.
- FIG. 8 is a schematic drawing, illustrating a cross-sectional view of FIG. 7 taken along a line VIII-VIII;
- FIG. 9 is another schematic drawing, illustrating a top view of a bonding pad layout according to the invention.
- FIG. 10 is a schematic drawing, illustrating a cross-sectional view of FIG. 9 taken along a line X-X;
- FIG. 11 is another schematic drawing, illustrating a top view of a bonding pad layout according to the invention.
- FIG. 12 is a schematic drawing, illustrating a cross-sectional view of FIG. 11 taken along a line XII-XII;
- FIGS. 13 through 16 are schematic drawings, illustrating cross-sectional views of bonding pad layouts according to the invention.
- FIGS. 17 through 22 are schematic drawings, illustrating cross-sectional views of bonding pad layouts according to the invention.
- FIG. 23 is a schematic drawing, illustrating a cross-sectional view of a no ther bonding pad layout according to the invention.
- FIG. 2 is a schematic drawing, illustrating a top view of a bonding pad layout according to the invention.
- FIGS. 3, 4, 5 and 6 are schematic drawings, illustrating cross-sectional views of FIG. 2 taken along lines III-III, IV-IV, V-V and VI-VI, respectively.
- a p-type substrate 200 having an n-well 202 is provided.
- a p-type doped region 204 is formed as a diffusion region in the n-well 202 .
- a bonding pad includes a stacked metal layer 208 and a metal layer 250 lies located on the p-type substrate 200 and is aligned with the p-type doped region 204 .
- the stacked metal layer 208 includes several metal layers 210 , 220 , 230 , 240 and several dielectric layers 212 , 222 , 232 , 242 , 252 .
- the metal layers 210 , 220 , 230 , 240 and the dielectric layers 212 , 222 , 232 , 242 , 252 are stacked alternately on the p-type substrate 200 .
- the metal layer 250 is formed on the dielectric layer 252 .
- a junction capacitance C p occurs between the n-well 202 and the p-type doped region 204 .
- a junction capacitance C N occurs between the n-well 202 and the p-type substrate 200 .
- a total equivalent capacitance C Meq also occurs due to contribution from the metal layers 210 , 220 , 230 , 240 , 250 . All the capacitance of C P , C N , and C Meq are coupled in series so that a parasitic capacitance of the bonding pad is effectively reduced.
- the metal layers 210 , 220 , 230 , and 240 are all designed, for example, to have a bar structures in this embodiment but the metal layer 250 is a planar layer.
- Each width of the metal layers 210 , 220 , 230 and 240 is designed to be as small as possible, so that an area of the p-type substrate 200 overlapped by the metal layers 210 , 220 , 230 and 240 is reduced. This is significantly helpful to reduce the parasitic capacitance of the bonding pad.
- the metal layers 210 and 240 are parallel to a row direction 400 shown in FIG. 2, and the metal layer 240 is aligned with the metal layer 210 . Additionally, the metal layers 220 and 230 are parallel to a column direction 300 shown in FIG. 2 and perpendicular to the row direction 400 . Similarly, the metal layer 230 is aligned with the metal layer 220 . As a result, the metal layers 210 and 240 are shown as a layer structure in FIG. 4 but not shown in FIG. 3 due to the different cross-sectional line III-III. In FIGS. 5 and 6, the metal layers 210 and 240 are shown like bars which are not connected to each other, and the metal layer 210 is aligned with the metal layer 240 .
- the metal layers 220 and 230 are shown as bars in FIG. 6 and not shown in FIG. 5.
- the metal layers 220 and 230 are shown as bars that are not connected to each other, and the metal layer 230 is aligned with the metal layer 220 .
- a layout of the metal layers 210 , 220 , 230 and 240 resembles a mesh or a net as shown in FIG. 2.
- each of the metal layers 210 , 220 , 230 , 240 and 250 are connected with the adjacent metal layers by via plugs 214 , 224 , 234 , 244 in the dielectric layers 222 , 232 , 242 , and 252 .
- the via plugs are alternately positioned in the adjacent dielectric layers 222 , 232 , 242 , and 252 so as to achieve a uniform distribution of the via plugs 214 , 224 , 234 , 244 .
- the via plug 244 is not aligned with the via plug 234 as shown in FIG. 4.
- the via plug 234 and the via plug 224 are not aligned and the via plug 224 and the via plug 214 are also not aligned as shown in FIG. 2.
- This structure can effectively avoid the peel-off effect due to a uniform stress.
- the via plug 224 connecting the metal layers 220 and 230 is only shown in FIGS. 3 and 6.
- the via plug 214 connecting the metal layers 210 and 220 and the via plug 234 connecting the metal layers 230 and 240 are only shown in FIGS. 4 and 6 due to different cross-sectional views.
- the via plug 244 connecting the metal layers 240 and 250 is only shown in FIGS. 4 and 5.
- the via plug 214 is aligned with the via plug 234 and is not aligned with the via plugs 224 and 244 , as shown in FIGS. 4 and 6.
- a passivation layer 262 is formed on the metal layer 250 with a bonding pad opening 270 used for a subsequent bonding process.
- the bonding pad according to the invention includes the stacked metal layer 208 and the metal layer 250 .
- the peel-off effect is effectively avoided by this structure.
- the area of the p-type substrate 200 overlapped by the metal layers 210 , 220 , 230 and 240 is decreased by about 50% comparing with the conventional bonding pad.
- the junction capacitance C P between the n-well 202 and the p-type doped region 204 , the junction capacitance C N between the n-well 202 and the p-type substrate 200 and the total equivalent capacitance C Meq between the substrate 200 and the metal layers 210 , 220 , 230 , 240 , 250 are series connected.
- the parasitic capacitance of the bonding pad is about 50% less than that of the conventional bonding pad.
- a layout of the metal layers 210 , 220 , 230 and 240 mentioned above is not the only way to reduce the area of the p-type substrate 200 overlapped by the metal layers 210 , 220 , 230 and 240 according to the invention.
- FIG. 7 is a top view of a portion of a substrate, schematically illustrating a bonding pad layout according to the invention
- FIG. 8 is a cross-sectional view, schematically illustrating the bonding pad taken along a line VIII-VIII of FIG. 7.
- the metal layers are referred in numerals 710 , 720 , 730 , 740 and 750 .
- Each of the metal layers 710 , 720 , 730 and 740 are designed as a bar, and the metal layer 750 is a planar layer.
- the metal layers 710 , 720 , 730 and 740 are aligned with each other and are isolated by several dielectric layers 212 , 222 , 232 , 242 in between.
- a top dielectric layer 252 covers the metal layer 740 .
- the metal layer 750 is located on the dielectric layer 252 . Additionally, a direction of the metal layers 710 , 720 , 730 and 740 deviates from the direction 400 (FIG. 2) with an angle, which preferably is 45 degrees in this embodiment.
- each of the metal layers 710 , 720 , 730 , 740 and 750 are coupled with the adjacent metal layers by via plugs 714 , 724 , 734 , 744 in the dielectric layers 212 , 222 , 232 , 242 .
- Positions of the via plugs are not aligned for two adjacent layers. In this manner, the via plug 714 and the via plug 724 are not aligned, the via plug 724 and the via plug 734 are not aligned, and also the via plug 734 and the via plug 744 are not aligned.
- the via plug 714 and the via plug 734 may be aligned and the via plug 724 and the via plug 744 may be aligned.
- the position of the via plug 724 connecting the metal layers 720 and 730 is not superimposed on the position of the via plug 714 used to connect the metal layers 710 and 720 as shown in FIG. 8.
- the position of the via plug 734 connecting the metal layers 730 and 740 is not superimposed on the position of the via plug 724 .
- the via plug 734 is aligned with the via plug 714
- the via plug 744 is aligned with the via plug 724 .
- FIGS. 9 and 11 are top views of a portion of a substrate, schematically illustrating another two bonding pad layouts according to the invention, and FIGS. 10 and 12 are cross-sectional views, schematically illustrating the bonding pad layouts respectively taken along lines X-X and XII-XII in FIGS. 9 and FIGS. 10.
- a layout of the metal layers in FIG. 9 includes, for example, several concentric circles, and a layout of the metal layers in FIG. 11 is concentric polygons, such as squares.
- the metal layers are referred in numerals 910 , 920 , 930 , 940 and 950 .
- Each of the metal layers 910 , 920 , 930 and 940 are designed as concentric circles, and the metal layer 950 is a planar layer.
- the metal layers 910 , 920 , 930 and 940 are aligned with each other, and each of the metal layers 910 , 920 , 930 , 940 , 950 are coupled by via plugs 914 , 924 , 934 , 944 , which are formed in several isolation layers, such as the dielectric layers 212 , 222 , 232 , 242 , 252 as shown in the previous examples.
- the via plugs 914 , 924 , 934 , 944 are alternately distributed for the two adjacent layers.
- the design concept of this layout is the same as the previous designs.
- the metal layers are referred to by numerals 1110 , 1120 , 1130 , 1140 and 1150 .
- the metal layers 1110 , 1120 , 1130 and 1140 are designed as concentric squares, and the metal layer 1150 is a plane.
- the metal layers 1110 , 1120 , 1130 and 1140 are aligned with each other, and each of the metal layers 1110 , 1120 , 1130 , 1140 and 1150 are coupled with the adjacent metal layers by via plugs 1114 , 1124 , 1134 and 1144 .
- the design concept of this layout is the same as the previous designs.
- FIGS. 13, 14, 15 and 16 are top views of a portion of a substrate, schematically illustrating other bonding pad layouts for the metal layers 210 , 220 , 230 and 240 according to the invention.
- Layouts of the metal layers in FIGS. 13, 14, 15 and 16 respectively are concentric pentagons, concentric hexagons, concentric heptagons and concentric octagons.
- the design concept of these layouts is the same as the previous examples. According to the concept, other kinds of polygons are also acceptable in the invention.
- the layouts of the metal layers 210 , 220 , 230 and 240 resemble meshes.
- the layout shown in FIG. 17 is a honeycombed type mesh
- the layout shown in FIG. 18 is a mesh composed of adjacent octagonal units arranged in rows.
- the mesh in the invention comprises a mesh composed of a unit shape as seen in FIGS. 17 and 18.
- a mesh composed of various unit shapes is suitable for the invention.
- the layout of the metal layers 210 , 220 , 230 and 240 is a mesh composed of rows of pentagonal structures connected by a line, with each pentagonal unit connected to the pentagon in the row above or below by a line.
- Each unit shape of the mesh is changed to a heptagon, an octagon and a circle in FIGS. 20, 21 and 22 , respectively.
- other kinds of polygons are acceptable.
- the bonding pad is not formed above an active device region or circuit region because a subsequent bonding wire process could damage the formed device.
- the bonding pad of the invention include a top metal layer 250 of FIG. 4 and the stacked metal layer 208 .
- the bonding pad opening 270 can be adjusted at the location above the device region. As a result, the available substrate surface can be more efficiently used.
- FIG. 23 is a cross-sectional view, schematically illustrating a bonding pad layout with a device, according to the invention.
- devices are formed on the substrate just under the bonding pad.
- a device 32 such as a field effect transistor, is formed on a substrate 30 .
- Metal layers 51 , 52 , 53 , 54 , 55 and 56 are formed in a dielectric layer 60 over the device 32 , in which the dielectric layer 60 serves as an isolation and a frame to stack the metal layers 51 , 52 , 53 , 54 , 55 , 56 .
- the dielectric layer 60 can also further include several sub-layers to hold and isolate the metal layers.
- a bonding pad includes the metal layers 55 and 56 and is covered by the a passivation layer 80 .
- the passivation layer 80 includes a bonding pad opening 82 , which exposes a portion of the metal layer 56 .
- the metal layers 51 and 52 near the substrate 30 are used to serve as, for example, signal lines, and the metal layers 53 and 54 are designed to be planar layers and used to serve as, for example, power lines.
- a passivation layer 80 is formed on a dielectric layer 60 , and the bonding pad opening 82 is formed in the passivation layer 80 to expose the metal layer 56 .
- a bonding wire 84 is attached to the metal layer 56 within the bonding pad opening 84 .
- Each pair of the metal layers 51 , 52 , 53 , 54 , 55 and 56 is isolated by the dielectric layer 60 .
- the metal layers 55 , 56 are coupled by a via plug 75 and the metal layers 51 , 52 are coupled by a via plug 71 .
- the metal layers 52 , 53 and 54 serving as signal lines and power lines are also coupled by via plugs (not shown), and the metal layers 54 and 55 are similar. However, these via plugs should not be formed under the bonding pad opening 82 .
- the metal layers 53 , 54 can be used to be the buffer layers, and the bonding stress borne on the active devices can be reduced through these buffer layers.
- the device 32 such as a CMOS device, is formed on the substrate 30 or an n-well 34 in the substrate 30 .
- the metal layer 56 is a plane, and the metal layer 55 is designed as applying one of the layouts shown in example 1 for the metal layer 55 so that the parasitic capacitance and the bonding reliability of the bonding pad are effectively reduced and increased, respectively.
- the bonding pad in the invention is formed by multiple metal layers and buried deeply in the dielectric layer, so that the peel-off effect is avoided and the bonding reliability effectively increases.
- the overlapping area of between the substrate and the metal layers is greatly reduced.
- the parasitic capacitance of the bonding pad is reduced.
- a diffusion region is formed in the substrate so that the contact capacitance of the diffusion region and the capacitance of the bonding pad are connected in series. The parasitic capacitance of the bonding pad is reduced.
- the invention is compatible with the current conventional processes. Only the layout design of the bonding pad is changed to meet the requirement of a semiconductor device. Manufactures can achieve the bonding pad structure of the invention without modifying their fabrication processes.
- the device can be formed under the bonding pad so that the substrate surface is more efficiently used for compact circuit layout.
Abstract
A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.
Description
- This application claims the priority benefit of Taiwan application serial no. 88104304, filed Mar. 19, 1999, the full disclosure of which is incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a semiconductor device. More particularly, the present invention relates to a bonding pad with low capacitance for a semiconductor device.
- 2. Description of the Related Art
- Trends for electrical products are light, short, small, and thin. Usually, the chips manufacturing technology and the packaging technology are rapidly developed to meet these trends. However, due to a limitation of bonding machines, a size of a bonding pad for a semiconductor device is not reduced as well as a line width of a chip is greatly reduced. Because the size of the bonding pad is insufficiently small, an area of a substrate overlapped by the bonding pad is large. As a result, a parasitic capacitance of the bonding pad remains high. Additionally, a peel-off effect often occurs while forming the bonding wire, so that bonding reliability is decreased.
- FIG. 1 is a cross-sectional view, schematically illustrating a conventional bonding pad.
- Referring to FIG. 1, a
dielectric layer 12 is formed on asubstrate 10, and ametal layer 14 is formed on thedielectric layer 12. Apassivation layer 16 having a bonding pad opening 18 is formed on themetal layer 14. Abonding pad wire 19 is formed on themetal layer 14 within the bonding pad opening 18. A parasitic capacitance of the bonding pad maybe small if the distance between thesubstrate 10 and themetal layer 14 is large. But if the bonding pad is only formed by the uppermost metal layer to increase the distance between thesubstrate 10 and themetal layer 14, the peel-off effect, denoted as aregion 17, often occurs during formation of thebonding wire 19 and chip packaging. The bonding reliability is therefore reduced due to the peel-off effect. - The present invention provides a low-capacitance bonding pad for a semiconductor device so as to avoid a peel-off effect and reduce a parasitic capacitance of the bonding pad.
- To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate at a region on which a bonding pad is to be formed. The bonding pad includes a stacked metal layer and a metal layer, in which the metal layer is on the stacked metal layer. The stacked metal layer includes several metal layers and several dielectric layers, in which the metal layers are isolated by the dielectric layers in between by alternately stacking them up. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with an adjacent metal layer by a via plug.
- Since the bonding pad includes several metal layers and buried deeply in the dielectric layer, the peel-off effect is effectively avoided. An area of the substrate overlapped by the metal layers stacked in the stacked metal layer is small because the areas of the metal layers stacked in the stacked metal layer are small. As a result, the parasitic capacitance of the bonding pad is also effectively reduced. Moreover, the parasitic capacitance of the bonding pad is further reduced due to the diffusion region in the substrate, which serves as an additional capacitor coupled in series to the capacitor induced by the metal layers. The metal layers in the stacked metal layer can include various geometry structures. For example, the metal layer includes several metal bars in one layer and crosses to each other in different layer in different bar direction so as to form a geometric structure, such as a net structure or any other overlapping structure.
- To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides another low-capacitance bonding pad for a semiconductor device. A device is formed under a bonding pad which is made from a stacked metal layer and an uppermost metal layer. The metal layers stacked in the stacked metal layer are formed with small area and each area of the metal layer in the stacked metal layer is smaller than the uppermost metal layer.
- The device is formed on a substrate. Several metal layers close to the device serve as signal lines. Several metal layers stacked on the metal layers as signal lines serve as power lines, and other metal layers stacked on the power lines serve as the bonding pad which consists of a stacked metal layer and an uppermost metal layer. The metal layers in the stacked metal layer can include various geometry structures. For example, the metal layer includes several metal bars in one layer and crosses to each other in different layer in different bar direction so as to form a geometric structure, such as a net structure or any other overlapping structure.
- Because the device is formed between the bonding pad and the substrate, an area of the integrated circuits layout is reduced. The area of the substrate overlapped by the metal layers stacked in the stacked metal layer is small since areas of the metal layers are small, so that the parasitic capacitance of the bonding pad is reduced. The peel-off effect is avoided and the bonding reliability increases because the bonding pad includes the stacked metal layers which are buried deeply in the dielectric layer.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
- FIG. 1 is a schematic drawing, illustrating a cross-sectional view of a conventional bonding pad;
- FIG. 2 is a schematic drawing, illustrating a top view of a bonding pad layout according to the invention;
- FIG. 3 is a schematic drawing, illustrating a cross-sectional view of FIG. 2 taken along a line II-III;
- FIG. 4 is a schematic drawing, illustrating a cross-sectional view of FIG. 2 taken along a line IV-IV;
- FIG. 5 is a schematic drawing, illustrating a cross-sectional view of FIG. 2 taken along a line V-V;
- FIG. 6 is a schematic drawing, illustrating a cross-sectional view of FIG. 2 taken along a line VI-VI;
- FIG. 7 is another schematic drawing, illustrating a top view of a bonding pad layout according to the invention;
- FIG. 8 is a schematic drawing, illustrating a cross-sectional view of FIG. 7 taken along a line VIII-VIII;
- FIG. 9 is another schematic drawing, illustrating a top view of a bonding pad layout according to the invention;
- FIG. 10 is a schematic drawing, illustrating a cross-sectional view of FIG. 9 taken along a line X-X;
- FIG. 11 is another schematic drawing, illustrating a top view of a bonding pad layout according to the invention;
- FIG. 12 is a schematic drawing, illustrating a cross-sectional view of FIG. 11 taken along a line XII-XII;
- FIGS. 13 through 16 are schematic drawings, illustrating cross-sectional views of bonding pad layouts according to the invention;
- FIGS. 17 through 22 are schematic drawings, illustrating cross-sectional views of bonding pad layouts according to the invention; and
- FIG. 23 is a schematic drawing, illustrating a cross-sectional view of a no ther bonding pad layout according to the invention.
- Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
- FIG. 2 is a schematic drawing, illustrating a top view of a bonding pad layout according to the invention. FIGS. 3, 4,5 and 6 are schematic drawings, illustrating cross-sectional views of FIG. 2 taken along lines III-III, IV-IV, V-V and VI-VI, respectively.
- Referring to FIGS. 2 and 4, a p-
type substrate 200 having an n-well 202 is provided. A p-type dopedregion 204 is formed as a diffusion region in the n-well 202. A bonding pad includes a stackedmetal layer 208 and ametal layer 250 lies located on the p-type substrate 200 and is aligned with the p-type dopedregion 204. The stackedmetal layer 208 includesseveral metal layers dielectric layers dielectric layers type substrate 200. Themetal layer 250 is formed on thedielectric layer 252. In this structure as described above, a junction capacitance Cp occurs between the n-well 202 and the p-type dopedregion 204. A junction capacitance CN occurs between the n-well 202 and the p-type substrate 200. A total equivalent capacitance CMeq also occurs due to contribution from the metal layers 210, 220, 230, 240, 250. All the capacitance of CP, CN, and CMeq are coupled in series so that a parasitic capacitance of the bonding pad is effectively reduced. - The metal layers210, 220, 230, and 240 are all designed, for example, to have a bar structures in this embodiment but the
metal layer 250 is a planar layer. Each width of the metal layers 210, 220, 230 and 240 is designed to be as small as possible, so that an area of the p-type substrate 200 overlapped by the metal layers 210, 220, 230 and 240 is reduced. This is significantly helpful to reduce the parasitic capacitance of the bonding pad. - The metal layers210 and 240 are parallel to a
row direction 400 shown in FIG. 2, and themetal layer 240 is aligned with themetal layer 210. Additionally, the metal layers 220 and 230 are parallel to acolumn direction 300 shown in FIG. 2 and perpendicular to therow direction 400. Similarly, themetal layer 230 is aligned with themetal layer 220. As a result, the metal layers 210 and 240 are shown as a layer structure in FIG. 4 but not shown in FIG. 3 due to the different cross-sectional line III-III. In FIGS. 5 and 6, the metal layers 210 and 240 are shown like bars which are not connected to each other, and themetal layer 210 is aligned with themetal layer 240. Similarly, the metal layers 220 and 230 are shown as bars in FIG. 6 and not shown in FIG. 5. In FIGS. 3 and 4, the metal layers 220 and 230 are shown as bars that are not connected to each other, and themetal layer 230 is aligned with themetal layer 220. A layout of the metal layers 210, 220, 230 and 240 resembles a mesh or a net as shown in FIG. 2. - In the invention, each of the metal layers210, 220, 230, 240 and 250 are connected with the adjacent metal layers by via
plugs dielectric layers dielectric layers plug 244 is not aligned with the viaplug 234 as shown in FIG. 4. Similarly, the viaplug 234 and the viaplug 224 are not aligned and the viaplug 224 and the viaplug 214 are also not aligned as shown in FIG. 2. This structure can effectively avoid the peel-off effect due to a uniform stress. The viaplug 224 connecting the metal layers 220 and 230 is only shown in FIGS. 3 and 6. The viaplug 214 connecting the metal layers 210 and 220 and the viaplug 234 connecting the metal layers 230 and 240 are only shown in FIGS. 4 and 6 due to different cross-sectional views. The viaplug 244 connecting the metal layers 240 and 250 is only shown in FIGS. 4 and 5. Furthermore, the viaplug 214 is aligned with the viaplug 234 and is not aligned with the via plugs 224 and 244, as shown in FIGS. 4 and 6. - A
passivation layer 262 is formed on themetal layer 250 with abonding pad opening 270 used for a subsequent bonding process. - The bonding pad according to the invention includes the stacked
metal layer 208 and themetal layer 250. The peel-off effect is effectively avoided by this structure. The area of the p-type substrate 200 overlapped by the metal layers 210, 220, 230 and 240 is decreased by about 50% comparing with the conventional bonding pad. Because of the diffusion region, that is, the p-type dopedregion 204 in the invention, the junction capacitance CP between the n-well 202 and the p-type dopedregion 204, the junction capacitance CN between the n-well 202 and the p-type substrate 200 and the total equivalent capacitance CMeq between thesubstrate 200 and the metal layers 210, 220, 230, 240, 250 are series connected. As a result, the parasitic capacitance of the bonding pad is about 50% less than that of the conventional bonding pad. - A layout of the metal layers210, 220, 230 and 240 mentioned above is not the only way to reduce the area of the p-
type substrate 200 overlapped by the metal layers 210, 220, 230 and 240 according to the invention. - FIG. 7 is a top view of a portion of a substrate, schematically illustrating a bonding pad layout according to the invention, and FIG. 8 is a cross-sectional view, schematically illustrating the bonding pad taken along a line VIII-VIII of FIG. 7. In FIGS. 7 and 8, the metal layers are referred in
numerals metal layer 750 is a planar layer. The metal layers 710, 720, 730 and 740 are aligned with each other and are isolated by severaldielectric layers top dielectric layer 252 covers themetal layer 740. Themetal layer 750 is located on thedielectric layer 252. Additionally, a direction of the metal layers 710, 720, 730 and 740 deviates from the direction 400 (FIG. 2) with an angle, which preferably is 45 degrees in this embodiment. - Referring to FIGS. 7 and 8, each of the metal layers710, 720, 730, 740 and 750 are coupled with the adjacent metal layers by via
plugs dielectric layers plug 714 and the viaplug 724 are not aligned, the viaplug 724 and the viaplug 734 are not aligned, and also the viaplug 734 and the viaplug 744 are not aligned. The viaplug 714 and the viaplug 734 may be aligned and the viaplug 724 and the viaplug 744 may be aligned. As a result, the position of the viaplug 724 connecting the metal layers 720 and 730 is not superimposed on the position of the viaplug 714 used to connect the metal layers 710 and 720 as shown in FIG. 8. The position of the viaplug 734 connecting the metal layers 730 and 740 is not superimposed on the position of the viaplug 724. However, the viaplug 734 is aligned with the viaplug 714, and the viaplug 744 is aligned with the viaplug 724. - Based on a concept of reducing the area of the substrate overlapped by the metal layers, other layouts of the metal layers are also suitable for the invention.
- FIGS. 9 and 11 are top views of a portion of a substrate, schematically illustrating another two bonding pad layouts according to the invention, and FIGS. 10 and 12 are cross-sectional views, schematically illustrating the bonding pad layouts respectively taken along lines X-X and XII-XII in FIGS.9 and FIGS. 10. A layout of the metal layers in FIG. 9 includes, for example, several concentric circles, and a layout of the metal layers in FIG. 11 is concentric polygons, such as squares.
- In FIGS. 9 and 10, the metal layers are referred in
numerals metal layer 950 is a planar layer. Referring to FIGS. 9 and 10, the metal layers 910, 920, 930 and 940 are aligned with each other, and each of the metal layers 910, 920, 930, 940, 950 are coupled by viaplugs dielectric layers - In FIGS. 11 and 12, the metal layers are referred to by
numerals metal layer 1150 is a plane. Referring to FIGS. 11 and 12, themetal layers metal layers plugs - FIGS. 13, 14,15 and 16 are top views of a portion of a substrate, schematically illustrating other bonding pad layouts for the metal layers 210, 220, 230 and 240 according to the invention. Layouts of the metal layers in FIGS. 13, 14, 15 and 16 respectively are concentric pentagons, concentric hexagons, concentric heptagons and concentric octagons. The design concept of these layouts is the same as the previous examples. According to the concept, other kinds of polygons are also acceptable in the invention.
- In FIGS. 17 and 18, the layouts of the metal layers210, 220, 230 and 240 resemble meshes. The layout shown in FIG. 17 is a honeycombed type mesh, and the layout shown in FIG. 18 is a mesh composed of adjacent octagonal units arranged in rows. The mesh in the invention comprises a mesh composed of a unit shape as seen in FIGS. 17 and 18. However, a mesh composed of various unit shapes is suitable for the invention. In FIG. 19, the layout of the metal layers 210, 220, 230 and 240 is a mesh composed of rows of pentagonal structures connected by a line, with each pentagonal unit connected to the pentagon in the row above or below by a line. Each unit shape of the mesh is changed to a heptagon, an octagon and a circle in FIGS. 20, 21 and 22, respectively. Also, other kinds of polygons are acceptable.
- Although only a few layouts for the metal layers are disclosed in the embodiment. An implementation of the layout is not limited by the disclosed examples because the concept disclosed in the invention is to reduce the area of the substrate overlapped by the metal layers. By this concept, the parasitic capacitance of the bonding pad is reduced and the peel-off effect is avoided. As a result, any kind of layout that meets the concept is suitable for the invention. The bonding pad layout can be designed with many types of unit shape that meet the concept, so that any kind of geometry is suitable for use in the invention.
- In a conventional semiconductor device, the bonding pad is not formed above an active device region or circuit region because a subsequent bonding wire process could damage the formed device.
- This issue can also be solved by the invention. Since the bonding pad of the invention include a
top metal layer 250 of FIG. 4 and the stackedmetal layer 208. Thebonding pad opening 270 can be adjusted at the location above the device region. As a result, the available substrate surface can be more efficiently used. - FIG. 23 is a cross-sectional view, schematically illustrating a bonding pad layout with a device, according to the invention. In this example2, devices are formed on the substrate just under the bonding pad.
- Referring to FIG. 23, a
device 32, such as a field effect transistor, is formed on asubstrate 30. Metal layers 51, 52, 53, 54, 55 and 56 are formed in adielectric layer 60 over thedevice 32, in which thedielectric layer 60 serves as an isolation and a frame to stack the metal layers 51, 52, 53, 54, 55, 56. Thedielectric layer 60 can also further include several sub-layers to hold and isolate the metal layers. A bonding pad includes the metal layers 55 and 56 and is covered by the apassivation layer 80. Thepassivation layer 80 includes abonding pad opening 82, which exposes a portion of themetal layer 56. The metal layers 51 and 52 near thesubstrate 30 are used to serve as, for example, signal lines, and the metal layers 53 and 54 are designed to be planar layers and used to serve as, for example, power lines. Apassivation layer 80 is formed on adielectric layer 60, and thebonding pad opening 82 is formed in thepassivation layer 80 to expose themetal layer 56. Abonding wire 84 is attached to themetal layer 56 within thebonding pad opening 84. Each pair of the metal layers 51, 52, 53, 54, 55 and 56 is isolated by thedielectric layer 60. The metal layers 55, 56 are coupled by a viaplug 75 and the metal layers 51, 52 are coupled by a viaplug 71. The metal layers 52, 53 and 54 serving as signal lines and power lines are also coupled by via plugs (not shown), and the metal layers 54 and 55 are similar. However, these via plugs should not be formed under thebonding pad opening 82. Thus, the metal layers 53, 54 can be used to be the buffer layers, and the bonding stress borne on the active devices can be reduced through these buffer layers. - In the invention, the
device 32, such as a CMOS device, is formed on thesubstrate 30 or an n-well 34 in thesubstrate 30. Themetal layer 56 is a plane, and themetal layer 55 is designed as applying one of the layouts shown in example 1 for themetal layer 55 so that the parasitic capacitance and the bonding reliability of the bonding pad are effectively reduced and increased, respectively. - According to the foregoing, the advantages of the invention include the following:
- 1. The bonding pad in the invention is formed by multiple metal layers and buried deeply in the dielectric layer, so that the peel-off effect is avoided and the bonding reliability effectively increases.
- 2. In the invention, the overlapping area of between the substrate and the metal layers is greatly reduced. The parasitic capacitance of the bonding pad is reduced.
- 3. A diffusion region is formed in the substrate so that the contact capacitance of the diffusion region and the capacitance of the bonding pad are connected in series. The parasitic capacitance of the bonding pad is reduced.
- 4. The invention is compatible with the current conventional processes. Only the layout design of the bonding pad is changed to meet the requirement of a semiconductor device. Manufactures can achieve the bonding pad structure of the invention without modifying their fabrication processes.
- 5. The device can be formed under the bonding pad so that the substrate surface is more efficiently used for compact circuit layout.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (25)
1. A low-capacitance bonding pad structure for a semiconductor device, the structure comprising:
a substrate;
a stacked metal layer positioned on the substrate, wherein the stacked metal layer further comprises a plurality of metal layers and a plurality of dielectric layers, which are alternately stacked up, and the metal layers are coupled by a plurality of via plugs in the dielectric layers;
an uppermost metal layer positioned on the stacked metal layer, wherein an area of each metal layer in the stacked metal layer is smaller than that of the uppermost metal layer; and
a passivation layer having a bonding pad opening positioned on the uppermost metal layer, wherein the bonding pad opening exposes a portion of the uppermost metal layer.
2. The structure of claim 1 , wherein the metal layers in the stacked metal layer are in the shape of bars.
3. The structure of claim 2 , wherein the bar direction of each layer of the metal layers is across to each other for the different metal layers.
4. The structure of claim 2 , wherein the metal layers are stacked and aligned with each other.
5. The structure of claim 1 , wherein the metal layers in the stacked metal layer comprises concentric polygons.
6. The structure of claim 1 , wherein the metal layers in the stacked metal layer comprises concentric circles.
7. The structure of claim 1 , wherein the metal layers in the stacked metal layer comprises a mesh structure.
8. The structure of claim 7 , wherein the metal layers in the stacked metal layer are aligned with each other.
9. The structure of claim 7 , wherein the mesh is composed of a unit geometric shape.
10. The structure of claim 9 , wherein the unit shape is a polygon.
11. The structure of claim 9 , wherein the unit shape is a circle.
12. The structure of claim 1 , wherein the mesh is composed of various unit shapes.
13. The structure of claim 1 , wherein locations of the via plugs in two adjacent layers of the dielectric layers are shifted with a proper distance.
14. A semiconductor structure, the structure comprising:
a substrate;
a bonding pad over the substrate, wherein the bonding pad comprises a stacked metal layer and an uppermost metal layer; and
a device located on the substrate just under the bonding pad.
15. The structure of claim 14 , wherein the stacked metal layer comprises a plurality of metal layers and a plurality of dielectric layers, which are alternatingly stacked up, and the metal layers are coupled by a plurality of via plugs in the dielectric layers.
16. The structure of claim 14 , wherein an area of each metal layer in the stacked metal layer is smaller than that of the uppermost metal layer.
17. The structure of claim 14 , wherein the structure further comprises a signal line and a power line between the device and the bonding pad.
18. The structure of claim 17 , wherein the stacked metal layer comprises a plurality of metal layers and a plurality of dielectric layers, which are alternatingly stacked up, and the metal layers are coupled by a plurality of via plugs in the dielectric layers.
19. The structure of claim 17 , wherein an area of each metal layer in the stacked metal layer is smaller than that of the uppermost metal layer.
20. The structure of claim 14 , wherein the device on the substrate just under the bonding pad is an active device.
21. The structure of claim 14 , wherein the device on the substrate just under the bonding pad is a passive device.
22. A low-capacitance bonding pad structure for a semiconductor device, the structure comprising:
a substrate having a well;
a doped region as a diffusion region formed in the well; and
a bonding pad over the substrate and aligned with the doped region, wherein the bonding pad comprises a stacked metal layer and an uppermost metal layer.
23. The structure of claim 22 , wherein ions doped in the doped region is opposite to those in the well.
24. The structure of claim 22 , wherein the stacked metal layer comprises a plurality of metal layers and a plurality of dielectric layers, which are alternatingly stacked up, and the metal layers are coupled by a plurality of via plugs in the dielectric layers.
25. The structure of claim 22 , wherein an area of each metal layer in the stacked metal layer is smaller than that of the uppermost metal layer.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US09/818,455 US6633087B2 (en) | 1999-03-19 | 2001-03-27 | Low-capacitance bonding pad for semiconductor device |
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TW088104304A TW430935B (en) | 1999-03-19 | 1999-03-19 | Frame type bonding pad structure having a low parasitic capacitance |
TW88104304 | 1999-03-19 |
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US09/818,455 Division US6633087B2 (en) | 1999-03-19 | 2001-03-27 | Low-capacitance bonding pad for semiconductor device |
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US09/818,449 Expired - Lifetime US6717238B2 (en) | 1999-03-19 | 2001-03-27 | Low-capacitance bonding pad for semiconductor device |
US09/818,816 Abandoned US20010010404A1 (en) | 1999-03-19 | 2001-03-27 | Low-capacitance bonding pad for semiconductor device |
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US09/818,449 Expired - Lifetime US6717238B2 (en) | 1999-03-19 | 2001-03-27 | Low-capacitance bonding pad for semiconductor device |
US09/818,816 Abandoned US20010010404A1 (en) | 1999-03-19 | 2001-03-27 | Low-capacitance bonding pad for semiconductor device |
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Publication number | Priority date | Publication date | Assignee | Title |
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Families Citing this family (102)
Publication number | Priority date | Publication date | Assignee | Title |
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US6426555B1 (en) * | 2000-11-16 | 2002-07-30 | Industrial Technology Research Institute | Bonding pad and method for manufacturing it |
US6833620B1 (en) * | 2000-11-28 | 2004-12-21 | Ati Technologies, Inc. | Apparatus having reduced input output area and method thereof |
US6455943B1 (en) * | 2001-04-24 | 2002-09-24 | United Microelectronics Corp. | Bonding pad structure of semiconductor device having improved bondability |
FR2824954A1 (en) * | 2001-05-18 | 2002-11-22 | St Microelectronics Sa | Connection pad for an integrated circuit, comprises a reinforcement structure connected by feedthroughs to upper metallization |
US6501186B1 (en) * | 2001-07-25 | 2002-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd | Bond pad having variable density via support and method for fabrication |
US6678950B1 (en) * | 2001-11-01 | 2004-01-20 | Lsi Logic Corporation | Method for forming a bonding pad on a substrate |
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US6566758B1 (en) * | 2001-11-27 | 2003-05-20 | Sun Microsystems, Inc. | Current crowding reduction technique for flip chip package technology |
JP2005512315A (en) * | 2001-11-29 | 2005-04-28 | サン マイクロシステムズ インコーポレーテッド | Method and apparatus for improving integrated circuit performance and reliability using a patterned bump layout on a power grid |
KR100437460B1 (en) * | 2001-12-03 | 2004-06-23 | 삼성전자주식회사 | Semiconductor device having bonding pads and fabrication method thereof |
US7932603B2 (en) | 2001-12-13 | 2011-04-26 | Megica Corporation | Chip structure and process for forming the same |
US6650010B2 (en) * | 2002-02-15 | 2003-11-18 | International Business Machines Corporation | Unique feature design enabling structural integrity for advanced low K semiconductor chips |
KR100416614B1 (en) * | 2002-03-20 | 2004-02-05 | 삼성전자주식회사 | Semiconductor device for reinforcing a under structure of bonding pad and method for fabricating the same |
US6909196B2 (en) * | 2002-06-21 | 2005-06-21 | Micron Technology, Inc. | Method and structures for reduced parasitic capacitance in integrated circuit metallizations |
DE10229493B4 (en) * | 2002-07-01 | 2007-03-29 | Infineon Technologies Ag | Integrated semiconductor structure |
US7692315B2 (en) * | 2002-08-30 | 2010-04-06 | Fujitsu Microelectronics Limited | Semiconductor device and method for manufacturing the same |
US6955981B2 (en) | 2002-09-13 | 2005-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad structure to prompt excellent bondability for low-k intermetal dielectric layers |
US6908841B2 (en) * | 2002-09-20 | 2005-06-21 | Infineon Technologies Ag | Support structures for wirebond regions of contact pads over low modulus materials |
US6825541B2 (en) * | 2002-10-09 | 2004-11-30 | Taiwan Semiconductor Manufacturing Co., Ltd | Bump pad design for flip chip bumping |
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DE10249192A1 (en) * | 2002-10-22 | 2004-05-13 | Infineon Technologies Ag | Electronic component with integrated passive electronic component and method for its production |
DE60320299T2 (en) * | 2002-11-08 | 2009-05-20 | Nxp B.V. | Integrated circuit with at least one contact bump |
GB2411767B (en) * | 2002-12-20 | 2006-11-01 | Agere Systems Inc | Structure and method for bonding to copper interconnect structures |
JP4170103B2 (en) * | 2003-01-30 | 2008-10-22 | Necエレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
TWI220565B (en) | 2003-02-26 | 2004-08-21 | Realtek Semiconductor Corp | Structure of IC bond pad and its formation method |
US6864578B2 (en) * | 2003-04-03 | 2005-03-08 | International Business Machines Corporation | Internally reinforced bond pads |
JP4357862B2 (en) * | 2003-04-09 | 2009-11-04 | シャープ株式会社 | Semiconductor device |
TWI249842B (en) * | 2003-07-22 | 2006-02-21 | Ali Corp | Integrated circuit structure and design method |
US7495343B1 (en) | 2003-07-31 | 2009-02-24 | Nvidia Corporation | Pad over active circuit system and method with frame support structure |
US7453158B2 (en) | 2003-07-31 | 2008-11-18 | Nvidia Corporation | Pad over active circuit system and method with meshed support structure |
KR100555524B1 (en) * | 2003-11-01 | 2006-03-03 | 삼성전자주식회사 | Pad for bonding of semiconductor device and method of manufacturing the same |
US7098540B1 (en) * | 2003-12-04 | 2006-08-29 | National Semiconductor Corporation | Electrical interconnect with minimal parasitic capacitance |
JP4242336B2 (en) * | 2004-02-05 | 2009-03-25 | パナソニック株式会社 | Semiconductor device |
US20050242416A1 (en) * | 2004-04-29 | 2005-11-03 | United Microelectronics Corp. | Low-capacitance bonding pad for semiconductor device |
JP4759229B2 (en) * | 2004-05-12 | 2011-08-31 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP2005327952A (en) * | 2004-05-17 | 2005-11-24 | Mitsubishi Electric Corp | Semiconductor device for electric power |
DE102004025658A1 (en) * | 2004-05-26 | 2005-12-29 | Infineon Technologies Ag | Method for producing a semiconductor circuit and corresponding semiconductor circuit |
US7274108B2 (en) * | 2004-11-15 | 2007-09-25 | United Microelectronics Corp. | Semiconductor chip capable of implementing wire bonding over active circuits |
JP4517843B2 (en) * | 2004-12-10 | 2010-08-04 | エルピーダメモリ株式会社 | Semiconductor device |
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US20060207790A1 (en) * | 2005-03-15 | 2006-09-21 | Jayoung Choi | Bonding pads having slotted metal pad and meshed via pattern |
US7646087B2 (en) * | 2005-04-18 | 2010-01-12 | Mediatek Inc. | Multiple-dies semiconductor device with redistributed layer pads |
US20060244156A1 (en) * | 2005-04-18 | 2006-11-02 | Tao Cheng | Bond pad structures and semiconductor devices using the same |
US7482258B2 (en) * | 2005-04-28 | 2009-01-27 | International Business Machines Corporation | Product and method for integration of deep trench mesh and structures under a bond pad |
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US20070267748A1 (en) * | 2006-05-16 | 2007-11-22 | Tran Tu-Anh N | Integrated circuit having pads and input/output (i/o) cells |
US7808117B2 (en) * | 2006-05-16 | 2010-10-05 | Freescale Semiconductor, Inc. | Integrated circuit having pads and input/output (I/O) cells |
EP2054935A2 (en) * | 2006-08-17 | 2009-05-06 | Nxp B.V. | Testing for correct undercutting of an electrode during an etching step |
US7868459B2 (en) * | 2006-09-05 | 2011-01-11 | International Business Machines Corporation | Semiconductor package having non-aligned active vias |
DE102006046182B4 (en) * | 2006-09-29 | 2010-11-11 | Infineon Technologies Ag | Semiconductor element with a support structure and manufacturing method |
US7679180B2 (en) * | 2006-11-07 | 2010-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bond pad design to minimize dielectric cracking |
CN101536184B (en) * | 2006-11-13 | 2011-07-13 | Nxp股份有限公司 | Bond pad structure and method for producing same |
US7573115B2 (en) * | 2006-11-13 | 2009-08-11 | International Business Machines Corporation | Structure and method for enhancing resistance to fracture of bonding pads |
US7749885B2 (en) * | 2006-12-15 | 2010-07-06 | Micron Technology, Inc. | Semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers |
US20080296758A1 (en) * | 2007-05-30 | 2008-12-04 | Texas Instruments Incorporated | Protection and Connection of Devices Underneath Bondpads |
US7825005B1 (en) * | 2007-08-27 | 2010-11-02 | Raytheon Company | Multiple substrate electrical circuit device |
DE102007046556A1 (en) * | 2007-09-28 | 2009-04-02 | Infineon Technologies Austria Ag | Semiconductor device with copper metallizations |
KR100937664B1 (en) * | 2007-12-26 | 2010-01-19 | 주식회사 동부하이텍 | Pad of semiconductor devic and method for manufacturing the pad |
US20090189289A1 (en) * | 2008-01-27 | 2009-07-30 | International Business Machines Corporation | Embedded constrainer discs for reliable stacked vias in electronic substrates |
FR2931586B1 (en) * | 2008-05-22 | 2010-08-13 | St Microelectronics Grenoble | METHOD FOR MANUFACTURING AND TESTING AN INTEGRATED ELECTRONIC CIRCUIT |
US8138616B2 (en) * | 2008-07-07 | 2012-03-20 | Mediatek Inc. | Bond pad structure |
US8212357B2 (en) * | 2008-08-08 | 2012-07-03 | International Business Machines Corporation | Combination via and pad structure for improved solder bump electromigration characteristics |
US8581423B2 (en) * | 2008-11-17 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Double solid metal pad with reduced area |
US8310056B2 (en) * | 2009-05-29 | 2012-11-13 | Renesas Electronics Corporation | Semiconductor device |
JP5313854B2 (en) * | 2009-12-18 | 2013-10-09 | 新光電気工業株式会社 | Wiring substrate and semiconductor device |
JP5610905B2 (en) * | 2010-08-02 | 2014-10-22 | パナソニック株式会社 | Semiconductor device |
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US20130154099A1 (en) | 2011-12-16 | 2013-06-20 | Semiconductor Components Industries, Llc | Pad over interconnect pad structure design |
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US9177914B2 (en) * | 2012-11-15 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal pad structure over TSV to reduce shorting of upper metal layer |
US8928142B2 (en) | 2013-02-22 | 2015-01-06 | Fairchild Semiconductor Corporation | Apparatus related to capacitance reduction of a signal port |
US9773732B2 (en) | 2013-03-06 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for packaging pad structure |
US9431320B2 (en) | 2013-03-15 | 2016-08-30 | Analog Devices, Inc. | Methods and structures to facilitate through-silicon vias |
US8890339B1 (en) | 2013-04-30 | 2014-11-18 | Freescale Semiconductor, Inc. | Self-defining, low capacitance wire bond pad |
US9461000B2 (en) * | 2013-05-21 | 2016-10-04 | Esilicon Corporation | Parallel signal via structure |
US9076804B2 (en) * | 2013-08-23 | 2015-07-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Systems and methods to enhance passivation integrity |
KR102246277B1 (en) * | 2014-03-14 | 2021-04-29 | 에스케이하이닉스 주식회사 | Semiconductor device and method for manufacturing the same |
US9245846B2 (en) * | 2014-05-06 | 2016-01-26 | International Business Machines Corporation | Chip with programmable shelf life |
CN106661289B (en) | 2014-06-24 | 2020-06-05 | 陶氏环球技术有限责任公司 | Polyolefin photovoltaic backsheet comprising a stabilized polypropylene layer |
US9536848B2 (en) * | 2014-10-16 | 2017-01-03 | Globalfoundries Inc. | Bond pad structure for low temperature flip chip bonding |
JP6806252B2 (en) * | 2017-07-13 | 2021-01-06 | 富士電機株式会社 | Semiconductor device |
US10410934B2 (en) * | 2017-12-07 | 2019-09-10 | Micron Technology, Inc. | Apparatuses having an interconnect extending from an upper conductive structure, through a hole in another conductive structure, and to an underlying structure |
CN109950220B (en) * | 2017-12-21 | 2021-01-01 | 合肥杰发科技有限公司 | Bonding pad structure and manufacturing method thereof |
US10566300B2 (en) * | 2018-01-22 | 2020-02-18 | Globalfoundries Inc. | Bond pads with surrounding fill lines |
US11171131B2 (en) * | 2018-08-29 | 2021-11-09 | Stmicroelectronics International N.V. | Multi-fingered diode with reduced capacitance and method of making the same |
US20210104477A1 (en) * | 2019-10-04 | 2021-04-08 | Macronix International Co., Ltd. | Pad structure |
CN111584450A (en) * | 2020-05-26 | 2020-08-25 | 四川中微芯成科技有限公司 | IO pad structure for wire bonding |
CN112397467B (en) * | 2020-11-13 | 2024-02-27 | 武汉新芯集成电路制造有限公司 | Wafer bonding structure and manufacturing method thereof |
CN116110872A (en) * | 2023-04-12 | 2023-05-12 | 江苏应能微电子股份有限公司 | Low parasitic capacitance bonding pad |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6370442A (en) * | 1986-09-11 | 1988-03-30 | Kyocera Corp | Multilayer interconnection substrate |
JPH04196552A (en) * | 1990-11-28 | 1992-07-16 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
JPH05283467A (en) * | 1992-03-30 | 1993-10-29 | Nec Corp | Semiconductor integrated circuit device |
US5404047A (en) * | 1992-07-17 | 1995-04-04 | Lsi Logic Corporation | Semiconductor die having a high density array of composite bond pads |
US5410107A (en) * | 1993-03-01 | 1995-04-25 | The Board Of Trustees Of The University Of Arkansas | Multichip module |
EP0637840A1 (en) * | 1993-08-05 | 1995-02-08 | AT&T Corp. | Integrated circuit with active devices under bond pads |
DE69330603T2 (en) * | 1993-09-30 | 2002-07-04 | Cons Ric Microelettronica | Process for metallization and connection in the production of power semiconductor components |
JP3432284B2 (en) * | 1994-07-04 | 2003-08-04 | 三菱電機株式会社 | Semiconductor device |
US5652689A (en) * | 1994-08-29 | 1997-07-29 | United Microelectronics Corporation | ESD protection circuit located under protected bonding pad |
JPH08293523A (en) * | 1995-02-21 | 1996-11-05 | Seiko Epson Corp | Semiconductor device and its manufacture |
US5965903A (en) * | 1995-10-30 | 1999-10-12 | Lucent Technologies Inc. | Device and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein |
KR100230428B1 (en) * | 1997-06-24 | 1999-11-15 | 윤종용 | Semiconductor device comprising a multi-conductive pad and method for manufacturing the same |
KR100267105B1 (en) * | 1997-12-09 | 2000-11-01 | 윤종용 | Semiconductor device with multi-layer pad and manufacturing method |
TW392325B (en) * | 1998-05-01 | 2000-06-01 | United Microelectronics Corp | Structure of metallization and process thereof |
US5986343A (en) * | 1998-05-04 | 1999-11-16 | Lucent Technologies Inc. | Bond pad design for integrated circuits |
US6043144A (en) * | 1998-05-25 | 2000-03-28 | United Microelectronics Corp. | Bonding-pad structure for integrated circuit and method of fabricating the same |
TW416575U (en) * | 1998-06-03 | 2000-12-21 | United Integrated Circuits Corp | Bonding pad structure |
TW406394B (en) * | 1998-06-17 | 2000-09-21 | Nanya Plastics Corp | Ion-replulsion structure used in the fuse window |
US6163074A (en) * | 1998-06-24 | 2000-12-19 | Samsung Electronics Co., Ltd. | Integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein |
US6261944B1 (en) * | 1998-11-24 | 2001-07-17 | Vantis Corporation | Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect |
US6291331B1 (en) * | 1999-10-04 | 2001-09-18 | Taiwan Semiconductor Manufacturing Company | Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue |
US20020043727A1 (en) * | 2000-10-13 | 2002-04-18 | Hsiao-Che Wu | Bonding pad structure |
-
1999
- 1999-03-19 TW TW088104304A patent/TW430935B/en not_active IP Right Cessation
- 1999-06-09 US US09/329,648 patent/US6448641B2/en not_active Expired - Lifetime
-
2001
- 2001-03-27 US US09/818,455 patent/US6633087B2/en not_active Expired - Lifetime
- 2001-03-27 US US09/818,449 patent/US6717238B2/en not_active Expired - Lifetime
- 2001-03-27 US US09/818,816 patent/US20010010404A1/en not_active Abandoned
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US8541893B2 (en) | 2004-09-20 | 2013-09-24 | Samsung Electronics Co., Ltd. | Semiconductor memory device and power line arrangement method thereof |
DE102005045697B4 (en) * | 2004-09-20 | 2009-10-08 | Samsung Electronics Co., Ltd., Suwon | Semiconductor device and utility line arrangement method |
US20060060986A1 (en) * | 2004-09-20 | 2006-03-23 | Sung-Hoon Kim | Semiconductor memory device and power line arrangement method thereof |
US8384189B2 (en) | 2005-03-29 | 2013-02-26 | Megica Corporation | High performance system-on-chip using post passivation process |
US20080284032A1 (en) * | 2005-03-29 | 2008-11-20 | Megica Corporation | High performance system-on-chip using post passivation process |
US20090001511A1 (en) * | 2005-03-29 | 2009-01-01 | Megica Corporation | High performance system-on-chip using post passivation process |
US7741724B2 (en) * | 2007-04-02 | 2010-06-22 | Sanyo Electric Co., Ltd. | Semiconductor device |
US20080237877A1 (en) * | 2007-04-02 | 2008-10-02 | Sanyo Electric Co., Ltd. | Semiconductor device |
US20090166880A1 (en) * | 2007-12-28 | 2009-07-02 | Stmicroelectronics S.A. | Electrical bonding pad |
US9035423B1 (en) * | 2013-12-25 | 2015-05-19 | Mitsubishi Electric Corporation | Semiconductor device with inductor having interleaved windings for controlling capacitance |
US9515083B2 (en) | 2014-09-19 | 2016-12-06 | Samsung Electronics Co., Ltd. | Nonvolatile memory device |
US9899409B2 (en) | 2014-09-19 | 2018-02-20 | Samsung Electronics Co., Ltd. | Nonvolatile memory device having pad structure for high speed operation |
US11158591B2 (en) * | 2016-05-13 | 2021-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond pad structure for bonding improvement |
Also Published As
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US6633087B2 (en) | 2003-10-14 |
TW430935B (en) | 2001-04-21 |
US6717238B2 (en) | 2004-04-06 |
US6448641B2 (en) | 2002-09-10 |
US20010010404A1 (en) | 2001-08-02 |
US20010010408A1 (en) | 2001-08-02 |
US20010010407A1 (en) | 2001-08-02 |
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