BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
A memory cell of an MRAM (Magneto-Resistive Random Access Memory) is shown diagrammatically in FIG. 8. In such a memory It cell, the information to be stored is stored by the nature of the orientation of the magnetic moments in adjacent magnetized layers ML1 and ML2, which are separated from one another by a very thin nonmagnetic intermediate layer TL, which is nonconductive. This is because the size of the electrical AS resistance across the memory cell depends on the parallel or antiparallel orientation of the magnetic moments in the magnetized layers ML1 and ML2, that is to say the polarization thereof. In the case of the parallel orientation of the magnetic moments in the two layers ML1 and ML2, the resistance of the memory cell is generally lower than in the case of their antiparallel orientation. This effect is also referred to as TMR effect (TMR=“tunneling magnetoresistive”) or as MTJ effect (MTJ=“magnetic tunnel junction”).
As a result, the memory content of the memory cell can be read out by detecting the resistance of the memory cell, the resistance being different for a “1” or “0”. Parallel magnetization of the two layers ML1 and ML2 may be assigned to a digital zero, for example, in which case the antiparallel magnetization of these layers corresponds to a digital one.
The change in resistance between the parallel and the antiparallel orientation of the magnetic moments in the magnetized layers ML1 and ML2 is physically based on the interaction of the electron spins of the conduction electrons in the thin nonmagnetic intermediate layer TL with the magnetic moments in the magnetized layers ML1 and ML2 of the memory cell. In this case, “thin” is intended to express the fact that the conduction electrons can cross the intermediate layer TL without spin scattering processes.
Preferably, the magnetization of one of the two magnetized layers ML1 and ML2 is coupled to an antiferromagnetic support or covering layer, as a result of which the magnetization in this magnetized layer remains essentially fixed, while the magnetic moment of the other magnetized layer can be freely oriented even in the case of small magnetic fields, as are generated for instance by a current in a word line WL and a bit line BL above and below the magnetized layer.
In a memory cell array, programming currents IWL and IBL flowing through the word line WL and through the bit line BL, respectively, are chosen such that a magnetic field strong enough for programming prevails only in the cell in which the word line WL crosses the bit line BL, by virtue of the sum of the two currents IWL and IBL, while all of the other memory cells present on this word line WL or this bit line BL cannot be reprogrammed by the current flowing only through one of these two lines.
FIG. 8B once again diagrammatically illustrates the resistance RC of the memory cell between a bit line BL and a word line WL. The resistance RC is larger for the antiparallel orientation of the magnetic moments in the layers ML1 and ML2 than for the parallel orientation of the magnetic moments, i.e. RC (“0”)<RC (“1”), if the above assumption for the assignment of a “1” or a “0” is taken as a basis.
In their simplest embodiment, MRAMs include interconnects—crossing one another in a matrix form—of the word lines WL and of the bit lines BL, via which the memory cells are addressed. An upper interconnect, for example the bit line BL (cf. FIG. 8A), is in this case connected to the upper magnetized layer ML1, e.g. a ferromagnetic layer, while the lower interconnect, which forms the word line WL, bears against the lower magnetized layer ML2, which may likewise be a ferromagnetic layer. If a voltage is applied to the memory cell via the two interconnects for the word line WL and the bit line BL, then a tunneling current flows through the thin nonmagnetic intermediate layer TL. This thin nonmagnetic intermediate layer then forms the resistance RC (See FIG. 8B) which, depending on the parallel or the antiparallel orientation of the magnetic moments, that is to say the parallel or the antiparallel polarization of the upper and lower ferromagnetic layers, given a suitable voltage across the memory cell, assumes the magnitude RC (“0”)<RC (“1”) or RC (“1”)=RC (“0”)+ΔRC.
FIG. 9 shows a memory cell array in which memory cells are configured like a matrix at crossover points between word lines WL and bit lines BL.
The cell content is indicated diagrammatically here depending on the antiparallel or parallel polarization as a “1” or a “0” for two memory cells.
In a memory cell array as shown diagrammatically in FIG. 9, not only does a current flow via the memory cell at the crossover point between a selected word line WL and a selected bit line BL, but undesirable shunt currents also occur at further memory cells which are respectively connected to the selected word line WL and the selected bit line BL. These undesirable shunt currents interfere to a considerable extent with the read current which flows through the selected memory cell.
Therefore, efforts have already been made to use suitable circuitry of the memory cell array to largely separate such undesirable shunt currents from the read current, so that only the read current through the selected memory cell or the read voltage across the memory cell is available for detection. In this case, however, because of the parasitic currents flowing through the other memory cells, the resistance of the memory cells must be chosen to be high, in particular in the Mohm range, in order to be able to construct sufficiently large memory cell arrays.
Another way of avoiding the undesirable shunt currents is to augment the inherently simply constructed MTJ memory cell (cf. FIG. 10a) with a diode D (cf. FIG. 10b) or with a switching transistor T (cf. FIG. 10c) (R. Scheuerlain et al., “A 10 ns Read and Write Time Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET-Switch in each Cell”, ISSCC Feb. 2000 p. 128/R.c. Sousa et al., “Vertical Integration of a spin dependent tunnel junction with an amorphous Si diode”, appl. Phys. Letter Vol. 74, No. 25, pp. 3893 to 3895).
The advantage of such augmentation by a diode or a switching transistor is that, in the memory cell array, given suitable circuitry, a read current only flows through the memory cell that is respectively read, since all of the remaining memory cells are inhibited. The resistance of the memory cell can then be chosen to be lower in contrast to a pure MTJ cell in accordance with FIG. 10a, as a result of which the read current becomes relatively large and the read-out can take place rapidly in the ns range. Such additional circuitry with a diode or a transistor has the disadvantage, however, that it causes considerable additional technological and areal outlay. In the current state of the art, it is a common feature of all memory cell types that it is very difficult to detect or evaluate a read signal as “0” or “1” since the tunneling resistance formed by the layer sequence of the layers ML1, TL and ML2 generally fluctuates, not only over a wafer but even in many cases between adjacent memory cells, to a much greater extent, i.e. up to 40%, than the difference in the resistance ΔRC between a “1” state and a “0” state, which is just 15%, for example. In other words, these conditions make it considerably more difficult or even impossible to reliably detect the content of a memory cell.
In other memory types that differ from MRAMs, a “1” or a “0” is detected from a current or a voltage read signal by comparing the read signal with either a reference current or a reference voltage, which should have a value midway between the read current or the read voltage for a “1” and the read current or the read voltage for a “0” in order to achieve the best signal-to-noise ratio in each case for both digital values. The reference current or the reference voltage can be generated by means of reference sources or, alternatively, by means of reference cells to which a “1” and a “0” have been permanently written.
However, such a procedure can be used at best in a limited fashion, if at all, for detecting the read signal in an MTJ cell. This is attributable to the great fluctuation—outlined in the introduction—of the tunneling resistance from memory cell to memory cell and over the entire wafer.
To date, there have been only two approaches for solving the problems evinced above:
A first approach (in this respect, cf. R. Scheuerlain et al. “A 10 ns Read and Write Time Non-volatile Memory Array Using a Magnetic Tunnel Junction and FET-Switch in each Cell”, ISSCC February 2000, p. 128) is suitable for MTJ cells with a switching transistor (cf. FIG. 10c) and consists in using two adjacent complementary memory cells for storing only one cell content. It always being the case that the memory content is written to the first memory cell and the complement of the memory content, that is to say the inverted memory content, is written to the second memory cell. During read-out, both memory cells are read and the contents are detected. In this case, the read signal and the signal-to-noise ratio are twice as large as in the customary reference method explained above. However, the space requirement and the technological outlay for two memory cells and two switching transistors are also very large, and it must be ensured that the resistance fluctuations between the two adjacent complementary cells are so small that reliable detection can be effected.
This precondition is not necessary in the second approach, which is based on self-referencing of a read pure MTJ memory cell (cf. FIG. 10a). In this case, the procedure is as follows:
Firstly, the cell content of a selected memory cell is read out and stored. A “0”, for example, is then programmed into this memory cell. The content of the programmed-in “0” of the memory cell is then read out and stored. The cell content stored first is compared with the stored known “0” and detected, and the cell content thus detected is written back to the memory cell again.
What is disadvantageous about such a procedure is, then, that during the detection of the read signal, a predefined half read signal has to be added to the “0” that is programmed in as a reference and read out again, as a result of which resistance fluctuations once again enter into the detection of the memory cell.
In the second approach, then, in order to be totally independent of resistance fluctuations of the memory cells, the method just explained has to be completed by writing in a “1”. The following method sequence is then present:
(a) The cell content of a selected memory cell is read and stored.
(b) A “0”, for example, is programmed into the memory cells.
(c) The content of the programmed-in “0” of the memory cell is read and stored.
(d) A “1”, for example, is programmed into the memory cell.
(e) The content of the programmed-in “1” of the memory cell is read and stored.
(f) The stored cell content from (a) is compared with the stored quantity “1” and “0” from (c) and (e) and is detected. This is effected by forming a reference voltage Vref from the known “0” and “1”. Only half of the read signal difference is available in each case for detecting the read “1” or “0”, as is indicated for a read “0” in FIG. 11a and for a read “1” in FIG. 11b.
(g) Finally, the detected cell content is written back to the memory cell again. Through the written-in and read “1” and “0”, the method according to the second approach generates the reference voltage in the selected memory cell itself, so that resistance fluctuations from memory cell to memory cell do not influence the detection. However, the signal-to-noise ratio of a “1” or of a “0” is only half as large as in the first-described method of the complementary cells according to the first approach. The considerable disadvantage of the method according to the second approach is that a total of three read cycles and three write cycles and also an evaluation cycle are required, as a result of which the read operation becomes very slow.
To summarize, it can thus be stated that twice the space requirement and small resistance fluctuations between adjacent memory cells are required in the first approach, while the second approach, with a total of seven cycles, demands a considerable amount of time for a read operation.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for nondestructively reading memory cells of an MRAM memory which overcomes the above-mentioned disadvantageous of the prior art apparatus and methods of this general type. In particular, it is an object of the invention, to provide such a method that has a small space requirement and that requires less time for each read operation.
With the foregoing and other objects in view there is provided, in accordance with the invention a method for nondestructively reading memory cells of an MRAM memory, which includes steps of: determining a standard resistance of a memory cell at a voltage at which a resistance of the memory cell is independent of a stored content of the memory cell; determining an actual resistance or of the memory cell at a voltage at which the resistance of the memory cell is dependent on the stored content of the memory cell; obtaining a normalized actual resistance of the memory cell by dividing the actual resistance or by the standard resistance; obtaining a comparison result by comparing the normalized actual resistance with a reference value; and detecting the stored content of the memory cell dependent on the comparison result.
The method may be more easily understood in reference to the following somewhat repetitive description in which reference is made to formulas. In other words the method includes steps of:
(a) determining a standard resistance Rstandard of a memory cell at a voltage at which the resistance of the memory cell is independent of the cell content thereof;
(b) determining the actual resistance R(0) or R(1) of the memory cell at a voltage at which the resistance of the memory cell is dependent on the cell content thereof;
(c) normalizing the actual resistance using the standard resistance by forming
(d) comparing Rstandard(0) or Rstandard(1) with a normalized reference resistance:
(e) detecting the memory cell content as a 0 or as a 1 in a manner dependent on the comparison result.
The method and a configuration that is utilized when performing the method thus exploit a property of MTJ memory cells to which hardly any attention has been given heretofore. Specifically, the value of the tunneling resistance of a memory cell is dependent on the voltage across the memory cell. In this case, there are voltage ranges in which the tunneling resistance has the same magnitude, that is to say is of the same magnitude for a “1” and a “0”, independently of the directions of the polarizations in the two magnetized layers. In other voltage ranges, by contrast, in the case of antiparallel orientation of the polarization in the two magnetized layers, the resistance is larger by AR than in the case of parallel orientation of the polarization in these layers, so that the cell content can in this case be differentiated according to “0” and “1” at this voltage.
The method is based on the fact that in the voltage range mentioned first, which shall be designated by U1, the resistance RC of the memory cell can be determined independently of the content of the memory cell, while in the voltage range mentioned second, which shall be indicated by U2, the resistance RC can be detected depending on the cell content. It is thus possible to normalize the resistance RC (U2) dependent on the cell content by means of the resistance RC (U1) independent of the cell content such that the content of different memory cells, which need not be adjacent, can be compared with one another again. As a result, it is also possible to compare the normalized read signal of an addressed memory cell with a normalized reference signal of a reference cell to which in each case a “0” or a “1” is always written, and thus to detect the content of the memory cell as “1” or “0”.
In accordance with an added feature of the invention, the method includes: storing the standard resistance of the memory cell in a transistor circuit; and connecting the memory cell to the transistor circuit.
In accordance with an additional feature of the invention, the method includes: providing an amplifier having an output; and using a switch to connect the transistor circuit to the output of the amplifier.
In accordance with another feature of the invention, the method includes: defining the amplifier as a first amplifier having a first input; providing a second amplifier having an output and a first input; connecting the first input of the first amplifier to the output of the second amplifier; and connecting the first input of the second amplifier to the memory cell.
In accordance with a further feature of the invention, the method includes: providing the first amplifier with a second input and supplying the second input of the first amplifier with a first fixed voltage; and providing the second amplifier with a second input and supplying the second input of the second amplifier with a second fixed voltage.
In accordance with a further added feature of the invention, the method includes: providing the transistor circuit with two transistors having source-drain paths that are connected in parallel; and locating the two transistors between the memory cell and an output.
In accordance with a concomitant feature of the invention, the method includes: providing the two transistors with gate terminals; and connecting the gate terminals to a switch and to a storage capacitor.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for the nondestructive reading of memory cells of an MRAM memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.