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Publication numberUS20020018366 A1
Publication typeApplication
Application numberUS 09/805,297
Publication dateFeb 14, 2002
Filing dateMar 13, 2001
Priority dateMar 13, 2000
Also published asDE10012105A1, DE10012105B4, US6407945
Publication number09805297, 805297, US 2002/0018366 A1, US 2002/018366 A1, US 20020018366 A1, US 20020018366A1, US 2002018366 A1, US 2002018366A1, US-A1-20020018366, US-A1-2002018366, US2002/0018366A1, US2002/018366A1, US20020018366 A1, US20020018366A1, US2002018366 A1, US2002018366A1
InventorsAndreas von Schwerin, Oskar Kowarik, Franz Schuler
Original AssigneeVon Schwerin Andreas Graf, Oskar Kowarik, Franz Schuler
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for reading nonvolatile semiconductor memory configurations
US 20020018366 A1
Abstract
A method for reading non-volatile semiconductor memory configurations includes determining a high threshold voltage and a low threshold voltage based on a charge state of a floating gate for a transistor, and applying a reverse bias between a bulk and a source of the transistor during reading.
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Claims(6)
We claim:
1. A method for reading non-volatile semiconductor memory configurations, which comprises:
determining a high threshold and a low threshold voltage based on a charge state of a floating gate for a transistor; and
applying a reverse bias between a bulk and a source of the transistor during reading.
2. The method according to claim 1, which further comprises
permitting the low threshold voltage to assume negative voltage values for NMOS transistors; and
permitting the low threshold voltage to assume positive voltage values for PMOS transistors.
3. The method according to claim 1, which further comprises expanding the window between the high threshold voltage and the low threshold voltage by applying the reverse bias.
4. The method according to claim 1, which further comprises maintaining constant the window between the high threshold voltage and the low threshold voltage by applying the reverse bias.
5. The method according to claim 1, which further comprises shifting a threshold voltage for NMOS transistors by γ({square root}{square root over (−VSB+2φf)}−{square root}{square root over (2φf)}) and shifting a threshold voltage for PMOS transistors by −γ({square root}{square root over (VSB−2φf)}−{square root}{square root over (−2φf)}) by applying the bias, where γ is the substrate control factor and φf is the Fermi voltage of the bulk.
6. The method according to claim 1, which further comprises placing each of a drain of the transistor and the source of the transistor at different potentials when the reverse bias has been applied.
Description
BACKGROUND OF THE INVENTION

[0001] Field of the Invention

[0002] The invention lies in the field of semiconductors. The invention relates to a method for reading nonvolatile semiconductor memory configurations in which a high threshold voltage and a low threshold voltage are determined based on the charge state of a floating gate for a transistor.

[0003] In semiconductor memory configurations using, as memory cells, MOS transistors with a control gate and a floating gate, a leakage current problem arises. This problem can also be called the “moving bit problem”, or MB problem for short. In the MB problem, the floating gate loses its charge due to very small leakage currents over long times, which means there exists a limited data holding property. Because the leakage currents are exponentially dependent on the electrical field over the silicon dioxide insulation layer in which the floating gate is embedded, a marked reduction in the leakage currents can be expected if the electrical fields are successfully reduced to a large extent in the zero-current state of the semiconductor memory configuration. As a consequence, the threshold voltages VT in the high VT state and in the low VT state of the transistor should also be as low as possible. The threshold voltages are known to stipulate the memory state of the transistor by virtue of high VT and low VT logic states being assigned to “0” and “1”, or vice-versa.

[0004] Another general problem with nonvolatile semiconductor memory configurations is that identical memory cells can have different programming speeds due to variations in technology, for example, when they are manufactured. As a result, different threshold voltages may arise for the transistors in these memory cells.

[0005] When reading nonvolatile semiconductor memory configurations, the aforementioned logic states high VT or high threshold voltage and low VT or low threshold voltage of the transistor need to be distinguished for each of the individual cells. For reliable reading, the difference between the two threshold voltages high VT and low VT should be as large as possible. The difference cannot be increased arbitrarily, however, because the level of the high VT , i.e., the high threshold voltage, state is determined by the negative (for NMOS) or positive (for PMOS) quantity of charge that can be applied to the floating gate of the transistor, and hence is limited by the available voltages. The difference cannot be increased arbitrarily also because the low threshold voltage low VT must always be higher than 0 V (for NMOS) or lower than 0 V (for PMOS) due to the fact that the transistor would otherwise be normally on, even when not selected.

[0006] For the aforementioned leakage current problem, there is still no satisfactory solution at present. The only factor being considered is the use of a UV shift, i.e., raising the threshold voltage in the zero-charge state, that is to say, after discharge by UV irradiation, to reduce electrostatic fields over the oxide insulation layer.

[0007] Different programming speeds of the individual memory cells can be allowed for, per se, by intelligent programming, where each memory cell is allocated its required threshold voltage. However, such a procedure is extremely time consuming and requires greater effort for construction and in the peripheral area.

[0008] Negative (for NMOS) or positive (for PMOS) threshold voltages for low VT can be prevented by using the aforementioned intelligent programming to check the respective threshold voltage reached to prevent it from falling below (for NMOS) or rising above (for PMOS) the 0 V limit. Such intelligent programming places additional demands on the construction of the circuit. Finally, connecting a selection transistor upstream in addition to the transistor can also prevent a flow of current, even if the transistor, that is to say the actual memory cell, is over-programmed and becomes normally on. Such an additional selection transistor significantly increases the chip area required, however, and is, therefore, extremely cost intensive.

SUMMARY OF THE INVENTION

[0009] It is accordingly an object of the invention to provide a method for reading nonvolatile semiconductor memory configurations that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that, while overcoming the leakage current problem, ensures a large difference between the threshold voltages, of which low VT can even assume negative (for NMOS) or positive (for PMOS) values.

[0010] The objectives of the invention are achieved by applying a reverse bias between the bulk and the source of the transistor.

[0011] With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for reading non-volatile semiconductor memory configurations including determining a high threshold and a low threshold voltage based on a charge state of a floating gate for a transistor, and applying a reverse bias between a bulk and a source of the transistor during reading.

[0012] In accordance with another mode of the invention, the low threshold voltage is allowed to assume negative voltage values for NMOS transistors and to assume positive voltage values for PMOS transistors.

[0013] In accordance with a further mode of the invention, applying the reverse bias expands the window between the high threshold voltage and the low threshold voltage.

[0014] In accordance with an added mode of the invention, the window between the high threshold voltage and the low threshold voltage is left constant by applying the reverse bias.

[0015] In accordance with an additional mode of the invention, by applying the bias, a threshold voltage for NMOS transistors is shifted by Y({square root}{square root over (−VSB+2Φf)}−{square root}{square root over (2Φf)}) and a threshold voltage for PMOS transistors is shifted by −Y({square root}{square root over (VSB−2Φf)}−{square root over (−2Φf)}) by applying the bias, where γ is the substrate control factor and φf is the Fermi voltage of the bulk.

[0016] The inventive method for reading memory cells in a nonvolatile semiconductor memory configuration is based on the utilization of the substrate control effect, described as follows: when a reverse bias VSB is applied between the bulk and the source of an NMOS or PMOS transistor, the threshold voltage thereof is shifted by:

γ({square root}{square root over (−VSB+2φf)}−{square root}{square root over (2φf)}),

[0017] where VSB<0 and φf>0 for NMOS, and

−γ({square root}{square root over (VSB−2φf)}−{square root}{square root over (−2φf)}),

[0018] where VSB>0 and φf<0 for PMOS, γ=substrate control factor, and φf=Fermi voltage of the bulk, that is to say, Fermi voltage of p-conductive or n-conductive silicon.

[0019] Thus, applying the reverse bias VSB between the bulk and the source allows an inherently normally-on memory cell having a negative (for NMOS) or positive (for PMOS) threshold voltage for a bulk voltage of 0 V to be off even with a positive (for NMOS) or negative (for PMOS) gate voltage.

[0020] In accordance with a concomitant mode of the invention, the drain and the source of the transistor are each placed at different potentials when the reverse bias has been applied.

[0021] The method according to the invention allows a series of significant advantages that cannot be readily achieved with the prior art.

[0022] First, if the distance between the high threshold voltage high VT and the low threshold voltage low VT, that is to say, the VT window, is left the same, then the high threshold voltage high VT can be lowered. Accordingly, if no external voltages are applied to the semiconductor memory configuration, a smaller electrical field exists over the silicon dioxide insulation layer in the high threshold voltage high VT state, which results in smaller leakage currents, in other words, in a lower leakage current susceptibility.

[0023] Second, lowering the relatively high threshold voltage high VT has the advantage that lower voltages are sufficient for the transfer to the high VT state in the transistor, which permits information to be erased in a memory cell array using relatively low voltages.

[0024] Third, the state of the low threshold voltage low VT is no longer limited by 0 V. Thus, negative (for NMOS) and positive (for PMOS) threshold voltages also become possible, which results in an increase in the size of the VT window when the high threshold voltage high VT is retained. Thus, relatively high cycle numbers can be achieved for the semiconductor memory configuration or its memory cells.

[0025] Fourth, the relatively large VT window or the relatively large difference between the high threshold voltage high VT and the low threshold voltage low VT allows, for example, technology-related variations in the threshold voltage to be tolerated for the low VT state and/or for the high VT state within a certain frame. Accordingly, it is possible to dispense with monitoring the threshold voltage during programming, which permits a simpler circuit construction. Intelligent programming both allows exact setting of the threshold voltage and makes it possible to prevent a normally-on state. The exact setting of the threshold voltage prevents variations due to different programming speeds.

[0026] Fifth, an enlarged VT window results in improved applications for the nonvolatile semiconductor memory configuration with more levels because the individual states arising in the place of high VT and low VT are more reliable to read. For example, a 2-bit cell can have four states.

[0027] Sixth, an enlarged VT window results in a higher level of cycle stability.

[0028] Seventh, biasing the source/bulk and the drain/bulk diodes of the transistor reduces the depletion layer capacitances, which is equivalent to reducing the bit line capacitances and the source line capacitances and, therefore, permits higher switching speeds.

[0029] In the inventive method for reading nonvolatile semiconductor memory configurations, a reverse bias is applied between the bulk and the source of the transistor in a memory cell. In addition, a positive (for the NMOS) or negative (for PMOS) source or drain voltage is applied so that the drain and the source are no longer at the same potential.

[0030] Therefore, an entirely crucial factor for reading is that the source and the drain are not at the same potential. In such a context, only relative voltages are of significance for a memory cell. If, however, an entire memory cell array is considered, then there are certainly differences. The table below indicates possible variants of reading voltages for an NMOS cell, where VS, V'S, are the source voltage, Vd is the drain voltage, and VB, V′B, are the bulk voltage:

Variant Source (S) Drain (D) Bulk (B)
(1) 0 V VD VB
(2) VS VD + VS 0 V
(3) VS + V′B VD + VS + V′B V′B

[0031] In such a context, the following relationships are true:

VB<0 V,

VS≈−VB, and

VB<V′B<0 V.

[0032] The above three voltage variants (1) to (3) represent identical conditions from the standpoint of the memory cell because the relative voltages between the electrodes S, D, B are the same. If, however, the whole memory is considered, then no bulk voltage need be applied for the variant (2). This means that, for the technology, a triple well can be dispensed with in the case of a p-doped base material, for example. If the capacitances whose charges need to be reversed when the reading conditions are set are considered, then variant (2) or, under some circumstances, a combination of variants (1) and (2), as is outlined in variant (3), is advantageous because relatively low depletion layer capacitances are present with biased pn junctions (cf. above). The presence of the source or drain voltage brings the substrate control effect to bear. As simulations have shown, the method according to the invention can prevent a drain current that would otherwise arise for conventional reading of the semiconductor memory configuration. Simulation likewise shows that, despite the low threshold voltage low VT shifted by the substrate control effect, a sufficient current still flows with a memory cell selected in the semiconductor memory configuration.

[0033] Other features that are considered as characteristic for the invention are set forth in the appended claims.

[0034] Although the invention is illustrated and described herein as embodied in a method for reading nonvolatile semiconductor memory configurations, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

[0035] The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0036]FIG. 1 is a partial, cross-sectional illustration of an NMOS memory transistor or a memory cell in the semiconductor memory configuration;

[0037] FIGS. 2 to 5 are partial, cross-sectional illustrations of well structures for memory transistors suitable for applying a bulk bias;

[0038]FIG. 6 is a curve illustrating the drain current ID as a function of the voltage on the control gate for the NMOS memory transistor of FIG. 1;

[0039]FIG. 7 is a schematic circuit diagram illustrating the method according to the invention;

[0040]FIG. 8 is a curve illustrating the drain current ID as a function of the voltage VCG on the control gate when a reverse bias is applied to the bulk; and

[0041]FIG. 9 is a graph illustrating the improvement in the cycle stability by the method according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] In all the figures of the drawing, sub-features and integral parts that correspond to one another bear the same reference symbol in each case.

[0043] Referring now to the figures of the drawings in detail and first, particularly to FIG. 1 thereof, there is shown a schematic cross-sectional illustration of a transistor as a memory cell in a nonvolatile semiconductor memory configuration. The transistor includes an n-conductive source zone S and an n-conductive drain zone D in a p-conductive semiconductor body or bulk B.

[0044] Above the channel region, the transistor shown in FIG. 1 also has a floating gate FG and a control gate CG, to which a control voltage VCG is applied. The source S and the drain D have a voltage VS and VD, respectively, applied to them, while a voltage VB is applied to the bulk B.

[0045] The indicated conduction types may, if appropriate, also be respectively reversed so that a p-channel MOS transistor (PMOS) is provided instead of the illustrated n-channel MOS transistor (NMOS). In such a configuration, an n-conductive bulk B then holds a p-conductive drain zone D and a p-conductive source zone S.

[0046] Various well structures for NMOS memory cells are shown in FIGS. 2 and 3, and various well structures for PMOS memory cells are shown in FIGS. 4 and 5. Thus, for its part, the bulk B in an NMOS memory cell may also be nested, as a p-conductive well p-well, in an n-conductive well n-well in a p-conductive silicon substrate to insulate it from adjacent memory cells, with a voltage of 0 V then being applied to the n-conductive well n-well (cf. FIG. 2). A corresponding well structure for a PMOS memory cell is shown in FIG. 4. FIGS. 3 and 5 show well structures in which the bulk is provided as a p-conductive well in an n-conductive substrate (cf. FIG. 3) or as an n-conductive well in a p-conductive substrate. Other well structures are also possible, of course.

[0047] The memory transistor shown in FIG. 1 has—like the variants indicated in FIGS. 2 to 5—different threshold voltages high VT and low VT based on the electrical charge stored in its floating gate FG, the threshold voltages each having an associated drain current ID based on the voltage VCG applied to control gate CG, as shown in FIG. 6. The window between the threshold voltages is ΔVT1.

[0048] For NMOS transistors, negative values of the voltage VCG cannot be used because the transistor is normally on. The same applies for positive values of the voltage VCG in PMOS transistors.

[0049] According to the invention indicated schematically in FIG. 7, a negative reverse bias VSB=VB−VS<0 is applied between the bulk B and the source S of the NMOS transistor. In a PMOS transistor, a positive reverse bias VSB=VB−VS>0 is applied accordingly between the bulk B and the source S. The negative (for NMOS) or positive (for PMOS) source/bulk bias shifts the threshold voltage VT by γ({square root}{square root over (−VSB+2φf)}−{square root}{square root over (2φf)}) for NMOS, as in the illustrative embodiment shown, for example, in FIG. 8, and by −γ({square root}{square root over (VSB−2φf)}−{square root}{square root over (−2φf)}) for PMOS.

[0050] As can be seen from FIG. 8, the shift in the threshold voltages low VT and high VT moves the window between the threshold voltages from ΔVT1. The shift allows the upper threshold voltage high VT to be lowered. The lowering ability has the advantage of providing a lower susceptibility to leakage current because there is a smaller electrical field in the oxide insulation layer.

[0051] If appropriate, the window ΔVT can also be expanded to permit a higher cycle number. Other advantages that can be achieved with the larger window ΔVT have already been indicated above. The enlargement of the window with ΔVT 2>ΔVT1 is obtained when an unshifted negative threshold voltage is permitted.

[0052]FIG. 9 illustrates the gain in cycle stability as a result of expanding the window ΔVT1 for conventional reading to the window ΔVT2 for reading based on the method according to the invention. It is clearly seen that the number of cycles can be significantly increased when the method according to the invention is used.

Referenced by
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US7379317Dec 23, 2004May 27, 2008Spansion LlcMethod of programming, reading and erasing memory-diode in a memory-diode array
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Classifications
U.S. Classification365/185.18, 365/185.24
International ClassificationG11C16/04, G11C16/26
Cooperative ClassificationG11C16/0416, G11C16/26
European ClassificationG11C16/04F1, G11C16/26
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Dec 12, 2013FPAYFee payment
Year of fee payment: 12
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May 7, 2002ASAssignment
Owner name: INFINEON TECHNOLOGIES AG, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VON SCHWERIN, ANDREAS GRAF;KOWARIK, OSKAR;SCHULER, FRANK;REEL/FRAME:012892/0863;SIGNING DATES FROM 20010303 TO 20010411
Owner name: INFINEON TECHNOLOGIES AG PATENTABTEILUNG ST.-MARTI
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Owner name: INFINEON TECHNOLOGIES AG PATENTABTEILUNG ST.-MARTI