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Publication numberUS20020021546 A1
Publication typeApplication
Application numberUS 09/846,986
Publication dateFeb 21, 2002
Filing dateMay 1, 2001
Priority dateJan 13, 1994
Also published asUS6052271, US6229168, US6232629, US6278146, US6437966, US6495872, US6794243, US6998323, US7075773, US20010001208, US20010002708, US20010022374, US20010036055, US20030209749, US20060007635
Publication number09846986, 846986, US 2002/0021546 A1, US 2002/021546 A1, US 20020021546 A1, US 20020021546A1, US 2002021546 A1, US 2002021546A1, US-A1-20020021546, US-A1-2002021546, US2002/0021546A1, US2002/021546A1, US20020021546 A1, US20020021546A1, US2002021546 A1, US2002021546A1
InventorsTakashi Nakamura
Original AssigneeRohm Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Ferroelectric capacitor and a mehtod for manufacturing thereof
US 20020021546 A1
Abstract
It is an object of the present invention to provide a ferroelectric capacitor which maintains high ferroelecticity. A silicon oxide layer 2, a lower electrode 12, a ferroelectric layer 8 and an upper electrode 10 are formed on a silicon substrate 2. The lower electrode 12 is formed by an alloy layer made of iridium and platinum. The alloy layer of the lower electrode 12 can be formed under appropriate lattice constant correspond with a kind and composition of the ferroelectric layer 8. So that, a ferroelectric layer having excellent ferroelectricity can be obtained. Also, it is possible to prevent vacancy of oxygen in the ferroelectric layer 8.
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Claims(19)
What is claimed is:
1. A ferrolectric capacitor comprising:
a) a substrate of semiconductor;
b) a lower electrode located on the substrate of semiconductor, having an alloy layer made of platinum and iridium;
c) a ferroectric layer formed on the lower electrode contacting with the alloy layer of the lower electrode;
d) an upper electrode formed on the ferroelectric layer.
2. A ferroelectric capacitor comprising:
a) a substrate of semiconductor;
b) a lower electrode formed on the substrate of semiconductor, having an iridium layer;
c) a ferroelectric layer formed on the lower electrode, contacting with the iridium layer of the lower electrode;
d) an upper electrode formed on the ferroelectric layer.
3. A ferroelectric capacitor in accordance with claim 1 or claim 2, wherein the lower electrode is located on the silicon oxide layer formed on the substrate of semiconductor, and the lower electrode having a buffer layer contacting with the silicon oxide layer under the alloy layer or the iridium layer.
4. A method for manufacturing a ferroelectric capacitor, comparing the steps of:
a) step for forming a lower electrode on a substrate of semiconductor by an alloy layer made of platinum and iridium, or an iridium layer using sputtering;
b) step for carrying out thermal treatment to the lower electrode in above 700 C;
c) step for forming a ferroelectric layer contacting on the alloy layer;
d) step for forming an upper electrode on the ferroelectric layer.
5. A method for manufacturing a ferroelectric capacitor, comparing the steps of:
a) step for forming a silicon oxide layer on A substrate of semiconductor;
b) step for forming a buffer layer on the silicon oxide layer;
c) step for forming a lower electrode on a titanium layer by an alloy layer made of platinum and iridium, or an iridium layer;
d) step for carrying out thermal treatment to the lower electrode in above 700 C;
e) step for forming a ferroelectric layer on the lower electrode;
f) step for forming an upper electrode on the ferroelectric layer.
6. A method for manufacturing a ferroelectric capacitor in accordance with claim 4 or claim 5, wherein the step for carrying out thermal treatment is also served as thermal treatment for forming the ferroelectric layer.
7. A ferrolectric capacitor comprising:
a) a substrate of semiconductor;
b) a lower electrode located on the substrate of semiconductor;
c) a ferroelectric layer forming on a lower electrode;
d) an upper electrode formed on the ferroelectric layer
characterized by that
at least either one of the lower electrode or the upper electrode comprises an iridium oxide layer.
8. A ferroelctric capacitor in accordance with claim 7, wherein a silicon oxide layer is located between the substrate of semiconductor and the lower electrode.
9. A ferroelectric capacitor in accordance with claim 8, wherein a buffer layer is located between the silicon oxide layer and the lower electrode.
10. A ferroelectric capacitor in accordance with claim 7, claim 8 or claim 9, wherein the lower electrode is made of the iridium oxide layer and the iridium layer or the platinum layer formed thereon.
11. A method for manufacturing a ferroelectric capacitor,
comprising steps of:
a) step for forming a lower electrode on a substrate of semiconductor;
b) step for forming a ferroelectric layer on the lower electrode;
c) step for forming an upper electrode on the ferroelctric layer;
characterized by that
at least either one of the step for forming the lower electrode or the step for forming the upper electrode is contained into a step for forming the iridium oxide layer by sputtering.
12. A ferroelctric capacitor in accordance with claim 7, wherein at least either one of the lower electrode or the upper electrode comprises an iridium oxide layer formed by oxidize the iridium layer and upper part of the iridium layer.
13. A ferroelectric capacitor in accordance with claim 12, wherein a silicon oxide layer is located between the substrate of semiconductor and the lower electrode.
14. A ferroelectric capacitor in accordance with claim 13, wherein a buffer layer is located between the silicon oxide layer and the lower electrode.
15. A method for manufacturing a ferroelectric capacitor,
comprising steps of:
a) step for forming a lower electrode on a substrate of semiconductor;
b) step for forming a ferroelctric layer on the lower electrode;
c) step for forming an upper electrode on the ferroelectric layer;
characterized by that
at least either one of the step for forming the lower electrode or the step for forming the upper electrode is contained into a step for forming an iridium layer by sputtering and then a step for forming the iridium oxide layer at least on surface of the iridium oxide layer.
16. A ferroelectric capacitor comprising:
a) an under layer made of poly silicon layer, poly silicide layer or tungsten layer;
b) an iridium oxide layer located on the under layer;
c) an iridium layer or a platinum layer located on the iridium oxide layer;
d) a high dielectric constant thin film or a ferroelctric layer located on the iridium layer or the platinum layer;
e) an upper layer located on the high dielectric constant thin film or the ferroelctric layer.
17. A ferroelctric capacitor in accordance with claim 16, wherein the iridium layer is located between the under layer and the iridium oxide layer.
18. An nonvolatile memory device comprising:
a) a silicon substrate formed a source region and a drain region wherein;
b) a silicon oxide layer located on a channel region formed between the source region and the drain region in the silicon substrate;
c) an upper layer formed on the silicon oxide layer, made of a poly silicon layer, a poly silicide layer or a tantalum layer;
d) an iridium oxide layer formed on the under layer;
e) an iridium layer or a platinum layer formed on the iridium oxide layer;
f) a high dielectric constant thin film or a ferrolectric layer formed on the platinum layer or the iridium layer;
g) an upper electrode formed on either the high dielectric constant thin film or the ferrolectric layer.
19. A ferroelectric capacitor comprising:
a) an under layer made of a poly silicon layer, a poly silicide layer or a tungsten layer;
b) a middle layer located on the under layer contained
at least an iridium oxide layer;
c) a high dielectric constant thin film or a ferroelectric layer located on the middle layer;
d) an upper electrode located on the high dielectric constant thin film or the ferroelectric layer.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a ferroelectric capacitor, more specifically, a ferroelctric capacitor which is improved ferroelectricity.

[0003] 2. Description of the Prior Art

[0004] A conventional ferroelectric capacitor is shown in FIG. 1. A silicon oxide layer 4 is formed on a silicon substrate 2, then a lower electrode 6 made of platinum is formed thereon. A PZT (PbZrxTi1-xO3) layer 8 as a ferroelectric layer is formed on the lower layer 6. Further, an upper layer 10 made of platinum is formed thereon. So that, a ferroelectric capacitor is formed by the lower electrode 6, the PZT layer 8 and the upper electrode 10.

[0005] The reason why the lower electrode 6 is made by platinum is as follows. The PZT layer 8 must be formed on a layer which is oriented axially or which has mono-crystal for obtaining better matching of lattice constant. When the PZT layer 8 is formed on an amorphous layer, ferroelectricity of the PZT layer is decreased because the amorphous layer is a layer which is not oriented axially. On the other hand, the lower electrode 6 must be formed under insulated condition from the silicon substrate 2. So that, the silicon oxide layer 4 is formed on the silicon substrate 2. Also the silicon oxide layer 4 is made of amorphous. Generally, a layer formed on amorphous becomes as a layer which is not oriented axially. However, platinum has a characteristics that becomes a layer which is oriented axially even when it is formed on amorphous. Therefore, platinum is utilized for the lower electrode 6.

[0006]FIG. 3A illustrates a structure of a memory device which is proposed by using a ferroelectric capacitor. A source region 104 and a drain region 106 are formed in the silicon substrate 102, a gate electrode 108 is formed on the channel region. A plug 110 made of poly silicon is formed on the drain region 106 of this transistor structure. Further, a platinum layer 112 is formed on the poly silicon plug 110, also PZT layer 114 is formed thereon as ferroelectic material. Further, a platinum layer 116 is formed on the PZT layer 114. So that, the memory device is formed.

[0007] Because of manufacturing process of PZT is totally different from that of transistor, the platinum layer 112, PZT layer 114, the platinum layer 116 are formed on the poly silicon plug 110 as shown in the figure.

[0008] The conventional ferroelectric capacitor shown in FIG. 1 has following issues to resolve. At first, it is depending on kind and composition of the ferroelectric material, a possibility of mismatching for lattice constant between the ferroelectric material and the platinum layer formed as the lower electrode is increased, so that ferroelectricity of the capacitor is possibly degraded.

[0009] Subsequently, platinum has a characteristics that oxygen goes though it easily, so that oxygen contained in the ferroelectric material (such as PZT) leaks therefrom. Therefore, degradation for retention property and fatigue property beside repeated polarization reverse is caused. That is, oxygen contained in the ferroelectric material leaks through columnar crystal structure of platinum as shown in FIG. 2.

[0010] It is necessary to resolve following issues to realize a conventional memory device shown in FIG. 3A.

[0011] In FIG. 3A, the platinum layer 112 is formed directly on the poly silicon plug 110. So that, platinum and poly silicon cause chemical reaction, then silicide is formed. Once silicide is formed, it is not possible to obtain high ferroelectricity. Even if a ferroelectric layer is formed thereon, because of lattice constant between silicide and the ferroelectric layer is totally different each other. Also, since surface of the poly silicon plug 110 has roughness, platinum formed on the poly silicon plug 110 can not be oriented. Therefore, the ferroelectric layer formed thereon does not have high ferroelectricity. FIG. 3B shows a hysteresis curve of PZT formed on platinum which is formed on poly silicon. As it is clear from the figure, remanent polarization Pr is almost disappeared from the figure. The same issue is observed when tungsten is used as the plug.

[0012] To resolve above described problems, there is a case that a tantalum layer which does not react with the platinum layer 112 is formed on the poly silicon plug 110, then the platinum layer 112 is formed thereon. According to above way, it is possible to prevent forming polycide as a result of chemical reaction of platinum and poly silicon, also better ferroelectricity can be observed due to improvement of orientation for the ferroelectric layer. However, surface of the tantalum layer 113 maintains roughness of the surface of the poly silicon plug 110, as shown in FIG. 4A. Therefore, platinum formed thereon can not be oriented axially. So that, the ferroelectric layer formed on the platinum does not have high ferroelectricity. Also, there is a issue that tantalum oxide is formed in a boundary between the poly silicon plug 110 and the tantalum layer 113 caused by thermal treatment. Therefore, dielectric constant of the memory device is decreased.

SUMMARY OF THE INVENTION

[0013] It is an object of the present invention to provide a ferroelectric capacitor which realizes less degradation for retention property and fatigue property beside repeated polarization reverse.

[0014] Also, another object of the present invention is to provide a ferroelectric capacitor maintains high ferroelecticity, less degradation for retention property, fatigue property and repeated polarization reverse.

[0015] Far another object of the present invention is to provide a dielectric capacitor and memory device having excellent characteristics.

[0016] A ferrolectric capacitor comprises:

[0017] a) a substrate of semiconductor;

[0018] b) a lower electrode located on the substrate of semiconductor, having an alloy layer made of platinum and iridium;

[0019] c) a ferroectric layer formed on the lower electrode contacting with the alloy layer of the lower electrode;

[0020] d) an upper electrode formed on the ferroelectric layer.

[0021] While the novel features of the invention are set forth in a general fashion, both as to organization and content, will be better understood and appreciated, along with other objections and features thereof, from the following detailed description taken in conjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1 is a view illustrating a structure of conventional ferroelectric capacitor.

[0023]FIG. 2 is a view illustrating concept for oxygen goes through from the lower electrode 6 made of platinum layer.

[0024]FIG. 3A is a view illustrating a structure of memory device utilizing a conventional ferroelectric capacitor.

[0025]FIG. 3B is a view illustrating a characteristics of ferroelectric material when a platinum layer is formed on poly silicon.

[0026]FIG. 4A is a view illustrating a concept for a tantalum layer formed on poly silicon.

[0027]FIG. 4B is a view illustrating a concept for an iridium oxide layer formed on poly silicon.

[0028]FIG. 5 is a view illustrating a structure of ferroelectric capacitor for an embodiment in the present invention.

[0029]FIG. 6 is a view illustrating characteristics of both platinum and iridium.

[0030]FIG. 7 is a view illustrating crystal face of platinum and iridium.

[0031]FIG. 8 is a view illustrating a structure to prevent leakage of oxygen by iridium oxygen layer in alloy of platinum and iridium.

[0032]FIG. 9 is a view illustrating a nonvolatile memory device utilized a ferroelectric capacitor 22.

[0033]FIG. 10A to FIG. 10D are the view illustrating manufacturing process of ferroelectric capacitor shown in FIG. 5.

[0034]FIG. 11 is a view illustrating variation for remanent polarization Pr and coercive field Ec when con ration of platinum and iridium is changed.

[0035]FIG. 12A and FIG. 12B are the view illustrating comparison hysteresis characteristics when utilize platinum for the lower electrode or utilize alloy of platinum and iridium for the lower electrode.

[0036]FIG. 13A is a view illustrating a hysteresis characteristics of the lower electrode made of iridium.

[0037]FIG. 13B is a view illustrating a structure to carry out a test shown in FIG. 13A.

[0038]FIG. 14 is a view illustrating an embodiment when forming a buffer wafer 30 between the lower electrode 12 and silicon oxide layer 4.

[0039]FIG. 15A and FIG. 15B are the view illustrating a hysteresis characteristics when utilize the iridium layer, the platinum layer as the buffer layer.

[0040]FIG. 16 is a view illustrating a structure of ferroelectric capacitor for an embodiment in the present invention.

[0041]FIG. 17 is a view illustrating a graph shows a result that proving iridium oxide is not influenced by orientation of a under layer.

[0042]FIG. 18A to FIG. 18D are the view illustrating manufacturing process of ferroelectric capacitor.

[0043]FIG. 19 is a view illustrating a graph shows variation of remanent polarization Pr.

[0044]FIG. 20 is a view illustrating a graph shows variation of remanent polarization Pr.

[0045]FIG. 21 is a view illustrating a graph shows a voltage applied to carry out fatigue test.

[0046]FIG. 22 is a view illustrating a structure for carrying out fatigue test.

[0047]FIG. 23A is a view illustrating a graph shows variation of remanent polarization Pr when the platinum layer is formed on the iridium oxide layer.

[0048]FIG. 23B is a view illustrating a graph shows variation of remanent polarization Pr when the platinum layer is formed on the iridium oxide layer.

[0049]FIG. 24 is a view illustrating a structure of forming a buffer layer 30 between the lower electrode 13 and silicon oxide layer 4 for an embodiment in the present invention.

[0050]FIG. 25 is a view illustrating a structure of ferroelectric capacitor for an embodiment in the present invention.

[0051]FIG. 26 is a view illustrating a structure for preventing leakage of oxygen by an iridium oxide layer 33.

[0052]FIG. 27A to FIG. 27D are the view illustrating manufacturing process of ferroelectric capacitor.

[0053]FIG. 28 is a view illustrating a graph shows variation of remanent polarization Pr.

[0054]FIG. 29 is a view illustrating a graph shows variation of remanent polarization Pr.

[0055]FIG. 30 is a view illustrating a structure of forming a buffer layer 34 between the lower electrode 32 and silicon oxide layer 4 for an embodiment in the present invention.

[0056]FIG. 31 is a view illustrating a structure of memory device utilizing a ferrolectric capacitor for an embodiment in the present invention.

[0057]FIG. 32 is a view illustrating a structure for carrying out a characteristics of the ferroelectric capacitor.

[0058]FIG. 33 is a view illustrating a graph shows a hysteresis characteristics of the ferroelectric capacitor.

[0059]FIG. 34A and FIG. 34B are the view illustrating graphs showing capacitance measured between point a and point b in FIG. 33, and capacitance measured between point a and point c in FIG. 33.

[0060]FIG. 35 is a view illustrating a structure of nonvolatile memory for an embodiment in the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0061] A structure of an embodiment for a ferroelectric capacitor in the present invention will be disclosed in FIG. 5. In this embodiment, a silicon oxide layer 4, a lower electrode 12, a ferroelectric layer 8 and an upper electrode 10 are formed on a silicon substrate 2. The lower electrode 12 is made of alloy of platinum and iridium.

[0062] Characteristics of platinum and iridium are shown in FIG. 6 by comparison. As it is clear from the figure, characteristics of iridium is almost the identical to characteristics of platinum. Iridium is suitable material for electrodes; because of resistivity of iridium is lower than platinum. Also, lattice constant of platinum is 3.923 Å, in the meantime, lattice constant of iridium is 3.839 Å. So that, it is possible to set the value of lattice constant for alloy of platinum and iridium between 3.923 Å to 3.839 Å. That is, optimum lattice constant is obtainable depending on kind and composition of the ferroelectric material.

[0063] For instance, the ferroelectric layer 8 by using bismuth titanate (Bi4Ti3O12) (hereinafter referred as BIT) will be disclosed. Lattice constant of BIT consist of a=5.45, b=5.41 and c=32.815. On the contrary, platinum and iridium used as the lower electrode 12 is oriented toward direction (111) as shown in FIG. 7. So that, it is necessary to equalize a band length L on the (111) axis of the lower electrode 12 to a=5.45 or b=5.41 to obtain a layer which is oriented toward c axis of BIT. In this embodiment, band length L can be 5.43 on (111) axis by making a composition ratio of the alloy for platinum and iridium as x=0.8 in Ptx Ir1-x. That is, a BIT layer having high ferroelectricity can be formed by carrying out matching among the lattice constant of BITs.

[0064] Although, platinum has a characteristics that hard to react with oxygen, iridium can be oxidized under high temperature as shown in a chart of FIG. 6. Therefore, iridium can be oxidized slightly when thermal treatment is carried out to alloy of platinum and iridium. An iridium oxide layer 20 is formed between columnar crystal of platinum, so that the iridium oxide layer 20 blocks a path where oxygen go through. As a result, it is possible to prevent vacancy of oxygen in the PZT layer 8 (see FIG. 8).

[0065] The ferroelectric capacitor thus formed as disclosed above can be applied to an nonvolatile memory device with combination of a transistor 24 as shown in FIG. 9.

[0066] Manufacturing process of a ferroelectric capacitor for an embodiment in the present invention will be disclosed from FIG. 10 A to FIG. 10D. Initially, a silicon oxide layer 4 is formed by thermal oxidizing surface of a silicon substrate 2 (FIG. 10A). Here, the silicon oxide layer 4 is formed in thickness of 600 nm. Then, alloy of platinum and iridium is formed on the silicon oxide layer 4 by utilizing the platinum and the iridium as a target (FIG. 10B). The alloy of platinum and iridium is used as a lower electrode 12 and the electrode is formed in thickness of 200 nm.

[0067] Subsequently, a PZT layer is formed on the lower electrode 12 as a ferroelectric layer 8 by sol-gel method (FIG. 10C). In this embodiment, solution mixture of PB(CH3COO)23H2O, Zr(t-OC4 H9)4, Ti(i-OC3 H7)4 is used for a precursor. After carrying out spin coating to the mixture, dry process is carried out at 150 C. Then preanneal is carried out under dry air atmosphere at 400 C. for 30 seconds. Above mentioned process is conducted by five times, then thermal treatment is carried out under oxygen atmosphere at above 700 C. So that, the ferroelectric layer 8 is formed in thickness of 250 nm. In this embodiment, PZT layer is formed under the condition that X is 0.52 in PBZrx Ti1-xO3 (hereinafter referred as PZT (52/48)).

[0068] Further, an upper electrode 10 made of platinum is formed on the ferroelectric layer 8 by sputtering (FIG. 10D). So that, a ferroelectric capacitor can be formed.

[0069] In above disclosed embodiment, iridium is oxidized with the lower electrode 12 when carrying out thermal treatment to form the ferroelectric layer 8 at above 700 C. However, the thermal treatment can be carried out when the lower electrode 12 is formed.

[0070]FIG. 11 is a graph shows variation of remanent polarization Pr and coercive field Ec, when composition ratio x of platinum and iridium is varied by utilizing Pt Ir as the lower electrode 12 and PZT (52/48) as the ferroelectric layer 8. As it is clear from the figure, value of remenent polarization Pr is higher when utilize iridium and platinum to form the lower electrode 12, than only use platinum for the lower electrode 12. That is, ferroelectricity is improved when utilizing the alloy of iridium and platinum for the lower electrode 12. A remarkable improvement can be obtained within a range from 0% to 50% of platinum, particularly excellent improvement is obtained when composition ratio of platinum is approximately 25%.

[0071] A hysteresis characteristics of a ferroelectric capacitor utilizing only platinum for the lower electrode 12 is shown in FIG. 12A. Also, another hysteresis characteristics of a ferroelectric capacitor utilizing alloy of platinum 25% and iridium 75% for the lower electrode 12 is shown in FIG. 12B. Here, thickness of the silicon oxide layer is 600 nm, thickness of the lower electrode is 200 nm and thickness of the PZT layer is 250 nm. In comparison with both graphs shown in FIG. 12A and FIG. 12B, it is clearly understand that the capacitor utilizing alloy (shown in FIG. 12B) shows excellent characteristics of remanent polarization Pr.

[0072] Further, far another hysteresis characteristics of a ferroelectric capacitor utilizing only iridium for the lower electrode 12 is shown in FIG. 13A. Although utilizing only iridium for the lower electrode 12, remanent polarization Pr and coercive field Ec are improved. A result of experiment shown in FIG. 13A is obtained by carrying out an experiment under a structure shown in FIG. 13B.

[0073]FIG. 14 shows a structure of ferroelectric capacitor for another embodiment in the present invention. In this embodiment, a titanium layer is formed between a lower electrode 12 and a silicon oxide layer 4 as a buffer layer 30. Since, adsorption between iridium and the silicon oxide layer 4 is not enough to adhere both of them, so that, ferrolectric characteristics is decreased due to causing partial delamination. Particularly, the issue is noticeable when ratio of iridium in the alloy is heightened. To resolve the issue, in this embodiment, the titanium layer 4 having excellent adsorption with iridium is formed. So that, ferroelectricity can be improved. The titanium layer is formed by sputtering method.

[0074]FIG. 15A shows a hysteresis characteristics when the titanium layer is formed as the buffer layer 30 under the lower electrode 12 made of iridium. Here, the silicon oxide layer is formed in thickness of 600 Å, thickness of the buffer layer is 5 nm, thickness of the lower electrode is 200 nm and thickness of PZT layer is 250 nm. As it is clear from the figure, characteristics of both remanent polarization Pr and coercive field Ec are improved in comparison with the characteristics shown in FIG. 13A.

[0075] Although, the titanium layer is used as the buffer layer 30 in above embodiment, it is possible to use other materials which improves adsorption for instance a platinum layer. Also, FIG. 15B shows a hysteresis characteristics when the platinum layer formed in thickness of 100 nm is used as the buffer layer. As it is clear to compare with FIG. 13A, characteristics of remanent polarization Pr, coercive field Ec are also improved in this embodiment.

[0076] The ferroelectric capacitor in the present invention is characterized to use lower electrode having an alloy layer comprises platinum and iridium. So that, it is possible to match lattice constant by varying composition ratio in correspond with kind or composition of the ferroelectric material. Also, it is possible to prevent vacancy of oxygen in the ferroelectric material by oxidized iridium.

[0077] The ferroelectric capacitor in this embodiment is also characterized to have the buffer layer contact with the silicon oxide layer, formed under the lower electrode. So that, adsorption of the ferroelectric layer can be improved.

[0078] Further, a method for manufacturing a ferroelectric capacitor in the present invention is characterized to comprise a step for forming the lower electrode made of an alloy layer for platinum and iridium or an iridium layer by carrying out thermal treatment to the lower electrode at above 700C. So that, it is possible to prevent vacancy of oxygen in the ferroelectric material due to either of the iridium layer or iridium contained in the alloy layer is oxidized.

[0079] Also, a method for manufacturing a ferroelectric capacitor in the present invention comprises a step for forming the buffer layer attached with the silicon oxide layer, under the lower electrode. So that, adsorption of the ferroelectric layer can be improved.

[0080] Moreover, a method for manufacturing a ferroelectric capacitor in the present invention is characterized to carry out thermal treatment to form a ferroelectric layer which also conducts thermal treatment to the lower electrode. Therefore, it is possible to improve efficiency of production by simplify the processes. That is, in accordance with the present invention, a ferrolectric capacitor having high ferroelectricity can be provided.

[0081]FIG. 16 shows a structure of ferroelectric capacitor for another embodiment in the present invention. In this embodiment, a silicon oxide layer 4, a lower electrode 13, a ferroelectric layer 8 and an upper electrode 15 are formed on a silicon substrate 2. The lower electrode and the upper electrode are made of iridium oxide.

[0082] Characteristics of platinum and iridium are shown in FIG. 6 for comparison. As it is clear from the figure, resistivity of iridium oxide is 4910−6 Ωcm which is suitable material for electrodes.

[0083] Since platinum has columnar crystal structure as shown in FIG. 2 of the conventional embodiment, oxygen contained in the ferroelectric layer 8 can go through the platinum. Therefore, in this embodiment, the lower electrode 13 is formed by iridium oxide. Since the iridium layer does not have columnar crystal structure, it is hard for oxygen to go through the iridium layer. So that, it is possible to prevent vacancy of oxygen in the ferroelectric layer 8. This fact can be applied to the upper electrode 15.

[0084] The iridium oxide layer does not have axis orientation despite of a layer formed underneath (hereinafter referred as the under layer) is oriented axially or not oriented. So that, the ferroelectric layer 8 formed on the iridium oxide layer 8 is not oriented axially.

[0085] Following experiment is carried out to prove the iridium layer does not have axis orientation despite of the under layer is oriented axially or not. Comparison of hysteresis characteristics is conducted between a ferroelectic capacitor which comprises the lower electrode 13 made of iridium oxide formed directly on the silicon substrate 2 and a ferrolectric capacitor which comprises the lower electrode 13 made of iridium oxide formed on the silicon oxide layer 4. Hysteresis characteristics of above ferroelectric capacitors are shown in FIG. 17A and FIG. 17B. FIG. 17A shows the ferroelectric capacitor comprises the lower electrode 13 formed on the silicon oxide layer 4. FIG. 17B shows the ferrolectric capacitor comprises the lower electrode 13 made of iridium oxide formed directly on the silicon substrate 2. As it is clear from the figures, characteristics of the ferroelctric layer 8 is identical despite of the under layer is oriented axially or not oriented. In above experiment, both of the lower electrode 13 and the upper electrode 15 are formed by iridium oxide layer, either one of the electrodes can be formed in other material.

[0086] The ferroelectric capacitor thus formed as disclosed above can be applied to an nonvolatile memory device with combination of a transistor 24 as shown in FIG. 9.

[0087] Manufacturing process of the ferroelectric capacitor for an embodiment in the present invention is shown in FIG. 18A to FIG. 18D. Initially, a silicon oxide layer 4 is formed by carrying out thermal oxidation to surface of a silicon substrate 2 (FIG. 18A). The silicon oxide layer is formed in thickness of 600 nm. A lower electrode 13 is formed by locating an iridium oxide layer on the silicon oxide layer 4 in reactive sputtering method with utilizing the iridium layer as a target (FIG. 18B). Here, the lower electrode 13 is formed in thickness of 200 nm.

[0088] Subsequently, a PZT layer is formed as a ferroelctric layer 8 on the lower electrode 13 by sol-gel method as shown in FIG. 10C (FIG. 18C).

[0089] Further, an upper electrode 15 is formed by locating the iridium oxide layer on the ferroelectric layer 8 by reactive sputtering (FIG. 18D). Here, the upper electrode 15 is formed in thickness of 200 nm. Thus, the ferroelectric capacitor is obtained.

[0090] A fatigue characteristics of remanent polarization Pr for a ferroelectric capacitor when the ferroelectric layer 8 is made of PZT (52/48) is shown in FIG. 19, and FIG. 20. An experiment is carried out with a ferrolectric capacitor under the structure shown in FIG. 22, by applying a voltage between point a and point b. Degradation of remanent polarization Pr is measured by applying a voltage of 5 V to -5 V between the upper electrode 15 and the lower electrode 13. The voltage of 5 V to -5V is defined as one (1) cycle (frequency of the voltage is set at 500 kHz).

[0091] The axis of ordinates of FIG. 19 and FIG. 20 shows value of Pr/Po, when initial remanent polarization is defined as Po and remanent polarization after the fatigue experiment is defined as Pr. The axis of abscissa shows number of cycles for the voltage shown in FIG. 21. In the figures, a curve 50 shows a variety of characteristics when the upper electrode 15 and the lower electrode 13 are both formed by iridium oxide layer. Also a curve 52 shows a variety of characteristics when the upper electrode 15 is made of platinum and the lower electrode 13 is made of iridium oxide layer. Further, a curve 54 shows a variety of characteristics when the upper electrode 15 is made of iridium oxide layer and the lower electrode 13 is made of platinum. A curve 56 shows a variety of characteristics when the upper electrode 15 and the lower electrode 13 are both formed by platinum.

[0092] As it is clear from the figures, degradation of remanent polarization Pr can be improved remarkably when either the upper electrode 15 or the lower electrode 13 is formed by iridium oxide layer. Further, occurrence of degradation can be suppressed until applying the voltage to 10 10 cycle, when both the upper electrode 15 and lower electrode 13 are made of iridium oxide.

[0093] Also, variety of characteristics is shown in FIG. 23A, when the lower electrode 13 made of the iridium oxide layer and the platinum layer formed thereon. Referring to FIG. 23A, Pr, Pmax, P, and N means the characteristics shown in FIG. 23B. As it is clear from the graph, further improvement is accomplished by forming the platinum layer on the iridium oxide layer. That is, only a slight degradation is observed until the voltage cycle reaches to 10 11 cycles.

[0094] It seems that this is due to improvement of ferroelectricity as a result of orientation for the ferroelectric layer 8 by forming the platinum layer thereunder. So that, an iridium layer or an alloy layer of platinum and iridium can be a substitution of the platinum layer.

[0095] A structure of another embodiment for ferroelectric capacitor in the present invention is shown in FIG. 24. In this embodiment, titanium layer (thickness of 5 nm) is formed between the lower electrode 13 and silicon oxide layer 4 as a buffer layer. Since adsorption between the iridium oxide layer and the silicon oxide layer 4 is not enough to adhere both of them. So that, there is a possibility to degrade the ferroelectricity because of partial delamination of the layers. To resolve the issue, in this embodiment, the titanium layer which has better adsorption with the silicon oxide layer 4 is formed as the buffer layer 30. As a result, ferroelectricity of the capacitor is improved. Also, the titanium layer is formed by sputtering method.

[0096] In above disclosed embodiment, although the titanium layer is formed as the buffer layer 30, other material(s) can be a substitution of the titanium layer as long as the material(s) improves adsorption. For instance, a platinum layer can be applicable for the material.

[0097] In above disclosed embodiments, PZT is utilized as the ferroelectric layer 8, any ferroelectric oxide property can be applied to the ferroelectric layer. For instance Bi4Ti3O12 can be utilized for the ferroelectric layer 8.

[0098] Also, the iridium oxide layer is formed by sputtering method in above disclosed embodiments, the iridium oxide layer can be formed by carrying out thermal treatment to iridium.

[0099] The ferroelectric capacitor in the present invention comprises a lower electrode or an upper electrode at least either one of them has an iridium oxide layer. So that, it is possible to prevent vacancy of oxygen in the ferroelctric layer by forming the iridium oxide layer.

[0100] Further, the ferroelectric capacitor in the present invention comprises a lower electrode made of a iridium oxide layer and a platinum layer formed thereon or the platinum layer. So that, ferroelectricity is improved, because of the ferroelectric layer is formed under axis oriented structure.

[0101] Still further, in a method for manufacturing a ferroelectric capacitor in the present invention, a step for forming an iridium oxide layer is included into at least either one of the step for forming a lower electrode or the step for forming an upper electrode. So that, it is possible to prevent vacancy of oxygen in the ferroelectric layer.

[0102] That is, a ferroelectric capacitor having characteristics of less degradation for retention property and fatigue property beside repeated polarization reverse can be obtained.

[0103] A structure of another embodiment for ferroelectric capacitor in the present invention is shown in FIG. 25. In this embodiment, a silicon oxide layer 4, a lower electrode 32, a ferroelectric layer 8 and an upper electrode 35 are formed on a silicon substrate 2. The lower electrode 32 is formed by an iridium layer 31 and an iridium oxide layer 33 formed thereon. Also, the upper electrode 35 is formed by an iridium layer 37 and an iridium oxide layer 33 formed thereon.

[0104]FIG. 26 shows enlarged view adjacent to the lower electrode 32. Since the iridium layer 31 has columnar crystal structures oxygen contained in the ferroelectric layer 8 can go through the iridium layer 31. In this embodiment, the iridium oxide layer 33 is formed on the upper surface of iridium layer 31. Since the iridium oxide layer 33 does not have columnar crystal structure, oxygen can not go through the iridium oxide layer 33 easily. So that, it is possible to prevent vacancy of oxygen. Further, the upper electrode 35 is formed under the same structure as the lower electrode 32, it is also possible to prevent vacancy of oxygen.

[0105] In above embodiment, the iridium oxide layer is formed on both the lower electrode and the upper electrode, the iridium oxide layer can be formed on either one of the electrodes.

[0106] The ferroelectric capacitor thus formed as disclosed above can be applied to an nonvolatile memory device with combination of a transistor 24 as shown in FIG. 9.

[0107] Manufacturing process of the ferroelectric capacitor for an embodiment in the present invention is shown in FIG. 27A to FIG. 27D. Initially, a silicon oxide layer 4 is formed by oxidizing surface of a silicon substrate 2 (FIG. 27A). Here, the silicon oxide layer 4 is formed in thickness of 600 nm. Then, an iridium layer 31 is formed on the silicon oxide layer 4 by utilizing iridium as a target by sputtering. Then, an iridium oxide layer 33 is formed on surface of the iridium layer 31 by carrying out thermal treatment under oxygen atmosphere at 800 C. for one (1) minute. The iridium layer 31 and the iridium oxide layer 33 are used as a lower electrode 32. Here, the lower electrode 32 is formed in thickness of 200 nm.

[0108] Subsequently, a PZT layer is formed as a ferroelectric layer 8 by sol-gel method as shown in FIG. 10C (FIG. 27C).

[0109] Further, an iridium layer 37 is formed on the ferroelectric layer 8 by sputtering then, an iridium oxide layer 39 is formed on surface of the iridium layer 37 by carrying out thermal treatment under oxygen atmosphere at 800 C. for one (1) minute (FIG. 27D). Both the iridium layer 37 and the iridium oxide layer 39 are used as an upper electrode 35. Here, the upper electrode 35 is formed in thickness of 200 nm. Thus, a ferroelectric capacitor is obtained.

[0110]FIG. 28, and FIG. 29 show a fatigue characteristics of remanent polarization Pr for the ferroelectric capacitor when the ferroelectric layer 8 is made of PZT (52/48). Degradation of remanent polarization Pr is measured by applying a voltage of 5 V to -5 V as shown in FIG. 21 between the upper electrode 35 and the lower electrode 32. The voltage of 5 V to 5 V is defined as one (1) cycle (frequency of the voltage is set at 500 kHz).

[0111] The axis of ordinates in FIG. 28 and FIG. 29 show a value of Pr/Po when initial remanent polarization is defined as Po and remanent polarization after the fatigue experiment is defined as Pr. The axis of abscissa shows number for cycle of the voltage shown in FIG. 21. In the figures, a curve 50 shows a variety of characteristics for remanent polarization when the silicon oxide layer is formed in thickness of 600 nm, the lower electrode 32 is formed with both the iridium layer 31 and the iridium oxide layer 33 in thickness of 200 nm, the ferroelectric layer is formed by PZT in thickness of 250 nm and the upper electrode 35 is formed by platinum in thickness of 200 nm. In the meantime, a curve 52 shows a variety of characteristics for remanent polarization when the surface of iridium layer 31 of the lower electrode 32 is not oxidized. Referring to the conditions, other conditions such as kind of layers and thickness of the layers are identical with the condition in the curve 50. Further, a curve 54 shows a variety of characteristics for remanent polarization when the lower electrode 32 is formed by platinum. Also the conditions are identical with the condition in the curve 50.

[0112] As it is clear from the figures, degradation of remanent polarization Pr is improved remarkably when the iridium oxide layer 31 is formed by carrying out oxidation to the surface of iridium layer 31. In this embodiment, a titanium layer is formed in thickness of 5 nm between the lower electrode 32 and the silicon oxide layer 4 as a buffer layer 34. As a result, ferroelectricity of the ferroelectric capacitor can be improved. The titanium layer is formed by sputtering method.

[0113] Although, the titanium layer is used as the buffer layer 34 in above embodiment, it is possible to use other materials as long as the material(s) improves adsorption such as platinum layer.

[0114] In above disclosed embodiment, though PZT is utilized as the ferroelectric layer 8, any other ferroelectric oxide property can be utilized. Such as Bi4Ti3O12 can be a substitution. Also, it is expected to accomplish the same advantages as described above by using ferroelectric properties of fluoride, chloride, bromide as the ferroelectric layer 8.

[0115] A ferroelectric capacitor in the present invention comprises the lower electrode or the upper electrode, at least either one of them are formed by the iridium layer and the iridium oxide layer formed thereon by oxidized the surface of the iridium layer. Therefore, it is possible to prevent vacancy of oxygen.

[0116] In a method for manufacturing a ferroelectric capacitor in the present invention comprises a step for forming the iridium layer by sputtering, and a step for forming the iridium oxide layer thereon by oxidizing at least the surface of iridium layer are included into at least either one of a step for forming the lower electrode or a step for forming the upper electrode. So that, it is possible to prevent vacancy of oxygen in the ferroelectric layer.

[0117]FIG. 31 shows a structure of a memory device for an embodiment in the present invention utilizing a ferroelectric capacitor. A source region 104 and a drain region 106 are formed in a silicon substrate 102, a gate electrode 108 is formed on a channel region. A plug 110 made of poly silicon (or tungsten) is formed as an under layer on the drain region 106 of the device. In the FIG. 31, an insulating layer 118 is formed on the silicon substrate 102.

[0118] An iridium oxide layer 111 is formed on the poly silicon plug 110. The iridium oxide layer 111 can be formed by utilizing iridium as a target by reactive sputtering. As shown in FIG. 4B, the iridium layer 111 has characteristics that the surface is flattened even though condition of the under layer is in rough. Also, resistivity of the iridium oxide layer is 49106 Ωcm, and the iridium oxide layer can be treated as a conductive property.

[0119] A platinum layer 112 is formed on the iridium oxide layer 111. So that, the platinum layer 112 is oriented axially. Then a PZT layer 114 is formed as a ferroelectric material, also a platinum layer 116 is formed thereon as an upper electrode. Thus, a memory device is formed. That is, in this embodiment, a middle layer is formed by the iridium oxide layer 111 and the platinum layer 112.

[0120] In according to this embodiment, the platinum layer 112 does not contact with the poly silicon plug 110 directly. Further, the platinum layer 112 is formed on the iridium oxide layer 111 which has characteristics that the upper surface is flattened even though condition of the under layer is in rough. Therefore, a PZT layer having excellent ferroelectric characteristics can be obtained because of the platinum layer 112 is oriented axially. Also, better characteristics is able to obtained, since a low dielectric oxide is not formed to a boundary between the iridium oxide layer 111 and the poly silicon plug 110.

[0121] An iridium layer or an alloy layer made of platinum and iridium can be a substitution of the platinum layer 112, 116.

[0122] In this embodiment, it is disclosed that when the under layer is made of poly silicon plug 110, exactly the same advantage can be expected when the plug is made of tungsten. Further, the plug can be made by polycide to obtain the advantages disclosed above. Here, polycide is a material which is formed by metal silicide (tungsten silicide, titanium silicide, molybdenum silicide, tantalum silicide or the like) in layer structure. To verify improvement of characteristics for the PZT layer when the platinum layer is formed on the iridium layer, an experiment is carried out under a structure shown in FIG. 32. In the figure, a poly silicon layer 124 is formed on a silicon oxide layer 122 and a silicon substrate 120. An iridium oxide layer 125 a, a platinum layer 126 a, an iridium oxide layer 125 b and a platinum layer 126 b are formed on the poly silicon layer 124, also a PZT layer 128 a, PZT layer 128 b and PZT layer 128 c are formed on thereon. Further, a platinum layer 130 is formed on the PZT layer 128 a as an upper electrode.

[0123] A hysteresis curve measured between point a and point b is shown in FIG. 33A. It is clearly understand that ferroelectricity of PZT layer 128 a is improved tremendously in comparison with the hysteresis curve shown in FIG. 3B.

[0124] Subsequently, FIG. 34A and FIG. 34B are a result of measurement of capacitance when varying an applied voltage between point a and point b, point a and point c. Capacitance between point a and point b is shown in FIG. 34A and capacitance between point a and point c is shown in FIG. 34B. In an assumption, once a low dielectric constant oxide is formed in a boundary between the poly silicon layer 124 and the iridium oxide layer 125 a, 125 b when the layers are formed, capacitance of these layers are supposed to different with each other. However, since capacitance of the layers are almost identical as shown in FIG. 34A and FIG. 34B. So that, it can be estimated that a low dielectric constant oxide is not formed in the boundary.

[0125] An iridium layer can be a substitution of the platinum layer 126 a. FIG. 33A is a hysteresis curve measured between point a and point b when an iridium layer is used instead of the platinum layer 126 a. In this case, an excellent ferroelectricity is indicated.

[0126]FIG. 35 shows a structure of nonvolatile memory device for an embodiment in the present invention. In this embodiment, a source region 160 and a drain region 162 are formed in a silicon substrate 140. A silicon oxide layer 142 is formed on a channel region. 164 which is formed between the source region 160 and the drain region 162. A lower electrode 154 is formed on the silicon oxide layer 142, then a PZT layer 150 is formed thereon as a ferroelectric layer. The PZT layer 150 is formed by sol-gel method as disclosed in FIG. 10C. The PZT layer is formed in thickness of 250 nm, then a platinum layer 152 is formed thereon as an upper electrode.

[0127] The lower electrode 154 comprises a poly silicon layer 144, an iridium oxide layer 146 formed thereon and a platinum layer 148 (iridium layer can be a substitution) formed on the iridium oxide layer 146. The iridium oxide layer 146 can be formed by reactive sputtering.

[0128] An nonvolatile memory device which has excellent characteristics can be obtained, once the nonvolatile memory device is formed as disclosed above. Also, even though thermal treatment in high temperature is carried out to the source region 160 and the drain region 162 for self-alignment purposes, not much oxide is formed in a boundary formed between the poly silicon layer 144 and the iridium oxide layer 146, as far as maintaining above disclosed structure. Further, it is possible to utilize the conventional MOS processes to the processes until forming the silicon oxide layer 142 and poly silicon layer 144 in this embodiment.

[0129] Additionally, once an iridium layer is formed between the poly silicon layer 144 and the iridium oxide layer 146, it is further possible to prevent forming a low dielectric constant property at high temperature thermal treatment. This is due to the iridium layer formed in the boundary is turned out to an iridium oxide layer having conductiveness even if the iridium layer is oxidized.

[0130] Also, in above embodiments, PZT is utilized as a ferroelectric material, any ferroelectric material can be used. For instance, Bi4Ti3O12 is usable. Moreover, a high dielectric constant thin film can be used for DRAM. Especially, a high dielectric constant property having AbO3 structure (perovskite structure) such as SrTiO3,(Sr, Ba)TiO3 or the like is preferable.

[0131] Further, iridium oxide is not formed in columnar structure which is different from platinum, oxygen contained in the ferroelectric layer does not go through iridium oxide. So that, by utilizing iridium has an advantage of preventing degradation of the ferroelectric layer.

[0132] In above embodiments, the middle layers are formed in 2 layers, these layers can be formed in 3 layer structure or more. Once an iridium oxide layer is included in the middle layers when the middle layers are formed, it is possible for the iridium oxide layer to eliminate influences such as orientation or the like caused by a layer formed thereunder to a layer formed thereon. This is due to characteristics of the iridium oxide layer that not be influenced by orientation of the layer formed thereunder.

[0133] A ferroelectric capacitor and an nonvolatile memory device in the present invention comprises a structure of an iridium oxide layer is located on an under layer, then a platinum layer (or an iridium layer) is formed thereon, and a ferroelectric layer (or a high dielectric constant thin film) is formed thereon. Since the platinum layer (or an iridium layer) formed on the iridium oxide layer is oriented axially, so that, quality of the ferroelectric layer (or a high dielectric constant thin film) formed thereon is improved.

[0134] Also, the ferroelectric capacitor in the present invention comprises an iridium layer between the under layer and the iridium oxide layer. To form the iridium layer, a low dielectric property is not formed in a boundary between the iridium layer and the under layer, even though thermal treatment is carried out in high temperature.

[0135] Further, the ferroelectric capacitor in the present invention include an iridium oxide layer in the middle layer. So that, influence of a layer formed underneath the under layer and influence of the iridium oxide layer caused by roughness of grain for the layer are not given to a layer formed on the iridium oxide layer.

[0136] That is, an ferroelectric capacitor and an nonvolatile memory device having excellent characteristics is obtained in the present invention.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7547933Oct 29, 2003Jun 16, 2009Fujitsu Microelectronics LimitedSemiconductor device and manufacturing method of a semiconductor device
US8153448 *May 12, 2009Apr 10, 2012Fujitsu Semiconductor LimitedManufacturing method of a semiconductor device
US8652854 *Mar 12, 2012Feb 18, 2014Fujitsu Semiconductor LimitedManufacturing method of a semiconductor device
US20090280577 *May 12, 2009Nov 12, 2009Fujitsu Microelectronics LimitedManufacturing method of a semiconductor device
US20120171785 *Mar 12, 2012Jul 5, 2012Fujitsu Semiconductor LimitedManufacturing method of a semiconductor device
EP1416526A2 *Oct 30, 2003May 6, 2004Fujitsu LimitedSemiconducteur device and manufacturing method of a semiconductor device
Classifications
U.S. Classification361/305, 257/E21.011, 257/E27.104, 257/E21.021, 257/E21.009
International ClassificationH01L27/115, H01L21/02
Cooperative ClassificationH01L27/11507, H01G4/008, H01L28/65, H01L28/55, H01G4/228, H01L28/75, H01L28/60, H01G4/33, H01L27/11502
European ClassificationH01L28/60, H01L28/75, H01G4/008, H01G4/228, H01G4/33, H01L27/115C4, H01L28/55, H01L28/65, H01L27/115C
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