US 20020021770 A1 Abstract Decoding an encoded signal (for example, a turbo encoded signal, a block encoded signal or the like) is performed by demodulating the received encoded signal to produce soft information, and iteratively processing the soft information with one or more soft-in/soft-output (SISO) modules. At least one of the SISO modules uses a tree structure to compute forward and backward state metrics. More generally, iterative detection is performed by receiving an input signal corresponding to one or more outputs of a module whose soft-inverse can be computed by running the forward-backward algorithm on a trellis representation of the module, and determining the soft inverse of the module by computing forward and backward state metrics of the received input signal using a tree structure.
Claims(90) 1. A decoding method comprising:
receiving an encoded signal; demodulating the received encoded signal to produce soft information; and iteratively processing the soft information with one or more soft-in/soft-output (SISO) modules, at least one SISO module using a tree structure to compute forward and backward state metrics. 2. The method of 3. The method of 4. The method of 5. The method of ^{−|x-y|}). 6. The method of 7. The method of 8. The method of 9. The method of 10. The method of 11. The method of 12. The method of 13. The method of 14. The method of _{2 }N), where N is a block size. 15. The method of 16. The method of 17. The method of 18. The method of tiling an observation interval into subintervals; and
applying a minimum half-window SISO operation on each subinterval.
19. The method of 20. A soft-in/soft-out (SISO) module comprising:
a plurality of fusion modules arranged into a tree structure and adapted to compute forward and backward state metrics, wherein each fusion module is defined by the equation: where C(k, m) is a matrix of minimum sequence metrics (MSM) of state pairs s _{k }and s_{m }based on soft-inputs between s_{k }and s_{m}. 21. The SISO module of 22. The SISO module of 23. The SISO module of 24. The SISO module of ^{−|x-y|}). 25. The SISO module of 26. The SISO module of 27. A soft-in/soft-out (SISO) module comprising:
one or more complete fusion modules (CFMs) for performing marginalization-combining operations in both a forward direction and a backward direction; one or more forward fusion modules (fFMs) for performing marginalization-combining operations only in the forward direction; and one or more backward fusion modules (bFMs) for performing marginalization-combining operations only in the backward direction, wherein the one or more CFMs, fFMs, and bFMs are arranged into a tree structure. 28. The SISO module of 29. The SISO module of 30. The SISO module of 31. The SISO module of 32. The SISO module of ^{−|x-y|}). 33. The SISO module of 34. The SISO module of 35. The SISO module of 36. A method of iterative detection comprising:
receiving an input signal corresponding to one or more outputs of a finite state machine (FSM); and determining the soft inverse of the FSM by computing forward and backward state metrics of the received input signal using a tree structure. 37. The method of 38. The method of 39. The method of 40. The method of 41. The method of ^{−|x-y|}). 42. The method of 43. The method of 44. The method of 45. The method of 46. The method of 47. The method of 48. The method of 49. The method of _{2 }N) , where N is a block size. 50. The method of 51. The method of 52. The method of 53. The method of tiles an observation interval into subintervals; and
applies a minimum half-window SISO operation on each subinterval.
54. A turbo decoder comprising:
a demodulator adapted to receive as input a signal encoded by a finite state machine (FSM) and to produce soft information relating to the received signal; and at least one soft-in/soft-out (SISO) module in communication with the demodulator and adapted to compute a soft-inverse of the FSM using a tree structure. 55. The decoder of 56. The decoder of 57. The decoder of 58. The decoder of _{2 }N), where N is a block size. 59. The decoder of 60. The decoder of 61. A method of iterative detection comprising:
receiving an input signal corresponding to output from one or more block encoding modules; and determining the soft inverse of the one or more block encoding modules by computing forward and backward state metrics of the received input signal using a tree structure. 62. The method of 63. The method of 64. The method of 65. The method of 66. The method of ^{−|x-y|}). 67. The method of 68. The method of 69. The method of 70. The method of 71. The method of 72. The method of 73. The method of 74. The method of 75. The method of 76. The method of 77. The method of tiles an observation interval into subintervals; and
applies a minimum half-window SISO operation on each subinterval.
78. A block decoder comprising:
a demodulator adapted to receive as input a signal encoded by a block encoding module and to produce soft information relating to the received signal; and at least one soft-in/soft-out (SISO) module in communication with the demodulator and adapted to compute a soft-inverse of the block encoding module using a tree structure. 79. The decoder of 80. The decoder of 81. The decoder of 82. The decoder of 83. The decoder of 84. The decoder of 85. An iterative detection method comprising:
receiving an input signal corresponding to one or more outputs of a module whose soft-inverse can be computed by running the forward-backward algorithm on a trellis representation of the module; and determining the soft inverse of the module by computing forward and backward state metrics of the received input signal using a tree structure. 86. The method of 87. The method of 88. The method of 89. The method of 90. The method of Description [0001] Due to the presence of noise on a communications channel, the signal received is not always identical to the signal transmitted. Channel coding, or equivalently, error correction coding, relates to techniques for increasing the probability that a receiver in a communications systems will be able to correctly detect the composition of the transmitted data stream. Typically, this is accomplished by encoding the signal to add redundancy before it is transmitted. This redundancy increases the likelihood that the receiver will be able to correctly decode the encoded signal and recover the original data. [0002] Turbo coding, a relatively new but widely used channel coding technique, has made signaling at power efficiencies close to the theoretical limits possible. The features of a turbo code include parallel code concatenation, non-uniform interleaving, and iterative decoding. Because turbo codes may substantially improve energy efficiency, they are attractive for use over channels that are power and/or interference limited. [0003] A turbo decoder may be used to decode the turbo code. The turbo decoder may include two soft-input/soft-output (SISO) decoding modules that work together in an iterative fashion. The SISO decoding module is the basic building block for established iterative detection techniques for a system having a network of finite state machines, or more generally, subsystems. [0004]FIGS. 7A and 7B respectively show block diagrams of typical turbo encoder [0005] At the decoder [0006] Each of the SISO decoder modules in the decoder [0007] The present inventors recognized that, depending on the latency of other components in a decoder or other detection system, reducing the latency of a SISO could result in a significant improvement in the system's throughput (a measurement of the number of bits per second that a system architecture can process). Consequently, the present inventors developed a tree-structured SISO that can provide reduced latency. [0008] Implementations of the tree-structured SISO may include various combinations of the following features. [0009] In one aspect, decoding an encoded signal (for example, a turbo encoded signal, a block encoded signal or the like) can be performed, e.g., in a wireless communications system, by demodulating the received encoded signal to produce soft information, and iteratively processing the soft information with one or more soft-in/soft-output (SISO) modules. At least one of the SISO modules uses a tree structure to compute forward and backward state metrics, for example, by performing recursive marginalization-combining operations, which may in various embodiments include min-sum operations, min*-sum operations (where min*=min(x,y)−ln(1+e [0010] The encoded signal may comprise at least one of a turbo encoded signal, a block turbo encoded signal, a low density parity check coded signal, a product coded signal, a convolutional coded signal, a parallel concatenated convolutional coded signal, and/or a serial concatenated convolutional coded signal. [0011] The iterative processing may be terminated upon occurrence of a predetermined condition, for example, the completion of a predetermined number of iterations. The iterative processing may include performing parallel prefix operation or parallel suffix operations, or both, on the soft information. Moreover, the iterative processing may include using soft output of a first SISO as soft input to another SISO, and/or may include performing marginalization-combining operations which form a semi-ring over the soft-information. [0012] The tree structure used by at least one SISO may be a tree structure that results in the SISO having a latency of O(log [0013] Processing performed by at least one SISO may include tiling an observation interval into subintervals, and applying a minimum half-window SISO operation on each subinterval. [0014] In another aspect, a SISO module may include a plurality of fusion modules arranged into a tree structure and adapted to compute forward and backward state metrics. Each fusion module may be defined by the equation:
[0015] where C(k, m) is a matrix of minimum sequence metrics (MSM) of state pairs s [0016] In another aspect, a SISO module may include one or more complete fusion modules (CFMs) for performing marginalization-combining operations in both a forward direction and a backward direction, one or more forward fusion modules (fFMs) for performing marginalization-combining operations only in the forward direction, and one or more backward fusion modules (bFMs) for performing marginalization-combining operations only in the backward direction. The one or more CFMs, fFMs, and bFMs are arranged into a tree structure (e.g., Brent-Kung tree, forward-backward tree). An amount of the CFMs may be set to a minimum number needed to compute a soft-inverse. In general, fFMs and bFMs may be used in the tree structure in place of CFMs wherever possible. [0017] In another aspect, iterative detection may include receiving an input signal (e.g., a turbo encoded signal or a convolutional coded signal) corresponding to one or more outputs of a finite state machine (FSM), and determining the soft inverse of the FSM by computing forward and backward state metrics of the received input signal using a tree structure. The forward and backward state metrics may be computed by one or more SISO modules, for example, using a tree-structured set of marginalization-combining operations. [0018] Determining the soft inverse of the FSM may include iteratively processing soft information, for example, performing parallel prefix operation or parallel suffix operations, or both, on the soft information. Moreover, the iterative processing may include using soft output of a first SISO as soft input to another SISO. At least one SISO further may the an observation interval into subintervals, and apply a minimum half-window SISO operation on each subinterval. [0019] In another aspect, a turbo decoder includes a demodulator adapted to receive as input a signal encoded by a FSM and to produce soft information relating to the received signal, and at least one SISO module in communication with the demodulator and adapted to compute a soft-inverse of the FSM using a tree structure. The tree structure may implement a combination of parallel prefix and parallel suffix operations. [0020] The turbo decoder may include at least two SISO modules in communication with each other. In that case, the SISO modules may iteratively exchange soft information estimates of the decoded signal. In any event, at least one SISO may compute the soft-inverse of the FSM by computing forward and backward state metrics of the received signal. [0021] In another aspect, iterative detection may be performed by receiving an input signal corresponding to output from one or more block encoding modules, and determining the soft inverse of the one or more block encoding modules by computing forward and backward state metrics of the received input signal using a tree structure. The input signal may include a block turbo encoded signal, a low density parity check coded signal, and/or a product coded signal. [0022] Determining the soft inverse of the block encoding module may include iteratively processing soft information, for example, performing parallel prefix operation or parallel suffix operations, or both, on the soft information. [0023] In another aspect a block decoder may include a demodulator adapted to receive as input a signal encoded by a block encoding module and to produce soft information relating to the received signal, and at least one SISO module in communication with the demodulator and adapted to compute a soft-inverse of the block encoding module using a tree structure. The tree structure used may implement a combination of parallel prefix and parallel suffix operations. The block decoder may further include at least two SISO modules in communication with each other, wherein the SISO modules iteratively exchange soft information estimates of the decoded signal. In any event, at least one SISO may compute the soft-inverse of the block encoding module by computing forward and backward state metrics of the received signal. [0024] In another aspect, iterative detection may include receiving an input signal (e.g., a block error correction encoded signal, a block turbo encoded signal, a low density parity check coded signal, and/or a product coded signal) corresponding to one or more outputs of a module whose soft-inverse can be computed by running the forward-backward algorithm on a trellis representation of the module (e.g., a FSM or a block encoding module), and determining the soft inverse of the module by computing forward and backward state metrics of the received input signal using a tree structure. [0025] One or more of the following advantages may be provided. The techniques and methods described here result in a tree-structure SISO module that can have a reduced latency as low as O(lg N) [where N is the block size and “lg” denotes log [0026] These reduced-latency SISOs can be used in virtually any environment where it is desirable or necessary to run the forward-backward algorithm on a trellis. For example, the tree-SISO finds application in wireless communications and in many types of decoding (turbo decoding, block turbo decoding, convolutional coding including both parallel concatenated convolutional codes and serial concatenated convolutional codes, parity check coding including low density parity check (LDPC) codes, product codes and more generally in iterative detection). The reduced-latency SISOs are particularly advantageous when applied to decode FSMs having a relatively small number of states, such as turbo code FSMs which typically have either 4 or 8 states. [0027] The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. [0028]FIG. 1 shows the C fusion process. [0029]FIG. 2 shows a fusion module array for combining the complete set of C matrices on [k [0030]FIG. 3 shows a tree-SISO architecture for N=16. [0031]FIG. 4 shows a tiled sub-window scheme based on the forward-backward algorithm. [0032]FIG. 5 shows a tiled sub-window approach with 4 tree-SISOs of window size 4 for N=16 to implement a d=4 MHW SISO. [0033]FIG. 6 is a graph showing a simulation of a standard turbo code for SISOs with various half-window sizes, N=1024, and ten iterations. [0034]FIGS. 7A and 7B show examples of a turbo encoder and a turbo decoder, respectively. [0035]FIGS. 8A and 8B show a forward-backward tree-SISO (FBT-SISO) implementation. [0036]FIG. 9 shows an embodiment of a Brent-Kung Tree-SISO. [0037]FIG. 10 is a graph showing transistor count estimations for the Brent-Kung Tree-SISO approach of FIG. 9. [0038]FIG. 11 shows the trellis structure for the parity check for a standard Hamming (7,4) code. [0039]FIG. 12 shows a tree structured representation of the Hamming code parity check, in which the forward-backward-tree-SISO algorithm may be run on this tree with an inward (up) set of message passes to the node labeled V6, followed by an outward (down) set of message passes to produce the desired soft-out metrics on the coded bits. [0040]FIG. 13 shows an example of an LDPC decoder (overall code rate of 0.5) in which beliefs are passed from the broadcaster nodes to the parity check nodes through a fixed permutation, and in which the parity check nodes can be implemented as a tree-structured SISO. [0041] The present inventors have developed a re-formulation of the standard SISO computation using a combination of prefix and suffix operations. This architecture—referred to as a Tree-SISO—is based on tree-structures for fast parallel prefix computations used in Very Large Scale Integration (VLSI) applications such as fast-adders. Details of the Tree-SISO and various alternative embodiments follow. [0042] Calculating the “soft-inverse” of a finite-state machine (FSM) is a key operation in many data detection/decoding algorithms. One of the more prevalent applications is iterative decoding of concatenated codes, such as turbo codes as described in Berrou, et al., “Near shannon limit error-correcting coding and decoding: turbo-codes,” [0043] There are two basic performance (speed) aspects of a data detection circuit architecture. The first is throughput which is a measurement of the number of bits per second the architecture can decode. The second is latency which is the end-to-end delay for decoding a block of N bits. Non-pipelined architectures are those that decode only one block at a time and for which the throughput is simply N divided by the latency. Pipelined architectures, on the other hand, may decode multiple blocks simultaneously, shifted in time, thereby achieving much higher throughput than their non-pipelined counterparts. [0044] Depending on the application, the throughput and/or latency of the data detection hardware may be important. For example, the latency associated with interleaving in a turbo-coded system with relatively low data rate (less than 100 Kb/s) will likely dominate the latency of the iterative decoding hardware. For future high-rate systems, however, the latency due to the interleaver may become relatively small, making the latency of the decoder significant. While pipelined decoders can often achieve the throughput requirements, such techniques generally do not substantially reduce latency. In addition, sometimes latency has a dramatic impact on overall system performance. For example, in a data storage system (e.g., magnetic hard drives), latency in the retrieval process has a dramatic impact on the performance of the microprocessor and the overall computer. Such magnetic storage channels may use high-speed Viterbi processing with turbo-coded approaches. [0045] The standard SISO algorithm is the forward-backward algorithm. The associated forward and backward recursion steps can be computed in parallel for all of the FSM states at a given time, yielding an architecture with O(N) computational complexity and latency, where N is the block size. The key result of this paper is the reformulation of the standard SISO computation using a combination of prefix and suffix operations, which leads to an architecture with O(lg N) latency. This architecture, referred to as a “tree-SISO”, is based on a tree-structure for fast parallel prefix computations in the Very Large Scale Integration (VLSI) literature (e.g., fast adders). [0046] This exponential decrease in latency for the tree-SISO comes at the expense of increased computational complexity and area. The exact value of these costs depends on the FSM structure (e.g., the number of states) and the details of the implementation. However, for a four-state convolutional code, such as those often used as constituent codes in turbo codes, the tree-SISO architecture achieves O(lg N) latency with computational complexity of O(N lg N). Note that, for this four-state example, the computation complexity of tree-SISO architecture increases sublinearly with respect to the associated speed-up. This is better than linear-scale solutions to the Viterbi algorithm (e.g., such as described in Fettweis, et al., “Parallel Viterbi algorithm implementation: Breaking the ACS-bottleneck” IEEE Trans. Commun., vol. 37, pp. 785-790, August 1989); the generalization of which to the SISO problem is not always clear. For this 4-state code example, the area associated with the O(lgN)-latency tree-SISO is O(N). [0047] Soft-In Soft-Out Modules [0048] Consider a specific class of finite state machines with no parallel state transitions and a generic S-state trellis. Such a trellis has up to S transitions departing and entering each state. The FSM is defined by the labeling of the state transitions by the corresponding FSM input and FSM output. Let t [0049] Consider the FSM as a system that maps a digital input sequence a [0050] where the set of transitions starting at time K [0051] implicitly defines a sequence of transitions t [0052] Depending on the specific application, one or both of the following “extrinsic” quantities will be computed
[0053] Because the system on which the SISO is defined is an FSM, the combining and marginalization operations in (2)-(3) can be computed efficiently. The traditional approach is the forward-backward algorithm which computes the MSM of the states recursively forward and backward in time. Specifically, for the standard fixed-interval algorithm based on soft-in for transitions t [0054] where f [0055] where u [0056] While the forward-backward algorithm is computationally efficient, straightforward implementations of it have large latency (i.e., O(N)) due to ACS bottleneck in computing the causal and anticausal state MSMs. [0057] Prefix and Suffix Operations [0058] A prefix operation is defined as a generic form of computation that takes in n inputs y [0059] where ⊕ is any associative binary operator. [0060] Similarly, a suffix operation can be defined as a generic form of computation that takes in n inputs y [0061] where ⊕ is any associative binary operator. Notice that a suffix operation is simply a (backward) prefix operation anchored at the other edge. [0062] Prefix and suffix operations are important since they enable a class of algorithms that can be implemented with low latency using tree-structured architectures. The most notable realizations of this concept are VLSI N-bit tree adders with latency O(lgN). [0063] Reformulation of the SISO Operation [0064] The proposed low-latency architecture is derived by formulating the SISO computations in terms of a combination of prefix and suffix operations. To obtain this formulation, define C(s [0065] With this observation, one key step of the algorithm is to compute C(O,k) and C(k, N) for k=0, 1, . . . , N−1. Note that the inputs of the algorithm are the one-step transition metrics which can be written as C(k, k+1) for k=0, 1, . . . , N−1. To show how this algorithm can be implemented with a prefix and suffix computation, a min-sum fusion operator on C matrices is defined that inputs two such matrices, one with a left-edge coinciding with the right-edge of the other, and marginalizes out the midpoint to obtain a pairwise state-MSM with larger span. Specifically, given C(k [0066] Note that the ⊕c operator is an associative binary operator that accepts two matrices and returns one matrix. This is illustrated in FIG. 1. With this definition C(0,k) and C(k, N) for k=0, 1, . . . , N−1 can be computed using the prefix and suffix operations as follows: [0067] In general, a SISO algorithm can be based on the decoupling property of state-conditioning. Specifically, conditioning on all possible FSM state values at time k, the shortest path problems (e.g., MSM computation) on either side of this state condition may be solved independently and then fused together (e.g., as performed by the c-fusion operator). More generally, the SISO operation can be decoupled based on a partition of the observation interval with each subinterval processed independently and then fused together. For example, the forward-backward algorithm is based on a partition to the single-transition level with the fusing taking place sequentially in the forward and backward directions. In contrast, other SISO algorithms may be defined by specifying the partition and a schedule for fusing together the solutions to the sub-problems. This may be viewed as specifying an association scheme to the above prefix-suffix operations (i.e., grouping with parentheses). [0068] The C-fusion operations may be simplified in some cases depending on the association scheme. For example, the forward-backward algorithm replaces all C-fusion operations by the much simpler forward and backward ACSs. However, latency is also a function of the association scheme. An architecture based on a pairwise tree-structured grouping is presented below. This structure allows only a small subset of the C-fusion operations to be simplified, but facilitates a significant reduction in latency compared to the forward-backward algorithm, by fusing solutions to the subproblems in a parallel, instead of sequential, manner. [0069] Low-Latency Tree-SISO Architectures [0070] Many low-latency parallel architectures based on binary tree-structured groupings of prefix operations can be adopted to SISOs such as described in Brent, et al., “A regular layout for parallel adders,” IEEE Transactions on Computers, vol. C-31, pp. 260-264, March 1982; T. H. Cormen, et al., Introduction to Algorithms. Cambridge, Mass.: The MIT Press, 1990; and A. E. Despain, “Chapter 2: Notes on computer architecture for high performance,” in New Computer Architectures, Academic Press, 1984. All of these have targeted n-bit adder design where the binary associative operator is a simple 1-bit addition. The present inventors were the first to recognize that parallel prefix-suffix architectures could be applied to an algorithm based on binary associative operators that are substantially more complex than 1-bit addition. Conventional parallel prefix architectures trade reduced area for higher latency and account for a secondary restriction of limited fanout of each computational module. This latter restriction is important when the computational modules are small and have delay comparable to the delay of wires and buffers (e.g., in adder design). The fusion operators, however, are relatively large. Consequently, given current VLSI trends, it is believed that they will dominate the overall delay for the near future. Thus, an architecture described herein minimizes latency with the minimal number of computational modules without regard to fanout. [0071] Specifically, the forward and backward metrics, f [0072] The basic span-K to span-2K FM array shown in FIG. 2 can be utilized to compute the C matrices on the entire interval in lgN stages. This is illustrated in FIG. 3 for the special case of N=16. Note that, indexing the stages from left to right (i.e., increasing span) as i=1, 2, . . . , n=lgN it is clear that there are 2 [0073] Because the final objective is to compute the causal and anticausal state metrics, however, not all FM's need be CFMs for all FM arrays. Specifically, the forward state metrics f [0074] Similarly, the backward state metrics can be updated via
[0075] A processing module that produces an f vector from another f vector and a C matrix, as described in equation (16), is referred to as an f Fusion Module (fFM). A b Fusion Module (bFM) is defined analogously according to the operation in equation (17). FIG. 3 indicates which FM's may be implemented as fFMs or bFMs. [0076] The importance of this development is that the calculation of the state metrics has O(lgN) latency. This is because the only data dependencies are from one stage to the next and thus all FM arrays within a stage and all FMs within an FM array can be executed in parallel, each taking O(1) latency. The cost of this low latency is the need for relatively large amounts of area. One mitigating factor is that, because the stages of the tree operate in sequence, hardware can be shared between stages. Thus, the stage that requires the most hardware dictates the total hardware needed. A rough estimate of this is N CFMs, each of which involves S [0077] The implementation of the completion operation defined in equation (8) should also be considered. The basic operation required is a Q-way ACS unit where Q is the number of transitions consistent with u [0078] The computational complexity of the state metric calculations can be computed using simple expressions based on FIGS. 2 and 3. As described below in the section heading “Computation Complexity Analysis”, the total number of computations, measured in units of S S-way ACS computations is [0079] For the example in FIG. 3 and a 4-state FSM, an equivalent of 110 sets of 4 4-way ACS operations are performed. This is to be compared with the corresponding forward-backward algorithm which would perform 2N=32 such operations and have baseline architectures with four times the latency. In general, note that for a reduction in latency from N to lgN, the computation is increased by a factor of roughly (½)(lgN−3)S+1. Thus, while the associated complexity is high, the complexity scaling is sub-linear in N. [0080] Optimizations for Sparse Trellises [0081] In general, the above architecture is most efficient for fully-connected trellises. For sparser trellis structures, however, the initial processing modules must process C-matrices containing elements set to ∝, accounting for MSMs of pairs of states between which there is no sequence of transitions, thereby wasting processing power and latency. Alternative embodiments may incorporate optimizations that address this inefficiency. [0082] Consider as a baseline a standard 1-step trellis with S=M [0083] More precisely, pre-collapsing involves adding the R metrics of the 1-step transitions that constitute the transition metrics of each super-transition t [0084] One principal issue is that for each u [0085] In order to identify the optimal R (i.e., for minimum latency) assuming both these optimizations are performed, the relative latencies of the constituent operations are needed. While exact latencies are dependent on implementation details, rough estimates may still yield insightful results. In particular, assuming that both the pre-collapsing additions and ACS operations for the state metric and completion operations are implemented using binary trees of adders/comparators, and their estimated delay is logarithmic in the number of their inputs. One important observation is that the pre-collapsing along with lgR simplified stages together add L 1-step transition metrics (producing the transition metrics for a fully-connected L-step trellis) and thus can jointly be implemented in an estimated lgL time units. In addition, the state metric (M [0086] It follows that the minimum latency occurs when R−L lgR is minimum (subject to 1≦R≦L), which occurs when R=L. This suggests that the minimum-latency architecture is one in which the trellis is pre-collapsed into a fully-connected trellis and more complex completion units are used to extract the soft outputs from the periodic state metrics calculated. [0087] The cost of this reduced latency is the additional area required to implement the trees of adders that produce the L-step transition metrics and the larger trees of comparators required to implement the more complex completion operations. Note, however, that this area overhead can be mitigated by sharing adders and comparators among stages of each tree and, in some cases, between trees with only marginal impact on latency. [0088] Use in Tiled Sub-Window Schemes [0089] The present inventors recognized that using smaller combining windows reduces latency and improves throughput of computing the soft-inverse. Minimum half-window (MHW) algorithms are a class of SISOs in which the combing window edges K [0090] The traditional forward-backward algorithm can be used on sub-windows to obtain a MHW-SISO. One particular scheme is the tiled sub-window technique in which combining windows of length 2d+h are used to derive all state metrics. In this scheme, as illustrated in FIG. 4, the windows are tiled with overlap of length 2d and there are
[0091] such windows. The forward-backward recursion on each interior sub-window yields h soft outputs, so there is an overlap penalty which increases as h decreases. [0092] For the i [0093] If all windows are processed in parallel, this architecture yields a latency of O(d+h). [0094] The tree-SISO algorithm can be used in a MHW scheme without any overlap penalty and with O(lgd) latency. Consider N/d combining windows of size d and let the tree-SISO compute C(id, id+j) and C((i+1)d, (i+1)d−j) for j=0, . . . , d−1 and i=0, . . . , N/d−1. Then, use one additional stage of logic to compute the forward and backward state metrics for all k time indices that fall within the i [0095] The inner minimization corresponds to a conversion from C information to f (b) information as in equations (13) and (14). The outer minimization corresponds to an fFM or bFM. The order of this minimization was chosen to minimize complexity. This is reflected in the example of this approach, shown in FIG. 5, where the last stage of each of the four tree-SISOs is modified to execute the above minimizations in the proposed order. The module that does this is referred to as a 2Cfb module. This module may be viewed as a specialization of the stage 2 center CFMs in FIG. 3. The above combining of sub-window tree-SISO outputs adds one additional processing stage so that the required number of stages of FMs is lg(d)+1. [0096] Computational Complexity Comparison [0097] The computational complexity of computing the state metrics using the forward-backward tiled scheme is the number of windows times the complexity of computing the forward-backward algorithm on each window. In terms of S S-way ACSs, this can be approximated for large N via
[0098] The computational complexity of computing the state metrics using the tree-SISO tiled scheme in terms of S S-way ACSs can be developed similarly and is
[0099] Determining which scheme has higher computational complexity depends on the relative sizes of h and d. If h is reduced, the standard forward-backward scheme reduces in latency but increases in computational complexity because the number of overlapped windows increase. Since the tiled tree-SISO architecture has no overlap penalty, as h is decreased in a tiled forward-backward scheme, the relative computational complexity trade-off becomes more favorable for the tree-SISO approach. In fact, for
[0100] the computational complexities of the tree-SISO are lower than for the tiled forward-backward scheme. [0101] A Design Example: 4-state PCCC [0102] The highly parallel architectures considered require large implementation area. In this example, an embodiment is described in which the area requirements are most feasible for implementation in the near future. Specifically, an iterative decoder based on 4-state sparse (one-step) trellises is considered. Considering larger S will yield more impressive latency reductions for the tree-SISO. This is because the latency-reduction obtained by the tree-SISO architecture relative to the parallel tiled forward-backward architecture depends on the minimum half-window size. One expects that good performance requires a value of d that grows with the number of states (i.e., similar to the rule-of-thumb for traceback depth in the Viterbi algorithm for sparse trellises). In contrast, considering pre-collapsing will yield less impressive latency reductions. For example, if d=16 is required for a single-step trellis, then an effective value of d=8 would suffice for a two-step trellis. The latency reduction factor associated with the tree-SISO for the former would be approximately 4, but only {fraction (8/3)} for the latter. However, larger S and/or pre-collapsing yields larger implementation area and is not in keeping with our desire to realistically assess the near-term feasibility of these algorithms. [0103] In particular, a standard parallel concatenated convolutional code (PCCC) with two 4-state constituent codes [1], [2] is considered. Each of the recursive systematic constituent codes generates parity using the generator polynomial G(D)=(1+D [0104] In order to determine the appropriate value for d to be used in the MHW-SISOs, simulations were performed where each SISO used a combining window {k−d, . . . k+d} to compute the soft-output at time k. This is exactly equivalent to the SISO operation obtained by a tiled forward-backward approach with h=1. Note that, since d is the size of all (interior) half-windows for the simulations, any architecture based on a MHW-SISO with d will perform at least as well (e.g., h=2 tiled forward-backward, d-tiled tree-SISO, etc.). Simulation results are shown in FIG. 6 for an interleaver size of N=1024 with min-sum marginalization and combining and ten iterations. The performance is shown for various d along with the performance of the fixed-interval (N=1024) SISO. No significant iteration gain is achieved beyond ten iterations for any of the configurations. The results indicate that d=16 yields performance near the fixed-interval case. This is consistent with the rule-of-thumb of five to seven times the memory for the traceback depth in a Viterbi decoder (i.e., roughly d=7×2=14 is expected to be sufficient). [0105] Since the required window size is d=16, the latency improvement of a tree-SISO relative to a tiled forward-backward scheme is close to 4=16/lg(16). The computational complexity of these two approaches is similar and depends on the details of the implementation and the choice of h for the tiled forward-backward approach. A complete fair comparison generally would require a detailed implementation of the two approaches. Below a design for the tree-SISO based sub-window architecture is described. [0106] A factor that impacts the area of the architecture is the bit-width of the data units. Simulation results suggest that an 8-bit datapath is sufficient. Roughly speaking, a tree-based architecture for this example would require 1024 sets of sixteen 4-way ACS units along with associated output registers to store intermediate state metric results. Each 4-way ACS unit can be implemented with an 8-bit 4-to-1 multiplexor, four 8-bit adders, six 8-bit comparators, and one 8-bit register. Initial VLSI designs indicate that these units require approximately 2250 transistors. Thus, this yields an estimate of 16×2250×1024≈40 Million transistors. This number or logic transistors pushes the limit of current VLSI technology but should soon be feasible. An architecture is considered in which one clock cycle is used per stage of the tree at a 200 MHz clock frequency. For d=16, each SISO operation can be performed in 6 such clock cycles (using one clock for the completion step). Moreover, assume a hard-wired interleaver comprising two rows of 1024 registers with an interconnection network. Such an interleaver would be larger than existing memory-based solutions, but could have a latency of 1 clock cycle. Consequently, one iteration of the turbo decoder, consisting of two applications of the SISO, one interleaving, and one deinterleaving, requires 14 clock cycles. Assuming ten iterations, the decoding of 1024 bits would take 140 clock cycles, or a latency of just 700 ns. [0107] This latency also implies a very high throughput which can further be improved with standard pipelining techniques. In particular, a non-pipelined implementation has an estimated throughput of 1024 bits per 700 ns=1.5 Gb/second. Using the tree-SISO architecture one could also pipeline across interleaver blocks as described by Masera et al., “VLSI architectures for turbo codes,” [0108] Moreover, unlike architectures based on the forward-backward algorithm, the tree-SISO can easily be internally pipelined, yielding even higher throughputs with linear hardware scaling. In particular, if dedicated hardware is used for each stage of the tree-SISO, pipelining the tree-SISO internally may yield another factor of lg(d) in throughput, with no increase in latency. For window sizes of d=16, the tree-based architecture could support over 120 Gb/second. That said, it is important to realize that with current technology such hardware costs may be beyond practical limits. Given the continued increasing densities of VLSI technology, however, even such aggressive architectures may become cost-effective in the future. [0109] Computation Complexity Analysis [0110] The number of required stages is n=lgN, with 2 [0111] For the example in FIG. 3, this reduces to N [0112] Using FIG. 3 as an example, it can be seen that the number of FMs that can be implemented as fFMs in stage i is n =2 [0113] where δ(j) is the Kronecker delta. The total number of fusion modules is therefore
[0114] Comparing equations (25) and (29), it is seen that, for relatively large N, the fraction of FMs that must be CFMs is (lg N−3)/(lg N−1). For smaller N, the fraction is slightly larger. For example, in FIG. 3, N [0115] The CFM is approximately S (i.e., the number of states) times more complex than the fFM and bFM operations. This can be seen by comparing equation (15) with equations (16) and (17). Specifically, the operations in equations (15), (16), and (17) involve S-way ACSs. For the CFM, an S-way ACS must be carried out for every possible state pair (s [0116] Summing over stages, the total number of computations is obtained, measured in units of S S-way ACS computations [0117] For the example in FIG. 3 and a 4-state FSM, an equivalent of 110 sets of S S-way ACS operations are performed. This is to be compared with the corresponding forward-backward algorithm which would perform 2N=32 such operations and have baseline architectures with four times the latency. In general, note that the for a reduction in latency from N to lg N, the computation is increased by a factor of roughly (½)(lg N−3) S+1. Thus, while the associated complexity is high, the complexity scaling is sub-linear in N. For small S, this is better than linear-scale solutions to low-latency Viterbi algorithm implementations (e.g.,such as described in P. J. Black, [0118] Hardware Resource Requirements [0119] The maximum of n [0120] The maximum of n <=>2 [0121] [0122] It follows that n [0123] can be used to find the maximizer of n [0124] Other Embodiments of a Tree-Structured SISO [0125] Generally, in implementing a tree-structured SISO, any of various tree structures can be used that represent a trade-off between latency, computational complexity and IC area according to the system designer's preferences. FIGS. 8A and 8B show an embodiment referred to as a Forward-Backward Tree-SISO (FBT-SISO). In the FBT-SISO, the tree structure recursion is bi-directional—inward and outward. As a result, the FBT-SISO has twice the latency of the Tree-SISO, but it also achieves a significant decrease in computational complexity and uses less area on an integrated circuit (IC) chip. [0126] Details of message passing using the generalized forward-backward schedule are shown in FIGS. 8A and 8B in min-sum processing. The inward messages are shown in FIG. 8A. Specifically, initially MI[tk] is set to uniform and the algorithm begins by activating the first level of subsystems to compute Mk[tk] from MI[x(tk)] and MI[a(tk)]. The messages passed inward to the next level of the tree are MSMk[sk, sk+1] which is simply Mk[tk] if there are no parallel transitions. This inward message passing continues with the messages shown. When the two messages on s4 reach V4-s, the outward propagation begins and proceeds downward as shown in FIG. 8B. Again, all nodes at a given level of the tree are activated before activating any of the nodes at the next level. At the bottom level, the input metric of (sk, sk+1) is MSM{k}c[sk, sk+1]—i.e., the sum of the forward and backward state metrics in the standard forward-backward algorithm. Thus, the final activation of the nodes on the bottom level produces the desired extrinsic output metrics. [0127] This FBT-SISO has twice the latency of the Tree-SISO because the messages must propagate both inward and outward. This modest increase in latency is accompanied by a significant reduction in computational complexity. Specifically, the FBT-Tree SISO has O(K) computational complexity and O(log2K) latency. This is to be compared to O(K log2K) computational complexity and O(log2K) latency for the Tree-SISO and O(K) computational complexity and O(K) latency for message passing on the standard trellis. [0128] Other embodiments of a tree-structured SISO may be advantageous depending on the designer's goals and constraints. In general, a tree-structured SISO can be constructed that uses virtually any type of tree structure. For example, advantageous results may be obtained with a tree-structured SISO that uses one or more of the tree structures described in R. P. Brent and H. T. Kung, “A regular layout for parallel adders,” IEEE Transactions on Computers, C-31:260-264 (March 1982) (the “Brent-Kung tree”); A. E. Despain, “New Computer Architectures,” Chapter 2: Notes on computer architecture for high performance, Academic Press (1984); T. H. Cormen, C. Leiserson, and R. L. Rivest, “Introduction to Algorithms,” The MIT Press (1990); and/or S. M. Aji and R. J. McEliece, “The generalized distributive law,” IEEE Trans. Inform. Theory, 46(2):325-343 (March 2000). [0129]FIG. 9 shows a representation of a Brent-Kung Tree-SISO in which calculation of the branch metrics in a d=16 sub-window uses a modified version of the Brent-Kung model. There are six pipeline stages in the Brent-Kung Tree-SISO which are indicated by the dotted lines. Nodes shaded gray represent a 2-way ACS while the black nodes represent a 4-way ACS. [0130] The Brent-Kung Tree-SISO is based on the Brent-Kung parallel adder. It was created to solve the fan-out problem of the prefix adders. Additionally it reduces the amount of hardware needed for the calculation of all the metrics. The fusion operation is also used here, but the amount of fusion operations needed is significantly reduced. In the Brent-Kung adder, instead of additions, fusion operations are performed at each node. In this form only the forward information can be calculated. The model was modified so that the calculation of both the forward and backward metrics could be performed at the same time. [0131] This model firstly reduces the number of units that have to be driven by the output of an ACS. In the worst case here, 4 units feed on the output of a single stage (i.e. node C0,8). This is almost half of what the previous approach needed. It is also observed that there is a significant number of operations that only need 2-way ACS units. Considering that the 2-way ACS unit uses less than half of the hardware needed in a 4-way ACS unit, the total size of the circuitry is expected to drop considerably. An analysis similar to the one performed before, verifies this intuitive assumption. The results are summarized in FIG. 10. [0132] Advantages presented by this approach may be counterbalanced with a reduction in the system's performance. A close look at the block diagram in FIG. 10 indicates that the longest path for the calculations is now 6 cycles long. Adding the three extra cycles needed for the forward and backward metric calculation, the completion step and the interleaving process brings the total delay of the SISO module to 9 cycles. This means that for the whole decoding process takes 180 cycles. Assuming that the same cells are used for implementation, this yields a total time of 540 nsec for processing one block of 1024 bits of data. The throughput of the system in this case will be 1.896 Gbps. If the unfolded design pipelined after each ACS step is used, that would allow one block to be processed after each step, and a throughput of 16.82 Gbps could be realized. If 20 SISOs were used to unfold the loop, the throughput would be 341.32 Gbps. For the first case, which is of interest due to the size of the design, the performance degradation is only about 24.1%. At the same time the number of transistors needed to implement this design is reduced by almost 43.8%. [0133] Decoding Block Codes and Concatenated Blocks with the Tree-Structure SISO [0134] There are other relevant decoding problems in which the conventional solution is to run the standard forward-backward algorithm on a trellis. The methods and techniques described herein also can be applied in place of the forward-backward algorithm in order to reduce the processing latency in these applications. One example of such an application is computing the soft inversion of a block error correction code using the trellis representation of the code. A method for decoding a block code using a trellis representation was described in Robert J. McEliece, “On the BCJR Trellis for Linear Block Codes,” IEEE Transactions on Information Theory,” vol. 42, No. 4, July 1996. In that paper, a method for constructing a trellis representation based on the parity-check structure of the code is described. Decoding, or more generally soft-inversion of the block code, can be accomplished by running the forward-backward algorithm on this trellis. The methods and techniques described herein can be applied to determine the soft-inversion of a block code in a manner similar to the tree-structured methods for soft-inversion of an FSM. Specifically, the forward and backward state metrics can be computed to find the soft-inversion of a block code by using a parallel prefix computational architecture with tree-structure. [0135] The application of the tree-SISO architecture to implementing the soft-inverse of a block code via the parity check structure is significant as a practical matter because several attractive turbo-like codes are based on the concatenation of simple parity check codes. These codes are often referred to as “turbo-like codes” since they have similar performance and are decoded using iterative algorithms in which soft-inverse nodes accept, update and exchange soft-information on the coded bits. Specific examples of turbo-like codes include: Low-Density Parity Check Codes (LDPCs) also known as Gallager codes and product codes (also known as turbo-block codes), which are described in J. Hagenauer, E. Offer, and L. Papke, “Iterative decoding of binary block and convolutional codes,” IEEE Transactions on Information Theory, 42(2):429-445, March 1996, and R. G. Gallager, “Low-Density Parity-Check Codes,” MIT Press, Cambridge, Mass., 1963. [0136] As a specific example, the parity check trellis for a standard Hamming(7,4) code is shown in FIG. 11. The forward-backward algorithm may be run on this trellis with latency on the order of 7. Alternatively, a tree-SISO architecture can be used resulting in the computational structure shown in FIG. 12. As in the case of FSM soft-inversion, the tree-structured computation yields the same forward and backward state metrics as the conventional solution method (i.e., running the standard forward-backward algorithm on a trellis), but has logarithmic latency (roughly ½ the latency in this simple example). In general, for a block code with length N, the conventional approach based on the forward-backward algorithm will have latency O(N), whereas the same computation can be computed using the tree-SISO with latency O(lg N). [0137] As a specific example of the use for a tree-structured parity check node SIS0 such as the one illustrated in FIG. 12, consider the iterative decoder for an LDPC, as illustrated in FIG. 13. This decoder has two basic types of soft-inverse processing nodes: the soft broadcaster nodes and the parity-check SISO nodes. In one embodiment, the decoder executes by activating the soft-broadcaster nodes in parallel, followed by permuting the generated soft-information which becomes the input to the parity check SISO nodes. These nodes are activated producing updated beliefs on the coded bit values that are passed back through the permutation and become the input to the soft-broadcaster. This may be viewed as a single iteration. Several iterations are required before the decoding procedure is complete. As in turbo decoding, the stopping criterion is part of the design, with a common choice being a fixed number of iterations. The computation shown in FIG. 11 is performed in each parity check SISO node in a preferred embodiment. Alternatively, the tree-structured architecture can be used for the computation at each parity check SISO node. In the most common form, the parity check nodes in LDPCs are single-parity checks, and therefore have a two-state trellis-representation. [0138] Conclusion [0139] Based on the interpretation of the SISO operation in terms of parallel prefix/suffix operations, a family of tree-structured architectures are described above. Compared to the baseline forward-backward algorithm architecture, the tree-SISO architecture reduces latency from O(N) to O(lgN). Alternative tree-structured SISOS, such as the FBT-SISO, trade a linear increase in latency for substantially lower complexity and area. [0140] An efficient SISO design generally is not built using a single tree-SISO, but rather using tree-SISOs as important components. For example, as described above, many tree-SISOs were used to comprise a SISO using tiled sub-windows. Latency in that example reduced from linear in the minimum half-window size (d) for fully-parallel tiled architectures based on the forward-backward algorithm, to logarithmic in d for tiled tree-SISOs. [0141] In general, potential latency advantages of the tree-SISO are clearly most significant for applications requiring large combining windows. For most practical designs, this is expected when the number of states increases. In the one detailed 4-state tiled-window example considered, the latency was reduced by a factor of approximately 4. For systems with binary inputs and S states, one would expect that d≅8 lg(S) would be sufficient. Thus, there is a potential reduction in latency of approximately 8 lg(S)/lg(8 lg S) which becomes quite significant as S increases. However, the major challenge in achieving this potential latency improvement is the area required for the implementation. In particular, building a high-speed S-way ACS unit for large S is the key challenge. Techniques to reduce this area requirement without incurring performance degradations (e.g., bit-serial architectures) are promising areas of research. In fact, facilitating larger S may allow the use of smaller interleavers, which alleviates the area requirements and reduces latency. [0142] Various implementations of the systems and techniques described here may be realized in digital electronic circuitry, integrated circuitry, specially designed ASICs (application specific integrated circuits) or in computer hardware, firmware, software, or combinations thereof. [0143] A number of embodiments of the present invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims. Patent Citations
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