US20020024116A1 - Method and apparatus for magnetic shielding of an integrated circuit - Google Patents

Method and apparatus for magnetic shielding of an integrated circuit Download PDF

Info

Publication number
US20020024116A1
US20020024116A1 US09/939,652 US93965201A US2002024116A1 US 20020024116 A1 US20020024116 A1 US 20020024116A1 US 93965201 A US93965201 A US 93965201A US 2002024116 A1 US2002024116 A1 US 2002024116A1
Authority
US
United States
Prior art keywords
shielding material
magnetic
integrated circuit
package
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/939,652
Other versions
US6429044B1 (en
Inventor
Mark Tuttle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
US Bank NA
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US09/939,652 priority Critical patent/US6429044B1/en
Publication of US20020024116A1 publication Critical patent/US20020024116A1/en
Application granted granted Critical
Publication of US6429044B1 publication Critical patent/US6429044B1/en
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT reassignment MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT PATENT SECURITY AGREEMENT Assignors: MICRON TECHNOLOGY, INC.
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Assignors: MICRON TECHNOLOGY, INC.
Assigned to JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT reassignment JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON SEMICONDUCTOR PRODUCTS, INC., MICRON TECHNOLOGY, INC.
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Assigned to MICRON SEMICONDUCTOR PRODUCTS, INC., MICRON TECHNOLOGY, INC. reassignment MICRON SEMICONDUCTOR PRODUCTS, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01012Magnesium [Mg]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01025Manganese [Mn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Definitions

  • the present invention relates to a method and apparatus for shielding electromagnetic integrated circuits from external magnetic fields.
  • a conventional integrated circuit (IC) package typically comprises (1) an IC chip or die including a plurality of input/output terminals; (2) a support for the chip, such as a pad, substrate or leadframe, including electrically conductive leads; (3) electrical connections such as wire bonds or conductive bumps for electrically connecting the input/output terminals of the chip with the electrically conductive leads; and (4) a material for encasing or encapsulating the chip, the support and the electrical connections while leaving portions of the leads accessible outside the casing or encapsulation.
  • Fabrication of such a conventional IC package requires attaching the IC chip to the support, connecting the input/output terminals of the chip to the electrically conductive leads, and encapsulating the IC chip, the support and the electrical connections in, for example, a plastic package.
  • Magnetic random access memories employ one or more ferromagnetic films as storage elements.
  • a typical multilayer-film MRAM includes a plurality of bit or digit lines intersected by a plurality of word lines. At each intersection, a ferromagnetic film is interposed between the corresponding bit line and word line to form a memory cell.
  • an MRAM cell When in use, an MRAM cell stores information as digital bits, the logic value of which depends on the states of magnetization of the thin magnetic multilayer films forming each memory cell.
  • the MRAM cell has two stable magnetic configurations, high resistance representing, for example, a logic state 0 and low resistance representing, for example, a logic state 1 .
  • the magnetization configurations of the MRAMs depend in turn on the magnetization vectors which are oriented as a result of electromagnetic fields applied to the memory cells.
  • the electromagnetic fields used to read and write data are generated by associated CMOS circuitry.
  • stray magnetic fields which are generated external to the MRAM, may cause errors in memory cell operation when they have sufficient magnitude.
  • Very high-density MRAMs are particularly sensitive to stray magnetic fields mainly because the minuscule MRAM cells require relatively low magnetic fields for read/write operations which, in turn, depend upon the switching or sensing of the magnetic vectors. These magnetic vectors are, in turn, easily affected and have the magnetic orientation changed by such external stray magnetic fields.
  • the present invention provides a method and apparatus which provide a packaging device for magnetic memory structures, such as MRAMs, which shields such memory structures from external magnetic fields.
  • the invention employs a magnetic shield, preferably formed of non-conductive magnetic oxides, which either partially contacts or completely surrounds an integrated circuit chip which includes such magnetic memory structures.
  • FIG. 1 is a cross-sectional view of an integrated circuit package assembly at an intermediate stage of processing and in accordance with a first exemplary embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the integrated circuit package assembly of FIG. 1 at a subsequent stage of processing to that shown in FIG. 1.
  • FIG. 3 is a cross-sectional view of the integrated circuit package assembly of FIG. 1 at a subsequent stage of processing to that shown in FIG. 2.
  • FIG. 4 is a cross-sectional view of the integrated circuit package assembly of FIG. 1 at a subsequent stage of processing and in accordance with a second embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of the integrated circuit package assembly of FIG. 1 at a subsequent stage of processing and in accordance with a third embodiment of the present invention.
  • the present invention provides a method for fabricating packaging devices for electromagnetic integrated circuit structures, such as MRAM structures, to provide electromagnetic shields and to a shielded packaged electromagnetic integrated circuit structure.
  • the present invention employs a magnetic shield, preferably formed of electrically non-conductive magnetic oxides, which either partially contacts or completely surrounds an integrated circuit chip which contains electromagnetic structures.
  • the magnetic shield is formed as a glob or layer of magnetic field shielding material which is affixed to one or more surfaces of an integrated circuit chip.
  • an encapsulating material of the chip packaging includes magnetic field shielding material therein.
  • FIGS. 1 - 4 illustrate exemplary embodiments of the present invention.
  • FIG. 1 depicts an integrated circuit (IC) package assembly 10 at an intermediate stage of processing.
  • a semiconductor chip or die 12 includes an array of input/output terminals 14 and internal electromagnetic structures, such as MRAM cells and access circuitry.
  • the chip 12 is supported by a die pad 16 (FIG. 1) which can be formed, for example, of a leadframe or a dielectric substrate.
  • a die pad 16 (FIG. 1) which can be formed, for example, of a leadframe or a dielectric substrate.
  • Each of the input/output terminals 14 is further electrically connected with respective conductive leads 22 by wire bonds 20 , or other suitable electrical connectors.
  • a magnetic shield is provided for shielding the chip 12 from external magnetic field disturbances.
  • a glob top 33 is formed over the semiconductor die 12 , including the input/output terminals 14 , and portions of the wire bonds 20 .
  • the glob top 33 comprises an electrically non-conductive magnetic shielding material 30 , which can be injected, for example, from a nozzle. If desired, a mold can be used to shape the magnetic shielding material 30 . If a mold is used, the magnetic shielding material 30 is injected into a cavity of the mold, and flows along the top of the chip 12 , the input/output terminals 14 and adjacent portions of the wire bonds 20 which are within the mold cavity.
  • the magnetic shielding material 30 hardens to form the glob top 33 , as illustrated in FIG. 2. If a mold is not used, a nozzle can simply deposit a glob top 33 of material on the upper surface of chip 12 .
  • the magnetic shielding material 30 may be formed, for example, of an electrically non-conductive material with permeability higher than that of air or silicon.
  • Manganites, chromites and cobaltites may be used also, depending on the device characteristics and specific processing requirements.
  • the magnetic shielding material 30 may be also composed of magnetic particles, for example nickel or iron particles, which are incorporated into a non-conducting molding material, for example a glass sealing alloy or a polyimide. Since nickel is conductive, the concentration of nickel particles in the glass alloy should be low enough so that shielding material 30 does not form a continuous conductor if the shield extends to the input/output terminals 14 or the wire bonds 20 .
  • the structure of FIG. 2 is further encapsulated into a packaging material 35 , for example a plastic compound, which, as known in the art, may be injected into a mold cavity through a passage (not shown).
  • a packaging material 35 for example a plastic compound, which, as known in the art, may be injected into a mold cavity through a passage (not shown).
  • the packaging material 35 As the packaging material 35 is injected, it flows around the glob top 33 , portions of the wire bonds 20 and conductive leads 22 , as well as around the die pad 16 .
  • the input/output terminals 14 of integrated circuitry including magnetic memory structures, such as MRAMs are shielded by the glob top 33 and encapsulated in the packaging material 35 for enhanced protection from external stray magnetic fields.
  • the packaging material 35 may also comprise a mold compound, such as a plastic compound, with conductive magnetic particles therein.
  • conductive magnetic particles of, for example, nickel, iron, and/or cobalt may be suspended in a matrix material, such as a plastic compound, at a concentration that does not allow the particles to touch and form a continuous shorting conductor between the leads.
  • the packaging material 35 may comprise a mold compound, such as a plastic compound, including non-conductive particles of, for example, non-conductive magnetic oxides and/or Mumetal alloys, which may comprise approximately 77% nickel (Ni), 4.8% copper (Cu), 1.5% chromium (Cr) and 14.9% iron (Fe).
  • FIGS. 2 and 3 show the magnetic shielding material 30 in the form of a rounded glob top 33 on only the top of chip 12 , it is also possible to apply a glob of shielding material 30 to the bottom surface instead, or to the top and bottom of chip 12 .
  • the material of choice for the die pad 16 is a dielectric substrate, it is also possible to apply a flat layer 60 of shielding material 30 to the bottom of the chip 12 , as illustrated in FIG. 5.
  • the bottom flat layer 60 of shielding material 30 may be conductive or non-conductive as needed, depending on the characteristics of the IC device.
  • a conductive magnetic shielding material may be composed of Mumetal alloys comprising approximately 77% nickel (Ni), 4.8% copper (Cu), 1.5% chromium (Cr) and 14.9% iron (Fe), or magnetic particles, such as nickel or iron particles, which are incorporated into a non-conducting molding material, for example a glass sealing alloy or polyimide. If, however, the material of choice for the die pad 16 is a lead frame comprising a magnetic material, such as the commonly used alloy 42 which already provides magnetic shielding, then the bottom flat layer 60 is optional.
  • FIG. 4 illustrates yet another exemplary embodiment of the present invention, in which a magnetic shielding material 50 is formed as the chip 12 encapsulating material which is used to form an IC packaging assembly 11 .
  • manganites, chromites and cobaltites may be used also, depending on the device characteristics and processing requirements.
  • conductive Mumetal alloys comprising approximately 77% nickel (Ni), 4.8% copper (Cu), 1.5% chromium (Cr) and 14.9% iron (Fe) may be used also, as well as conductive magnetic particles, such as nickel, iron or cobalt particles, incorporated into a molding material, for example a glass sealing alloy or a commercially available IC mold compound.
  • the magnetic shielding material 50 completely surrounds the semiconductor chip 12 .
  • a protective plastic packaging 56 (FIG. 4), such as a commercially available IC mold compound, is next optionally provided to completely surround the magnetic shielding material 50 and to complete the fabrication of the IC package assembly 11 .
  • the exemplary embodiments described above refer to specific locations where the shielding material is applied to a die, it is also possible to apply the shielding material in other locations.
  • two globs 33 or layers of material could be employed for shielding the magnetic memories structures, one on each side of chip 12 , or multiple globs or layers of the same or different shielding material which overlap each other may be used on one or both sides of chip 12 .
  • the specific shape of the shielding material is not limited to that shown in FIGS. 2 - 4 and other shapes, configurations, or geometries may be employed.

Abstract

Disclosed are a method and apparatus which provide a magnetic shield for integrated circuits containing electromagnetic circuit elements. The shield is formed of a magnetically permeable material, which may be a non-conductive magnetic oxide, and either partially contacts or completely surrounds the integrated circuit.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a method and apparatus for shielding electromagnetic integrated circuits from external magnetic fields. [0001]
  • BACKGROUND OF THE INVENTION
  • A conventional integrated circuit (IC) package typically comprises (1) an IC chip or die including a plurality of input/output terminals; (2) a support for the chip, such as a pad, substrate or leadframe, including electrically conductive leads; (3) electrical connections such as wire bonds or conductive bumps for electrically connecting the input/output terminals of the chip with the electrically conductive leads; and (4) a material for encasing or encapsulating the chip, the support and the electrical connections while leaving portions of the leads accessible outside the casing or encapsulation. Fabrication of such a conventional IC package requires attaching the IC chip to the support, connecting the input/output terminals of the chip to the electrically conductive leads, and encapsulating the IC chip, the support and the electrical connections in, for example, a plastic package. [0002]
  • Recently, very high-density magnetic memories, such as magnetic random access memories (MRAMs), have been proposed to be integrated together with CMOS circuits. Magnetic random access memories employ one or more ferromagnetic films as storage elements. A typical multilayer-film MRAM includes a plurality of bit or digit lines intersected by a plurality of word lines. At each intersection, a ferromagnetic film is interposed between the corresponding bit line and word line to form a memory cell. [0003]
  • When in use, an MRAM cell stores information as digital bits, the logic value of which depends on the states of magnetization of the thin magnetic multilayer films forming each memory cell. As such, the MRAM cell has two stable magnetic configurations, high resistance representing, for example, a logic state [0004] 0 and low resistance representing, for example, a logic state 1. The magnetization configurations of the MRAMs depend in turn on the magnetization vectors which are oriented as a result of electromagnetic fields applied to the memory cells. The electromagnetic fields used to read and write data are generated by associated CMOS circuitry. However, stray magnetic fields, which are generated external to the MRAM, may cause errors in memory cell operation when they have sufficient magnitude.
  • Very high-density MRAMs are particularly sensitive to stray magnetic fields mainly because the minuscule MRAM cells require relatively low magnetic fields for read/write operations which, in turn, depend upon the switching or sensing of the magnetic vectors. These magnetic vectors are, in turn, easily affected and have the magnetic orientation changed by such external stray magnetic fields. [0005]
  • To diminish the negative effects of the stray magnetic fields and to avoid sensitivity of MRAM devices to stray magnetic fields, the semiconductor industry could introduce memory cells requiring higher switching electromagnetic fields than a stray field which the memory cells would typically encounter. However, the current requirements for operating such memory cells is greatly increased because higher internal fields necessitate more current. Thus, both the reliability and scalability of such high current devices decrease accordingly, and the use of MRAMs which may be affected by stray magnetic fields becomes undesirable. [0006]
  • Accordingly, there is a need for an improved magnetic memory structure and a method of forming it, which shields against external magnetic fields. There is also a need of a packaging device for encasing a magnetic random access memory IC chip which reduces the effects of external magnetic fields on internal memory cell structures and operations. There is further a need for minimizing the cost of a packaging which shields a magnetic random access memory IC chip from external magnetic fields. [0007]
  • SUMMARY OF THE INVENTION
  • The present invention provides a method and apparatus which provide a packaging device for magnetic memory structures, such as MRAMs, which shields such memory structures from external magnetic fields. The invention employs a magnetic shield, preferably formed of non-conductive magnetic oxides, which either partially contacts or completely surrounds an integrated circuit chip which includes such magnetic memory structures.[0008]
  • These and other features and advantages of the invention will be more clearly apparent from the following detailed description which is provided in connection with accompanying drawings and which illustrates exemplary embodiments of the invention. [0009]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view of an integrated circuit package assembly at an intermediate stage of processing and in accordance with a first exemplary embodiment of the present invention. [0010]
  • FIG. 2 is a cross-sectional view of the integrated circuit package assembly of FIG. 1 at a subsequent stage of processing to that shown in FIG. 1. [0011]
  • FIG. 3 is a cross-sectional view of the integrated circuit package assembly of FIG. 1 at a subsequent stage of processing to that shown in FIG. 2. [0012]
  • FIG. 4 is a cross-sectional view of the integrated circuit package assembly of FIG. 1 at a subsequent stage of processing and in accordance with a second embodiment of the present invention. [0013]
  • FIG. 5 is a cross-sectional view of the integrated circuit package assembly of FIG. 1 at a subsequent stage of processing and in accordance with a third embodiment of the present invention. [0014]
  • DETAILED DESCRIPTION OF THE EMBODIMENTS
  • In the following detailed description, reference is made to various specific embodiments in which the invention may be practiced. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be employed, and that structural and electrical changes may be made without departing from the spirit or scope of the present invention. [0015]
  • The present invention provides a method for fabricating packaging devices for electromagnetic integrated circuit structures, such as MRAM structures, to provide electromagnetic shields and to a shielded packaged electromagnetic integrated circuit structure. The present invention employs a magnetic shield, preferably formed of electrically non-conductive magnetic oxides, which either partially contacts or completely surrounds an integrated circuit chip which contains electromagnetic structures. In one exemplary embodiment of the invention, the magnetic shield is formed as a glob or layer of magnetic field shielding material which is affixed to one or more surfaces of an integrated circuit chip. In another exemplary embodiment, an encapsulating material of the chip packaging includes magnetic field shielding material therein. [0016]
  • Referring now to the drawings, where like elements are designated by like reference numerals, FIGS. [0017] 1-4 illustrate exemplary embodiments of the present invention. FIG. 1 depicts an integrated circuit (IC) package assembly 10 at an intermediate stage of processing. A semiconductor chip or die 12 includes an array of input/output terminals 14 and internal electromagnetic structures, such as MRAM cells and access circuitry.
  • The [0018] chip 12 is supported by a die pad 16 (FIG. 1) which can be formed, for example, of a leadframe or a dielectric substrate. Each of the input/output terminals 14 is further electrically connected with respective conductive leads 22 by wire bonds 20, or other suitable electrical connectors.
  • Referring now to FIG. 2, a magnetic shield is provided for shielding the [0019] chip 12 from external magnetic field disturbances. According to a first exemplary embodiment of the present invention, a glob top 33 is formed over the semiconductor die 12, including the input/output terminals 14, and portions of the wire bonds 20. The glob top 33 comprises an electrically non-conductive magnetic shielding material 30, which can be injected, for example, from a nozzle. If desired, a mold can be used to shape the magnetic shielding material 30. If a mold is used, the magnetic shielding material 30 is injected into a cavity of the mold, and flows along the top of the chip 12, the input/output terminals 14 and adjacent portions of the wire bonds 20 which are within the mold cavity. Subsequent to the injection of the magnetic shielding material 30 into the mold cavity, the magnetic shielding material 30 hardens to form the glob top 33, as illustrated in FIG. 2. If a mold is not used, a nozzle can simply deposit a glob top 33 of material on the upper surface of chip 12.
  • The [0020] magnetic shielding material 30 may be formed, for example, of an electrically non-conductive material with permeability higher than that of air or silicon. As such, the preferred choice for the magnetic shielding material 30 is a non-conductive magnetic oxide, for example, a ferrite such as MFe2O4, wherein M=Mn, Fe, Co, Ni, Cu, or Mg, among others. Manganites, chromites and cobaltites may be used also, depending on the device characteristics and specific processing requirements.
  • Further, the [0021] magnetic shielding material 30 may be also composed of magnetic particles, for example nickel or iron particles, which are incorporated into a non-conducting molding material, for example a glass sealing alloy or a polyimide. Since nickel is conductive, the concentration of nickel particles in the glass alloy should be low enough so that shielding material 30 does not form a continuous conductor if the shield extends to the input/output terminals 14 or the wire bonds 20.
  • Next, as illustrated in FIG. 3, the structure of FIG. 2 is further encapsulated into a [0022] packaging material 35, for example a plastic compound, which, as known in the art, may be injected into a mold cavity through a passage (not shown). As the packaging material 35 is injected, it flows around the glob top 33, portions of the wire bonds 20 and conductive leads 22, as well as around the die pad 16. This way, the input/output terminals 14 of integrated circuitry including magnetic memory structures, such as MRAMs, are shielded by the glob top 33 and encapsulated in the packaging material 35 for enhanced protection from external stray magnetic fields.
  • Further, for even maximum protection, the [0023] packaging material 35 may also comprise a mold compound, such as a plastic compound, with conductive magnetic particles therein. For example, conductive magnetic particles of, for example, nickel, iron, and/or cobalt, may be suspended in a matrix material, such as a plastic compound, at a concentration that does not allow the particles to touch and form a continuous shorting conductor between the leads. Alternatively, the packaging material 35 may comprise a mold compound, such as a plastic compound, including non-conductive particles of, for example, non-conductive magnetic oxides and/or Mumetal alloys, which may comprise approximately 77% nickel (Ni), 4.8% copper (Cu), 1.5% chromium (Cr) and 14.9% iron (Fe).
  • Although FIGS. 2 and 3 show the [0024] magnetic shielding material 30 in the form of a rounded glob top 33 on only the top of chip 12, it is also possible to apply a glob of shielding material 30 to the bottom surface instead, or to the top and bottom of chip 12. Moreover, if the material of choice for the die pad 16 is a dielectric substrate, it is also possible to apply a flat layer 60 of shielding material 30 to the bottom of the chip 12, as illustrated in FIG. 5. In this case, the bottom flat layer 60 of shielding material 30 may be conductive or non-conductive as needed, depending on the characteristics of the IC device. A non-conductive magnetic shielding material may employ a non-conductive oxide, for example a ferrite such as MFe2O4, wherein M=Mn, Fe, Co, Ni, Cu, or Mg, among others, manganites, chromites and/or cobaltites. Similarly, a conductive magnetic shielding material may be composed of Mumetal alloys comprising approximately 77% nickel (Ni), 4.8% copper (Cu), 1.5% chromium (Cr) and 14.9% iron (Fe), or magnetic particles, such as nickel or iron particles, which are incorporated into a non-conducting molding material, for example a glass sealing alloy or polyimide. If, however, the material of choice for the die pad 16 is a lead frame comprising a magnetic material, such as the commonly used alloy 42 which already provides magnetic shielding, then the bottom flat layer 60 is optional.
  • FIG. 4 illustrates yet another exemplary embodiment of the present invention, in which a [0025] magnetic shielding material 50 is formed as the chip 12 encapsulating material which is used to form an IC packaging assembly 11. The preferred material for the magnetic shielding material 50 is a non-conductive magnetic oxide, for example a ferrite such as MFe2O4, wherein M=Mn, Fe, Co, Ni, Cu, or Mg, among others. However, manganites, chromites and cobaltites may be used also, depending on the device characteristics and processing requirements. Further, conductive Mumetal alloys comprising approximately 77% nickel (Ni), 4.8% copper (Cu), 1.5% chromium (Cr) and 14.9% iron (Fe) may be used also, as well as conductive magnetic particles, such as nickel, iron or cobalt particles, incorporated into a molding material, for example a glass sealing alloy or a commercially available IC mold compound.
  • The [0026] magnetic shielding material 50 completely surrounds the semiconductor chip 12. A protective plastic packaging 56 (FIG. 4), such as a commercially available IC mold compound, is next optionally provided to completely surround the magnetic shielding material 50 and to complete the fabrication of the IC package assembly 11.
  • Although the exemplary embodiments described above refer to specific magnetic shielding materials it must be understood that the invention is not limited to the materials described above, and other magnetic shielding materials, such as ferromagnetics like nickel-iron (Permalloy), nickel or iron may be used also, as long as they are capable of shielding electromagnetic structures within [0027] chip 12 from external magnetic fields.
  • Further, although the exemplary embodiments described above refer to specific locations where the shielding material is applied to a die, it is also possible to apply the shielding material in other locations. For example, as described above, two [0028] globs 33 or layers of material could be employed for shielding the magnetic memories structures, one on each side of chip 12, or multiple globs or layers of the same or different shielding material which overlap each other may be used on one or both sides of chip 12. In addition, the specific shape of the shielding material is not limited to that shown in FIGS. 2-4 and other shapes, configurations, or geometries may be employed.
  • The present invention is thus not limited to the details of the illustrated embodiments and the above description and drawings are only to be considered illustrative of exemplary embodiments which achieve the features and advantages of the present invention. Modifications and substitutions to specific process conditions and structures can be made without departing from the spirit and scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims. [0029]

Claims (33)

What is claimed as new and desired to be protected by Letters Patent of the United States is:
1. An integrated circuit package comprising:
at least one integrated circuit device which may be affected by external magnetic fields; and
a magnetic field shielding material in contact with at least a portion of said device.
2. The package of claim 1, wherein said shielding material contacts said device on at least a surface of said device.
3. The package of claim 2, wherein said shielding material is in the form of a material glob on said device.
4. The package of claim 1, wherein said shielding material completely surrounds said device and forms an exterior packaging for said device.
5. The package of claim 1, wherein said shielding material comprises a magnetic material selected from the group consisting of ferrites, manganites, chromites and cobaltites.
6. The package of claim 1, wherein said magnetic material comprises MFe2O4, wherein M is at least one atom selected from the group consisting of Mn, Fe, Co, Ni, Cu, and Mg.
7. The package of claim 1, wherein said shielding material comprises a material which includes conductive magnetic particles.
8. The package of claim 7, wherein said shielding material comprises a material which includes nickel particles.
9. The package of claim 7, wherein said shielding material comprises a material which includes iron particles.
10. The package of claim 7, wherein said shielding material comprises a material which includes cobalt particles.
11. The package of claim 1, wherein said device is a magnetic memory device.
12. The package of claim 11, wherein said device is a magnetic random access memory device.
13. An integrated circuit structure comprising:
a plurality of external leads; and
a die electrically connected to said external leads, said die being enclosed by a packaging material and being in contact with a shielding material, said die further comprising a magnetic random access memory device.
14. The integrated circuit structure of claim 13, wherein said shielding material is part of said packaging material.
15. The integrated circuit structure of claim 14, wherein said shielding material is in the form of a glob on said die.
16. The integrated circuit structure of claim 13, wherein said shielding material is in the form of said packaging material.
17. The integrated circuit structure of claim 13, wherein said shielding material comprises a magnetic material selected from the group consisting of ferrites, manganites, chromites and cobaltites.
18. The integrated circuit structure of claim 13, wherein said magnetic material comprises MFe2O4, wherein M is at least one atom selected from the group consisting of Mn, Fe, Co, Ni, Cu, and Mg.
19. The integrated circuit structure of claim 13, wherein said shielding material comprises a material which includes conductive magnetic particles.
20. The integrated circuit structure of claim 19, wherein said shielding material comprises a material which includes nickel particles.
21. The integrated circuit structure of claim 19, wherein said shielding material comprises a material which includes iron particles.
22. The integrated circuit structure of claim 19, wherein said shielding material comprises a material which includes cobalt particles.
23. A method of packaging a semiconductor device comprising:
electrically coupling a plurality of external leads to a die;
contacting said die with a shielding material which shields said die from external magnetic fields; and
enclosing said die in a package.
24. The method of claim 23, wherein said act of contacting said die with said shielding material further includes forming a glob of said shielding material on a surface of said die.
25. The method of claim 23, wherein said act of contacting said die with said shielding material further includes encapsulating said die in said shielding material, so that said shielding material forms an exterior package of said die.
26. The method of claim 23, wherein said device is a memory device.
27. The method of claim 23, wherein said device is a magnetic random access memory device.
28. The method of claim 23, wherein said shielding material comprises a magnetic material selected from the group consisting of ferrites, manganites, chromites and cobaltites.
29. The method of claim 23, wherein said magnetic material comprises MFe2O4, wherein M is at least one atom selected from the group consisting of Mn, Fe, Co, Ni, Cu, and Mg.
30. The method of claim 23, wherein said shielding material comprises a material which includes conductive magnetic particles.
31. The method of claim 30, wherein said shielding material comprises a material which includes nickel particles.
32. The method of claim 30, wherein said shielding material comprises a material which includes iron particles.
33. The method of claim 30, wherein said shielding material comprises a material which includes cobalt particles.
US09/939,652 2000-08-31 2001-08-28 Method and apparatus for magnetic shielding of an integrated circuit Expired - Lifetime US6429044B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/939,652 US6429044B1 (en) 2000-08-31 2001-08-28 Method and apparatus for magnetic shielding of an integrated circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/651,997 US6452253B1 (en) 2000-08-31 2000-08-31 Method and apparatus for magnetic shielding of an integrated circuit
US09/939,652 US6429044B1 (en) 2000-08-31 2001-08-28 Method and apparatus for magnetic shielding of an integrated circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/651,997 Division US6452253B1 (en) 2000-08-31 2000-08-31 Method and apparatus for magnetic shielding of an integrated circuit

Publications (2)

Publication Number Publication Date
US20020024116A1 true US20020024116A1 (en) 2002-02-28
US6429044B1 US6429044B1 (en) 2002-08-06

Family

ID=24615098

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/651,997 Expired - Lifetime US6452253B1 (en) 2000-08-31 2000-08-31 Method and apparatus for magnetic shielding of an integrated circuit
US09/939,652 Expired - Lifetime US6429044B1 (en) 2000-08-31 2001-08-28 Method and apparatus for magnetic shielding of an integrated circuit

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/651,997 Expired - Lifetime US6452253B1 (en) 2000-08-31 2000-08-31 Method and apparatus for magnetic shielding of an integrated circuit

Country Status (1)

Country Link
US (2) US6452253B1 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003034496A1 (en) * 2001-10-16 2003-04-24 Sony Corporation Information recorder and electronic apparatus with mounted information recorder
US20040019272A1 (en) * 2002-07-23 2004-01-29 Honeywell International Inc. Magnetic sensing device
US20040150091A1 (en) * 2003-02-05 2004-08-05 Stobbs Colin A. Magnetic shielding for magnetic random access memory
US20050230788A1 (en) * 2004-02-23 2005-10-20 Yoshihiro Kato Magnetic shield member, magnetic shield structure, and magnetic memory device
US20080029845A1 (en) * 2006-08-07 2008-02-07 University Of Central Florida Research Foundation On-Chip Magnetic Components
JP2010040817A (en) * 2008-08-06 2010-02-18 Casio Comput Co Ltd Semiconductor device and manufacturing method thereof
US20100213562A1 (en) * 2009-02-25 2010-08-26 Everlight Electronics Co., Ltd. Quad flat non-leaded chip package structure
US20100213563A1 (en) * 2009-02-25 2010-08-26 Everlight Electronics Co., Ltd. Semiconductor optoelectronic device and quad flat non-leaded optoelectronic device
US20110316129A1 (en) * 2006-06-02 2011-12-29 Honeywell International Inc. Multilayer structures for magnetic shielding
CN108962837A (en) * 2017-05-17 2018-12-07 上海磁宇信息科技有限公司 SoC chip local magnetic screen packaging method and SoC chip local magnetic screen packaging part

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1288753C (en) * 2000-04-04 2006-12-06 Nec东金株式会社 Electromagnetic noise eliminator, semiconductor device using the eliminator and making method thereof
US6515352B1 (en) * 2000-09-25 2003-02-04 Micron Technology, Inc. Shielding arrangement to protect a circuit from stray magnetic fields
US6614102B1 (en) * 2001-05-04 2003-09-02 Amkor Technology, Inc. Shielded semiconductor leadframe package
US6906396B2 (en) * 2002-01-15 2005-06-14 Micron Technology, Inc. Magnetic shield for integrated circuit packaging
JP3961914B2 (en) * 2002-09-05 2007-08-22 株式会社東芝 Magnetic memory device
KR100496860B1 (en) * 2002-09-19 2005-06-22 삼성전자주식회사 Magneto-resistive memory device and method for fabricating the same
JP2004349476A (en) * 2003-05-22 2004-12-09 Toshiba Corp Semiconductor device
US6865107B2 (en) * 2003-06-23 2005-03-08 Hewlett-Packard Development Company, L.P. Magnetic memory device
US7057249B2 (en) * 2003-07-02 2006-06-06 Hewlett-Packard Development Company, L.P. Magnetic memory device
US7179688B2 (en) * 2003-10-16 2007-02-20 Kulicke And Soffa Industries, Inc. Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method
DE102004056449A1 (en) * 2004-01-16 2005-08-25 Continental Teves Ag & Co. Ohg Integrated component, especially for use in motor vehicle, has protective medium with edge- and corner-free surface; protective medium has essentially square surface with rounded edges and corners
US20050206015A1 (en) * 2004-03-16 2005-09-22 Texas Instruments Incorporated System and method for attenuating electromagnetic interference
US20060283043A1 (en) * 2005-06-21 2006-12-21 Miles Lamstein Article of footwear
US7445942B2 (en) * 2005-07-15 2008-11-04 Magic Technologies, Inc. Process for manufacturing segmented MRAM array with patterned segmented magnetic shields
JP4332749B2 (en) * 2006-08-01 2009-09-16 セイコーエプソン株式会社 Electronic device manufacturing method and support member
US8269319B2 (en) * 2006-10-13 2012-09-18 Tessera, Inc. Collective and synergistic MRAM shields
US8154881B2 (en) * 2006-11-13 2012-04-10 Telecommunication Systems, Inc. Radiation-shielded semiconductor assembly
WO2008105315A1 (en) * 2007-02-27 2008-09-04 Renesas Technology Corp. Method for manufacturing magnetic memory chip device
US20080296711A1 (en) * 2007-05-30 2008-12-04 Freescale Semiconductor, Inc. Magnetoelectronic device having enhanced permeability dielectric and method of manufacture
JP5425461B2 (en) * 2008-12-26 2014-02-26 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US8125057B2 (en) * 2009-07-07 2012-02-28 Seagate Technology Llc Magnetic shielding for integrated circuit
CA2809883C (en) 2010-10-05 2016-10-04 Advanced Fusion Systems Llc High voltage high current regulator circuit
US8415775B2 (en) 2010-11-23 2013-04-09 Honeywell International Inc. Magnetic shielding for multi-chip module packaging
CN102623482A (en) * 2011-02-01 2012-08-01 飞思卡尔半导体公司 MRAM device and method of assembling same
DE102013013464B4 (en) * 2013-08-14 2021-06-24 Gottfried Wilhelm Leibniz Universität Hannover Electronic component
KR102628185B1 (en) * 2022-02-07 2024-01-24 (주)캠시스 Camera module with magnetic field interference prevention sturcure

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60244050A (en) * 1984-05-18 1985-12-03 Oki Electric Ind Co Ltd Semiconductor device
US5260601A (en) 1988-03-14 1993-11-09 Texas Instruments Incorporated Edge-mounted, surface-mount package for semiconductor integrated circuit devices
US4953002A (en) 1988-03-31 1990-08-28 Honeywell Inc. Semiconductor device housing with magnetic field protection
US4926546A (en) 1988-06-09 1990-05-22 A. O. Smith Corporation PC board panel configuration technique
CA2092371C (en) * 1993-03-24 1999-06-29 Boris L. Livshits Integrated circuit packaging
US5406117A (en) * 1993-12-09 1995-04-11 Dlugokecki; Joseph J. Radiation shielding for integrated circuit devices using reconstructed plastic packages
CN1110233C (en) * 1996-04-24 2003-05-28 冈村进 Semiconductor device
US5977626A (en) * 1998-08-12 1999-11-02 Industrial Technology Research Institute Thermally and electrically enhanced PBGA package

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050121809A1 (en) * 2001-10-16 2005-06-09 Yuichi Yamamoto Information storage apparatus and electronic device in which information storage apparatus is installed
WO2003034496A1 (en) * 2001-10-16 2003-04-24 Sony Corporation Information recorder and electronic apparatus with mounted information recorder
US20040019272A1 (en) * 2002-07-23 2004-01-29 Honeywell International Inc. Magnetic sensing device
US7037604B2 (en) * 2002-07-23 2006-05-02 Honeywell International, Inc. Magnetic sensing device
US7489015B2 (en) 2003-02-05 2009-02-10 Samsung Electronics Co., Ltd. Magnetic shielding for magnetic random access memory
US20040150091A1 (en) * 2003-02-05 2004-08-05 Stobbs Colin A. Magnetic shielding for magnetic random access memory
US20050230788A1 (en) * 2004-02-23 2005-10-20 Yoshihiro Kato Magnetic shield member, magnetic shield structure, and magnetic memory device
US7459769B2 (en) * 2004-02-23 2008-12-02 Sony Corporation Magnetic shield member, magnetic shield structure, and magnetic memory device
US20110316129A1 (en) * 2006-06-02 2011-12-29 Honeywell International Inc. Multilayer structures for magnetic shielding
US8399964B2 (en) * 2006-06-02 2013-03-19 Honeywell International Inc. Multilayer structures for magnetic shielding
US20080029845A1 (en) * 2006-08-07 2008-02-07 University Of Central Florida Research Foundation On-Chip Magnetic Components
US7719112B2 (en) * 2006-08-07 2010-05-18 University Of Central Florida Research Foundation, Inc. On-chip magnetic components
JP2010040817A (en) * 2008-08-06 2010-02-18 Casio Comput Co Ltd Semiconductor device and manufacturing method thereof
US20100213562A1 (en) * 2009-02-25 2010-08-26 Everlight Electronics Co., Ltd. Quad flat non-leaded chip package structure
US20100213563A1 (en) * 2009-02-25 2010-08-26 Everlight Electronics Co., Ltd. Semiconductor optoelectronic device and quad flat non-leaded optoelectronic device
CN108962837A (en) * 2017-05-17 2018-12-07 上海磁宇信息科技有限公司 SoC chip local magnetic screen packaging method and SoC chip local magnetic screen packaging part

Also Published As

Publication number Publication date
US6452253B1 (en) 2002-09-17
US6429044B1 (en) 2002-08-06

Similar Documents

Publication Publication Date Title
US6429044B1 (en) Method and apparatus for magnetic shielding of an integrated circuit
US6717241B1 (en) Magnetic shielding for integrated circuits
US6962833B2 (en) Magnetic shield for integrated circuit packaging
US20040232536A1 (en) Semiconductor device comprising magnetic element
US7489015B2 (en) Magnetic shielding for magnetic random access memory
US8652880B2 (en) Semiconductor device and method of manufacturing same
US5902690A (en) Stray magnetic shielding for a non-volatile MRAM
US6567299B2 (en) Magnetic memory device and magnetic substrate
US4953002A (en) Semiconductor device housing with magnetic field protection
KR101656330B1 (en) Small form factor magnetic shield for magnetorestrictive random access memory (mram)
KR101019592B1 (en) Magnetic memory device
US6625040B1 (en) Shielded PC board for magnetically sensitive integrated circuits
US6984867B2 (en) Magnetic memory device
JP2003115578A (en) Nonvolatile solid magnetic memory, its manufacturing method and multichip package
JP6010005B2 (en) Semiconductor device and manufacturing method thereof
JP2003309196A (en) Magnetic shielding package for magnetic nonvolatile memory element
JP2004207322A (en) Magnetic memory device
US20220344578A1 (en) Package structure and manufacturing method thereof
WO2011111789A1 (en) Magnetic device and process for production thereof
KR102613576B1 (en) MRAM Package with Magnetic Shielding Layer and Method of Manufacturing the Same

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA

Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001

Effective date: 20160426

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001

Effective date: 20160426

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT, MARYLAND

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001

Effective date: 20160426

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001

Effective date: 20160426

AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001

Effective date: 20160426

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001

Effective date: 20160426

AS Assignment

Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, ILLINOIS

Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001

Effective date: 20180703

Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, IL

Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001

Effective date: 20180703

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT;REEL/FRAME:047243/0001

Effective date: 20180629

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:050937/0001

Effective date: 20190731

AS Assignment

Owner name: MICRON SEMICONDUCTOR PRODUCTS, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001

Effective date: 20190731

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001

Effective date: 20190731