|Publication number||US20020027286 A1|
|Application number||US 09/409,185|
|Publication date||Mar 7, 2002|
|Filing date||Sep 30, 1999|
|Priority date||Sep 30, 1999|
|Also published as||US6444568, US6593653|
|Publication number||09409185, 409185, US 2002/0027286 A1, US 2002/027286 A1, US 20020027286 A1, US 20020027286A1, US 2002027286 A1, US 2002027286A1, US-A1-20020027286, US-A1-2002027286, US2002/0027286A1, US2002/027286A1, US20020027286 A1, US20020027286A1, US2002027286 A1, US2002027286A1|
|Inventors||Srinivasan Sundararajan, Mayur Trivedi|
|Original Assignee||Srinivasan Sundararajan, Mayur Trivedi|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (76), Classifications (21), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
 1. Field of the Invention
 The present invention relates to layers in semiconductor devices, and, in particular, to metal barrier diffusion layers.
 2. Discussion of the Related Art
 Integrated circuits fabricated on semiconductor substrates for very large scale integration typically require multiple levels of metal layers to electrically interconnect the discrete layers of semiconductor devices on the semiconductor chips. The different levels of metal layers are separated by various insulating or dielectric layers (also known as interlevel dielectric (ILD) layers), which have etched via holes to connect devices or active regions from one layer of metal to the next.
 As semiconductor technology advances, circuit elements and dimensions on wafers or silicon substrates are becoming increasingly more dense. Consequently, the interconnections between various circuit elements and dielectric layers needs to be as small as possible. One way to reduce the size of interconnection lines and vias is to use copper (Cu) as the interconnect material instead of conventionally used materials such as aluminum (Al). Because copper has a conductivity approximately twice that of aluminum, the number of metal layers required will be less.
 However, the use of copper as the interconnect material presents various problems. For example, there is currently no production-worthy etch process for Cu. This necessitates the use of a dual damascene “inlaid” approach. In the dual damascene approach, a dielectric or insulating diffusion barrier layer is deposited over a copper layer. The dielectric layer is then patterned, e.g., by conventional masking and etching techniques, to form a two-step connection having a narrower lower portion (or via portion) exposing desired connection areas on the underlying patterned metal layer and a wider upper portion (or trench portion) that will form the next layer of metal lines. The trench portion can be formed first or the via portion can be formed first (e.g., completely etching the dielectric layer down to the semiconductor substrate). Copper is then deposited to fill the two-step connection, such as by an “electrofill (electrochemical deposition)” process. The copper is then removed, e.g., by a chemical mechanical polish (CMP) process. The resulting structure is a via (the filled via portion) connecting the desired areas in the underlying metal layer with an overlying copper line (the filled trench portion).
 In the dual damascene approach, the contact to the devices in the semiconductor substrate is usually made with Tungsten (W) plugs. Copper (Cu) can be used for subsequent metal layers. There could be variations in this regard with some manufacturers using Cu for some layers and Al for the others. However, when Cu is used, the copper atoms must be prevented from migrating or diffusing into adjacent dielectric oxide or other inter-layer dielectric layers, which can compromise their integrity as an insulator. Thus, when using Cu, a dielectric diffusion barrier (DDB) is typically formed between the top of the Cu metal line or layer and a subsequently deposited ILD layer to prevent copper atom migration into the ILD layer. The ILD layer is then etched to define a via and a next level of copper lines. The two-step connection for the via and line can be formed using, e.g., a “timed” etch or an etchstop layer. A timed etch approach partially etches the ILD first. The etchstop approach utilizes an etchstop layer separating the ILD layer between the via and line. So the stack of the ILD would have a ILD layer (via level) followed by an etchstop layer at the desired height followed by an ILD layer (line level) on the etchstop layer. The via hole is defined first by photolithography. The vias are just vertical interconnections between a line above and a line below. So, when the lines are defined, we do not want the etch to continue below the desired vertical height. The etchstop layer precisely defines the line by not allowing etching beyond the etchstop layer.
 Once the etching is done, Tantalum (Ta) or Tantalum Nitride (TaN) followed by a Cu seed layer is deposited, i.e. by PVD. This is followed by a fill of the line and the via hole with electrochemical deposition of Cu, such as using a process called electrofill by those skilled in the art. Excess copper is then removed by a Cu CMP step. Once the CMP step is completed, it is followed by CuOx reduction step and another DDB deposition step. Thus, DDB layers between dielectric layers and metal lines prevent copper atoms from diffusing into the ILD layers.
 Typical materials used for the dielectric diffusion barrier are silicon nitride (SiN). Silicon carbide (SiC) is being considered since it can be made with a lower dielectric constant than SiN. For example, a SiC diffusion barrier can be formed using silane (SiH4) and methane (CH4) gases, with the flow rate of SiH4 varying between 100 and 500 sccm and the flow rate of CH4 varying between 9000 and 12000 sccm. The silicon carbide diffusion barrier is effective in preventing the migration of metal or copper atoms between adjacent metal layers. However, because silicon carbide is a semiconductor material, it can also exhibit a high leakage current, e.g., 300 μA/cm2 at an electric field strength of 106 V/cm.
 Accordingly, a barrier layer is desired that is effective in preventing the migration of metal atoms while also exhibiting low leakage current.
 In accordance with the present invention, a barrier layer is formed with a silicon carbon (or carbo) nitride (SICN) material. A SICN barrier layer is effective both in preventing metal atom migration and in reducing leakage current, e.g., a leakage current of 90 nA/cm2 has been measured in a 106 V/cm electric field, compared to a 300 μA/cm2 leakage current using a SiC barrier layer.
 In one embodiment, the SICN layer is formed by adding ammonia (NH3) gas to silane (SiH4) and methane (CH4) gas in a plasma enhanced chemical vapor deposition (PECVD) chamber, with flow rates of the NH3 ranging from 500 to 4000 sccm. In other embodiments, the SICN layer is formed by adding inert gases to methylsilane (CH3SiH3), dimethylsilane (CH3(SiH2)2), trimethylsilane (CH3(SiH)3), or tetramethylsilane (Si(CH3)4) in conjunction with NH3. Deposition can be performed in either single station or multi-station PECVD chambers. The SICN layer can also be formed using a high density plasma (HDP) deposition process with feed gases of 1) SiH4, C2H2, and N2 or 2) SiH4, CH4, and N2. Prior to forming the SiCN layer, the underlying metal or copper lines can be cleaned by using hydrogen or ammonia feed gases in PECVD or HDP chambers to remove the copper oxides. When cleaning in a PECVD chamber, the flow rates of NH3 or H2 range between 50 and 8000 sccm or higher, with the HFRF and LFRF power between 50 and 4000 W. When using an HDP chamber, typically flow rates of hydrogen range from 0 to 2000 sccm with a LFRF power range of 500 to 4000 W.
 In other embodiments of the present invention, the SiCN layer can be used as an etchstop layer when forming a two-step connection using a dual damascene process. A first dielectric layer is deposited on the copper or metal lines, where the first dielectric layer thickness is approximately the height of the via. After the via is formed, the SiCN layer is deposited and a second dielectric layer is deposited over the SiCN layer. This second dielectric layer is then patterned and etched to form the copper line, thereby resulting in the two-step connection. The SiCN layer prevents the etching of the second dielectric layer to encroach on the first dielectric layer. The SiCN layer can also be used as a passivation layer to prevent scratches to the device.
 This invention will be more fully understood in light of the following detailed description taken together with the accompanying drawings.
FIG. 1A is a cross-sectional view of a semiconductor device utilizing a silicon carbon nitride (SiCN) layer according to one embodiment of the present invention;
FIG. 1B is a cross-sectional view of a semiconductor device utilizing a silicon carbon nitride (SiCN) layer according to another embodiment of the present invention;
FIG. 2A is a graph of the leakage current as a function of the electric field in a silicon carbide (SiC) layer; and
FIG. 2B is a graph of the leakage current as a function of the electric field in a SiCN layer.
 Use of the same reference numbers in different figures indicates similar or like elements.
 In accordance with an embodiment of the present invention, a silicon carbon nitride (SiCN) layer is provided that has a low leakage current and is effective in preventing metal atoms from migrating or diffusing through the SiCN layer. Thus, when compared to conventional silicon carbide (SiC) layers, the SiCN layer, while similarly effective in blocking the migration of metal atoms through the layer, also exhibits a low leakage current, contrary to the high leakage current associated with SiC barrier layers. Thus, the SiCN layer can be used as a diffusion barrier between a metal layer and a dielectric layer to replace the conventional SiC diffusion barrier layer. The SiCN layer can also be used as an etchstop layer, such as in a dual damascene process, or a passivation layer for scratch protection.
FIG. 1A shows a dual damascene structure in which a SICN layer can be used, according to one embodiment. A copper (Cu) line 110 is first covered with a silicon carbon (or carbo) nitride SiCN dielectric diffusion barrier (DDB) 115. Before depositing the DDB, the Cu surface can be improved by removing of any copper oxide that may be remaining on the surface. Typically a hydrogen (H2) or an ammonia (NH3) plasma based reduction is used before the deposition of DDB 115. This copper surface reduction to remove CMP residue (e.g., Cu oxide) can be performed in a PECVD or a HDP chamber. Typical gases, flow rates, and powers used in the PECVD chamber are as follows: NH3 or H2 50-8000 sccm or higher, HFRF power: 50-4000 W, LFRF power: 50-4000 W. In the HDP chamber, typically flow rates of hydrogen is 0-2000 sccm with a LFRF power of 500-4000 W, which can also remove etch residue. This reduction has the benefit of removing CMP residues from the CMP step and the clean that follows.
 On top of Cu line 110, the SiCN DDB layer 115 is deposited. After the deposition of DDB layer 115, an interlevel dielectric (ILD) layer 120 is deposited. The thickness of ILD layer 120 is such that both a line and a via can be defined. ILD layer 120 is etched in a two-step etch so that a line 140 and a via 145 can be fabricated in the “inlaid” dual damascene fashion, as is known to those skilled in the art. A “timed” etch can be used to first etch a hole (for the via) and then etch a trench (for the line) in ILD layer 120. The via hole etch also etches the underlying portion of DDB layer 115 to allow metallic contact with the underlying metal line. Alternatively, an “etchstop” layer 125 can be used for etching the hole and trench, as shown in FIG. 1B. A first ILD layer 120A is deposited over DDB layer 115, where the thickness of ILD layer 120A is approximately the height of via 145. ILD layer 120A is patterned and etched to create the via hole. The portion of DDB layer 115 over the via hole is also etched to expose the underlying metal line. A SiCN etchstop layer 125 is deposited over ILD layer 120A, followed by deposition of a second ILD layer 120B, where the thickness of second ILD layer 120B is the depth of line 140. Note that the total thickness of ILD layers 120A and 120B is approximately the same as ILD layer 120 of FIG. 1A. Second ILD layer 120B is then patterned and etched to create the trench. SiCN etchstop layer 125 prevents the etching of second ILD layer 120B from continuing into first ILD layer 120A.
 After the etch processes creating the via hole and trench are completed, the next step is the metallic (conductive) diffusion barrier deposition (not shown). Tantalum (Ta) and Tantalum Nitride (TaN) are suitable materials, which are deposited by PVD in the form of a thin layer, e.g., approximately 150 Å thick. Over the Ta or TaN diffusion barrier layer, a Cu seed layer is deposited, typically about 1500 Å thick. The Cu seed is deposited so as to allow electroplated Cu to fill the trench and the via hole without voids. The next step is the electroplating or the electrofill of the trench and the via hole, as is known to those skilled in the art. Once the Cu fill is completed, a desired line 140 and via 145 are formed in the trench and via hole, respectively. The above described process can then be repeated to form a desired multi-level structure. A final SiCN layer can also be deposited as a passivation layer (not shown) for protecting the device from scratching. The SICN dielectric diffusion barrier (DDB) layer is critical as it effectively prevents copper diffusion into the ILD layers, while exhibiting low leakage current as shown in FIGS. 2A and 2B.
FIGS. 2A and 2B are experimental plots showing the leakage current (in units of A/cm2) as a function of the electric field (in units of MV/cm) in a conventional SiC barrier layer and in a SiCN barrier layer of the present invention, respectively. At 1 MV/cm, the leakage current is approximately 300 μA/cm2 in a SiC barrier (FIG. 2A), compared to that of approximately 100 nA/cm2 in a SiCN barrier (FIG. 2B). Thus, utilizing a SiCN barrier layer, as opposed to a SiC barrier layer, the leakage current is reduced by a factor of 3000 at an electric field of 1 MV/cm, while still maintaining the same effectiveness in preventing copper diffusion. Furthermore, the resulting SiCN layer has a relatively low dielectric constant, typically between around 5.3 and 6.3, depending on the mixture and ratio of gases used to form the SiCN.
 The SiCN layer can be deposited in various ways. One suitable method involves deposition in a plasma enhanced chemical vapor deposition (PECVD) chamber. In PECVD, the desired feed gases are reacted by passing them through a plasma field. The plasma used in such processes can comprise energy derived from a variety of sources such as electric discharges, electromagnetic fields in the radio-frequency or microwave range, lasers or particle beams. The specific frequency, power, and pressure are generally adjusted for the application, wafer size, reaction chamber, etc. In PECVD reactors the coupling between the plasma and the power is capacitive, resulting in low plasma density. The combination of low plasma density and high pressure results in negligible film sputtering in PECVD deposition. In addition, those skilled in the art will understand that the rate of film deposition in PECVD processes may increase with the amount of bias power applied to the wafer.
 One way of depositing SiCN using PECVD deposition involves feeding silane (SiH4), methane (CH4), and ammonia (NH3) to the PECVD chamber. Table 1 below lists the three gases for deposition of a SICN layer and their respective gas flow ranges, with the actual gas flow amount dependent upon the application and wafer size.
TABLE 1 Gas Flow Rate (sccm) SiH4 100-500 CH4 9000-12000 NH3 500-4000
 Note that NH3 flow rates of 1500 sccm and 3000 sccm both produced a SiCN layer with a measured leakage current of around 90 nA/cm2 at an electric field of 1 MV/cm. It was also noted that at NH3 flow rates above 4000 sccm, the resulting material started resembling a nitride, while at flow rates below 500 sccm, the resulting material behaved like silicon carbide. Table 2 below lists various process parameters and ranges for a SiCN deposition step. Note that the SiCN can be deposited using both multistation and single station deposition.
TABLE 2 Parameter Range Pressure (Torr) 1.0-4.0 Temperature (° C.) 300-450 LF Power (kW) 0-1 HF Power (kW) 0-1
 Other gases can also be used for PECVD deposition, such as methylsilane (CH3SiH3), dimethylsilane (CH3(SiH2)2), trimethylsilane (CH3(SiH)3), or tetramethylsilane (Si(CH3)4). NH3 is added to the methylsilanes to create the SiCN layer. N2 and SiH4 may also be used to adjust the composition. The system parameters will be the same as in Table 2.
 Instead of using PECVD, the SiCN layer can also be deposited using high density plasma (HDP) deposition. Feed gases of 1) SiH4, C2H2, and N2 or 2) SiH4, CH4, and N2 can be used to form the SiCN layer using an HDP process. HDP chemical vapor deposition (CVD) processes typically operate at a pressure range several (two to three) orders of magnitude lower than corresponding PECVD processes (i.e., in the milliTorr range). Moreover, in an HDP reactor, power is coupled inductively, instead of capacitively, to the plasma, resulting in higher plasma density. Consequently, in an HDP reactor, because of the pressure and plasma characteristics, the atoms impinging on the depositing film surface are much more energetic than in a PECVD reactor, such that gas-solid collisions may result in sputtering of the deposited film. Another characteristic of HDP deposition is that increased bias power applied to the wafer results in an increased in situ sputter etch component, thereby decreasing the deposition rate.
 The differences in the physics and chemistry of PECVD and HDP processes result in significant differences in the growth of the deposited film. For example, in PECVD processes, plasma is used to generate deposition precursors, which in turn, are driven to the wafer surface by applied bias power to the wafer. Because of the relatively high pressure of operation (on the order of 1 Torr, compared to a few milliTorr for HDP processes), the ions experience a large number of collisions. As a result, the flux of deposition precursor species to the wafer surface is distributed.
 The above-described embodiments of the present invention are merely meant to be illustrative and not limiting. It will thus be obvious to those skilled in the art that various changes and modifications may be made without departing from this invention in its broader aspects. For example, the above description described the use of a silicon carbon nitride layer, which has a low leakage current and prevents metal atom migration through the SiCN layer, as a diffusion barrier for copper or metal interconnection layers. However, the properties of the SICN layer also make such a layer suitable as an etchstop or a passivation layer for protecting the semiconductor device. An etchstop layer is used in dual damascene fabrication sequence in defining a line and a via. The passivation layer is used for protection from scratches and for protection from metal ions such as sodium. Therefore, the appended claims encompass all such changes and modifications as fall within the true spirit and scope of this invention.
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6579786 *||Nov 19, 2001||Jun 17, 2003||Infineon Technologies Ag||Method for depositing a two-layer diffusion barrier|
|US6812134 *||Jun 28, 2001||Nov 2, 2004||Lsi Logic Corporation||Dual layer barrier film techniques to prevent resist poisoning|
|US6849561 *||Aug 18, 2003||Feb 1, 2005||Asm Japan K.K.||Method of forming low-k films|
|US6878628 *||Oct 9, 2001||Apr 12, 2005||Asm International Nv||In situ reduction of copper oxide prior to silicon carbide deposition|
|US6887795||Nov 19, 2002||May 3, 2005||Asm International N.V.||Method of growing electrical conductors|
|US6919270||Oct 9, 2003||Jul 19, 2005||Asm Japan K.K.||Method of manufacturing silicon carbide film|
|US6949442||May 5, 2003||Sep 27, 2005||Infineon Technologies Ag||Methods of forming MIM capacitors|
|US6991959||Nov 25, 2003||Jan 31, 2006||Asm Japan K.K.||Method of manufacturing silicon carbide film|
|US7067407||Aug 3, 2004||Jun 27, 2006||Asm International, N.V.||Method of growing electrical conductors|
|US7071094 *||Jul 16, 2004||Jul 4, 2006||Lsi Logic Corporation||Dual layer barrier film techniques to prevent resist poisoning|
|US7138332||Jul 9, 2003||Nov 21, 2006||Asm Japan K.K.||Method of forming silicon carbide films|
|US7238393||Apr 14, 2003||Jul 3, 2007||Asm Japan K.K.||Method of forming silicon carbide films|
|US7244674||Apr 27, 2004||Jul 17, 2007||Agency For Science Technology And Research||Process of forming a composite diffusion barrier in copper/organic low-k damascene technology|
|US7335990||Jul 3, 2007||Feb 26, 2008||Agency For Science, Technology And Research||Process of forming a composite diffusion barrier in copper/organic low-k damascene technology|
|US7393780||May 4, 2006||Jul 1, 2008||Lsi Corporation||Dual layer barrier film techniques to prevent resist poisoning|
|US7419903||Apr 13, 2005||Sep 2, 2008||Asm International N.V.||Thin films|
|US7425392 *||Aug 26, 2005||Sep 16, 2008||Motorola, Inc.||Lithographic template and method of formation and use|
|US7436016||Aug 23, 2005||Oct 14, 2008||Infineon Technologies Ag||MIM capacitor with a cap layer over the conductive plates|
|US7476971 *||May 11, 2006||Jan 13, 2009||Toshiba America Electronic Components, Inc.||Via line barrier and etch stop structure|
|US7491634||Apr 28, 2006||Feb 17, 2009||Asm International N.V.||Methods for forming roughened surfaces and applications thereof|
|US7494927||Mar 20, 2003||Feb 24, 2009||Asm International N.V.||Method of growing electrical conductors|
|US7498242||Feb 21, 2006||Mar 3, 2009||Asm America, Inc.||Plasma pre-treating surfaces for atomic layer deposition|
|US7501291||Apr 19, 2006||Mar 10, 2009||Stmicroelectronics Sa||Process for fabricating an integrated circuit including a capacitor with a copper electrode|
|US7541284||Feb 14, 2007||Jun 2, 2009||Asm Genitech Korea Ltd.||Method of depositing Ru films having high density|
|US7563715||Dec 5, 2005||Jul 21, 2009||Asm International N.V.||Method of producing thin films|
|US7655564||Dec 12, 2007||Feb 2, 2010||Asm Japan, K.K.||Method for forming Ta-Ru liner layer for Cu wiring|
|US7666773||Mar 14, 2006||Feb 23, 2010||Asm International N.V.||Selective deposition of noble metal thin films|
|US7799674||May 29, 2008||Sep 21, 2010||Asm Japan K.K.||Ruthenium alloy film for copper interconnects|
|US7799680||Jan 9, 2007||Sep 21, 2010||Asm America, Inc.||Surface preparation prior to deposition on germanium|
|US7843035||Jul 30, 2008||Nov 30, 2010||Infineon Technologies Ag||MIM capacitors with catalytic activation layer|
|US7923382||Feb 10, 2009||Apr 12, 2011||Asm International N.V.||Method for forming roughened surface|
|US7955979||Feb 28, 2008||Jun 7, 2011||Asm International N.V.||Method of growing electrical conductors|
|US7972977||Oct 5, 2007||Jul 5, 2011||Asm America, Inc.||ALD of metal silicate films|
|US7981791||Aug 29, 2008||Jul 19, 2011||Asm International N.V.||Thin films|
|US7985669||Dec 30, 2009||Jul 26, 2011||Asm International N.V.||Selective deposition of noble metal thin films|
|US8025922||Mar 14, 2006||Sep 27, 2011||Asm International N.V.||Enhanced deposition of noble metals|
|US8084104||Aug 29, 2008||Dec 27, 2011||Asm Japan K.K.||Atomic composition controlled ruthenium alloy film formed by plasma-enhanced atomic layer deposition|
|US8133555||Oct 14, 2008||Mar 13, 2012||Asm Japan K.K.||Method for forming metal film by ALD using beta-diketone metal complex|
|US8252703||Apr 11, 2011||Aug 28, 2012||Asm International N.V.||Methods for forming roughened surfaces and applications thereof|
|US8329569||Jul 2, 2010||Dec 11, 2012||Asm America, Inc.||Deposition of ruthenium or ruthenium dioxide|
|US8383525||Apr 25, 2008||Feb 26, 2013||Asm America, Inc.||Plasma-enhanced deposition process for forming a metal oxide thin film and related structures|
|US8501275||Sep 21, 2011||Aug 6, 2013||Asm International N.V.||Enhanced deposition of noble metals|
|US8536058||Jun 3, 2011||Sep 17, 2013||Asm International N.V.||Method of growing electrical conductors|
|US8545936||Mar 28, 2008||Oct 1, 2013||Asm International N.V.||Methods for forming carbon nanotubes|
|US8563444||Jul 1, 2011||Oct 22, 2013||Asm America, Inc.||ALD of metal silicate films|
|US8664127||Jul 14, 2011||Mar 4, 2014||Applied Materials, Inc.||Two silicon-containing precursors for gapfill enhancing dielectric liner|
|US8716154||Oct 3, 2011||May 6, 2014||Applied Materials, Inc.||Reduced pattern loading using silicon oxide multi-layers|
|US8878331 *||Oct 24, 2012||Nov 4, 2014||Stmicroelectronics (Crolles 2) Sas||Method for manufacturing insulated-gate MOS transistors|
|US8889566||Nov 5, 2012||Nov 18, 2014||Applied Materials, Inc.||Low cost flowable dielectric films|
|US8927403||Jul 21, 2011||Jan 6, 2015||Asm International N.V.||Selective deposition of noble metal thin films|
|US9018108||Mar 15, 2013||Apr 28, 2015||Applied Materials, Inc.||Low shrinkage dielectric films|
|US9129897||Apr 20, 2012||Sep 8, 2015||Asm International N.V.||Metal silicide, metal germanide, methods for making the same|
|US9139906||Feb 27, 2008||Sep 22, 2015||Asm America, Inc.||Doping with ALD technology|
|US9144147||Feb 21, 2013||Sep 22, 2015||Applied Materials, Inc.||Semiconductor processing system and methods using capacitively coupled plasma|
|US20040115876 *||Nov 25, 2003||Jun 17, 2004||Asm Japan K.K.||Method of manufacturing silicon carbide film|
|US20040161535 *||Apr 14, 2003||Aug 19, 2004||Goundar Kamal Kishore||Method of forming silicon carbide films|
|US20040224474 *||May 5, 2003||Nov 11, 2004||Hans-Joachim Barth||Single mask MIM capacitor top plate|
|US20040253784 *||Jul 16, 2004||Dec 16, 2004||Lsi Logic Corporation||Dual layer barrier film techniques to prevent resist poisoning|
|US20050009320 *||Jul 9, 2003||Jan 13, 2005||Goundar Kamal Kishore||Method of forming silicon carbide films|
|US20050042883 *||Aug 18, 2003||Feb 24, 2005||Goundar Kamal Kishore||Method of forming low-k films|
|US20050059234 *||Sep 16, 2003||Mar 17, 2005||Applied Materials, Inc.||Method of fabricating a dual damascene interconnect structure|
|US20050181555 *||Apr 13, 2005||Aug 18, 2005||Haukka Suvi P.||Thin films|
|US20050208754 *||Aug 3, 2004||Sep 22, 2005||Juhana Kostamo||Method of growing electrical conductors|
|US20050210455 *||Feb 11, 2005||Sep 22, 2005||International Business Machines Corporation||Method for generating an executable workflow code from an unstructured cyclic process model|
|US20050282346 *||Aug 23, 2005||Dec 22, 2005||Hans-Joachim Barth||MIM capacitors|
|US20060019493 *||Jul 11, 2005||Jan 26, 2006||Li Wei M||Methods of metallization for microelectronic devices utilizing metal oxide|
|US20060177601 *||Feb 10, 2005||Aug 10, 2006||Hyung-Sang Park||Method of forming a ruthenium thin film using a plasma enhanced atomic layer deposition apparatus and the method thereof|
|US20060205203 *||May 4, 2006||Sep 14, 2006||Lsi Logic Corporation||Dual layer barrier film techniques to prevent resist poisoning|
|US20060216932 *||Feb 21, 2006||Sep 28, 2006||Devendra Kumar||Plasma pre-treating surfaces for atomic layer deposition|
|US20060240576 *||Apr 19, 2006||Oct 26, 2006||Stmicroelectronics Sa||Process for fabricating an integrated circuit including a capacitor with a copper electrode|
|US20070014919 *||Jul 15, 2005||Jan 18, 2007||Jani Hamalainen||Atomic layer deposition of noble metal oxides|
|US20130099329 *||Apr 25, 2013||Stmicroelectronics (Crolles 2) Sas||Method for manufacturing insulated-gate mos transistors|
|US20130217243 *||Aug 21, 2012||Aug 22, 2013||Applied Materials, Inc.||Doping of dielectric layers|
|CN100540730C||Mar 18, 2008||Sep 16, 2009||浙江理工大学||Method for manufacturing carbon silicon nitride film|
|CN102403220A *||Sep 17, 2010||Apr 4, 2012||中芯国际集成电路制造(上海)有限公司||Preparation process of SiCN diffusion barrier layer|
|WO2004100232A1 *||May 5, 2004||Nov 18, 2004||Barth Hans-Joachim||Method for forming the top plate of a mim capacitor with a single mask in a copper dual damascene integration scheme|
|U.S. Classification||257/751, 257/E21.266, 257/E23.157, 257/E21.292, 257/E21.293, 257/E23.164, 257/E21.27|
|International Classification||H01L23/532, H01L21/314, H01L21/318|
|Cooperative Classification||H01L21/318, H01L23/53209, H01L23/53271, H01L2924/0002, H01L21/3146, H01L21/314, H01L21/3185|
|European Classification||H01L23/532M2, H01L21/314, H01L21/318, H01L23/532M1|
|Sep 30, 1999||AS||Assignment|
Owner name: NOVELLUS SYSTEMS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUNDARARAJAN, SRINIVASAN;TRIVEDI, MAYUR;REEL/FRAME:010287/0606
Effective date: 19990928
|Jan 16, 2007||FPAY||Fee payment|
Year of fee payment: 4
|Jan 18, 2011||FPAY||Fee payment|
Year of fee payment: 8
|Jan 15, 2015||FPAY||Fee payment|
Year of fee payment: 12