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Publication numberUS20020027287 A1
Publication typeApplication
Application numberUS 09/111,799
Publication dateMar 7, 2002
Filing dateJul 8, 1998
Priority dateJul 8, 1997
Also published asUS6440844
Publication number09111799, 111799, US 2002/0027287 A1, US 2002/027287 A1, US 20020027287 A1, US 20020027287A1, US 2002027287 A1, US 2002027287A1, US-A1-20020027287, US-A1-2002027287, US2002/0027287A1, US2002/027287A1, US20020027287 A1, US20020027287A1, US2002027287 A1, US2002027287A1
InventorsHideo Takagi, Kiyoshi Izumi, Wataru Futo, Satoshi Otsuka, Shigetaka Uji, Masataka Hoshino, Yukihiro Satoh, Koji Endo, Yuzuru Ohta, Nobuhiro Misawa
Original AssigneeFujitsu Limited
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device with copper wiring and its manufacture method
US 20020027287 A1
Abstract
To reduce the connection resistance between copper wirings, and to improve the reliability of the wiring such as anti-electromigration characteristics.
1) a semiconductor device having a wiring structure in which an upper and a lower copper wirings are formed through an interlayer insulation film, and the upper and lower copper wirings are connected with a tungsten plug, 2) a-high density barrier layer is formed between the copper and the tungsten, 3) said copper wiring is embedded in a groove formed in an insulation film, 4) for forming an embedded copper wiring, a barrier metal is formed in a groove, a copper film is deposited by sputtering to a thickness above the depth of the groove, reflowed by heating to a temperature of 300 ˜450 C., and polished to leave a copper wiring in the groove, 5) a lower layer copper wiring and an insulation film are deposited, and a planarizing insulation film is formed thereon, 6) a copper wiring is formed, and reduced in a reducing gas, and without exposing to the atmosphere, an insulation film is deposited.
Images(7)
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Claims(11)
What is claimed is:
1] a semiconductor device characterized by having a wiring structure in that an upper and a lower copper wirings are formed through an interlayer insulating film, and said upper and lower copper wirings are connected with a tungsten plug:
2] The semiconductor device as described in claim 1, characterized in that a titanium nitride film is interposed between said copper wiring and said tungsten plug, and said titanium nitride film has much (200) plane than (111) plane.
3] The semiconductor device as described in claim 1, characterized in that said copper wiring is embedded in a trench formed in an insulating film.
4] The semiconductor device as described in claim 1, characterized in that the cross section of said copper wiring is larger than the cross section of said tungsten plug in the current direction.
5] A method of manufacturing a semiconductor device characterized by comprising the steps of:
forming an insulation film on a semiconductor substrate;
then forming a trench in said insulating film;
then forming a copper wiring in said trench;
then forming an interlayer insulating film on said semiconductor substrate, and forming a connection hole in said interlayer insulating film to expose said copper wiring;
then, embedding said connection hole with tungsten to form a plug; and
then, forming an upper copper wiring connected with said plug.
6] The method of manufacturing a semiconductor device as described in claim 5, characterized in that upon forming the copper wiring, the method further comprises the step of forming a film of a compound containing a refractory metal or a nitride of a refractory metal as a barrier metal in said trench.
7] The method of manufacturing a semiconductor device as described in claim 5, characterized by further comprising upon forming the copper wiring, the steps of:
depositing, using sputtering, a copper film to a thickness exceeding the depth of said trench;
then heating said copper film to a temperature of 300˜450 C. reflow the copper film;
then polishing said copper film to form a copper wiring in said trench.
8] The method of manufacturing a semiconductor device as described in claim 5, characterized by further comprising, upon forming a tungsten plug, the steps of:
depositing a refractory metal film containing nitrogen covering a connection hole formed in an interlayer insulating film;
then depositing a tungsten film, embedding said connection hole;
then removing by polishing the refractory metal film containing nitrogen and a tungsten film on the interlayer insulating film, to planarize the surface.
9] A method of manufacturing a semiconductor device characterized by comprising the steps of:
forming a copper wiring in a trench formed in an insulating film; and
forming a planarizing insulating film on said insulating film, to planarize the substrate surface.
10] A method of manufacturing a semiconductor device characterized by comprising the steps of:
forming a copper wiring;
heating the substrate in a reductive gas to a temperature over 250 C., or reducing an oxide film on a surface of said copper wiring in a plasma of a reductive gas;
then, without exposing said copper wiring to an external atmosphere, depositing an insulating film on said copper wiring.
11] A method of manufacturing a semiconductor device characterized by comprising the steps of:
forming a connection hole in an insulating film formed on a copper wiring;
heating the substrate in a reductive gas to a temperature over 250 C., or reducing an oxide film on a surface of said copper wiring in a plasma of a reducing gas; and
then depositing a metal for connection on said copper wiring,
Description
    DETAILED DESCRIPTION OF THE INVENTION
  • [0001]
    1. Technical Field to Which the Invention Belongs
  • [0002]
    This invention relates to a semiconductor device and its manufacturing method and more particularly to a method of embedding and connecting a copper (Cu) wiring and the structure.
  • [0003]
    Copper wiring is required a high anti-electromigration characteristics and a high grade embedding characteristics.
  • [0004]
    2. Conventional Art
  • [0005]
    Copper wiring is hard to be patterned by using reactive ion etching (RIE), as employed in patterning the conventional aluminum (Al) wiring, and hence embedded wiring is solely employed.
  • [0006]
    As the technique of embedding a via hole through an interlayer insulating film formed on a conventional copper wiring, those embedding methods are proposed such as a method by chemical vapor deposition (CVD) of copper and deposition by electroplating.
  • [0007]
    However, according to the CVD method or the electroplating method, many impurities are contained in the copper, and it is difficult to obtain high reliability against electromigration, etc.
  • [0008]
    Subject to be Solved by the Invention
  • [0009]
    An object of this invention is to reduce the connection resistance between copper wirings, and to improve the reliability of the copper wiring such as anti-electromigration characteristics.
  • [0010]
    Mean for Solving the Subject
  • [0011]
    The solution to the above subject can be achieved by:
  • [0012]
    1) a semiconductor device characterized by having a wiring structure in that an upper and a tower copper wirings are formed through an interlayer insulating film, and said upper and lower copper wirings are connected with a tung{tilde over (s)}ten plug; or
  • [0013]
    2) the semiconductor device as described in said 1, characterized in that a titanium nitride film is interposed between said copper wiring and said tungsten plug, and said titanium nitride film has much (200) plane than (111) plane; or
  • [0014]
    3) the semiconductor device as described in said 1, characterized in that said copper wiring is embedded in a trench formed in an insulating film; or
  • [0015]
    4) the semiconductor device as described in said 1, characterized in that the cross section of said copper wiring is larger than the cross section of said tungsten plug in the current direction; or
  • [0016]
    5) a method of manufacturing a semiconductor device characterized by comprising the steps of: forming an insulation film on a semiconductor substrate; then forming a trench in said insulating film; then forming a copper wiring in said trench; then forming an interlayer insulating film on said semiconductor substrate, and forming a connection hole in said interlayer insulating film to expose said copper wiring; then, embedding said connection hole with tungsten to form a plug; and then, forming an upper copper wiring connected with said plug; or
  • [0017]
    6) the method of manufacturing a semiconductor device as described in said 5, characterized in that upon forming the copper wiring, the method further comprises the step of forming a film of a compound containing a refractory metal or a nitride of a refractory metal as a barrier metal in said trench; or
  • [0018]
    7) the method of manufacturing a semiconductor device as described in said 5, characterized by further comprising upon forming the copper wiring, the steps of: depositing, using sputtering, a copper film to a thickness exceeding the depth of said trench; then heating said copper film to a temperature of 300˜450C. to reflow the copper film; then polishing said copper film to form a copper wiring in said trench; or
  • [0019]
    8) the method of manufacturing a semiconductor device as described in said 5, characterized by further comprising, upon forming a tungsten plug, the steps of: depositing a refractory metal film containing nitrogen covering a connection hole formed in an interlayer insulating film; then depositing a tungsten film, embedding said connection hole; then removing by polishing the refractory metal film containing nitrogen and a tungsten film on the interlayer insulating film, to planarize the surface; or
  • [0020]
    9) a method of manufacturing a semiconductor device characterized by comprising the steps of: forming a copper wiring in a trench formed in an insulating film; and forming a planarizing insulating film on said insulating film, to planarize the substrate surface; or
  • [0021]
    10) a method of manufacturing a semiconductor device characterized by comprising the steps of: forming a copper wiring; heating the substrate in a reductive gas to a temperature over 250 C., or reducing an oxide film on a surface of said copper wiring in a plasma of a reductive gas; then, without exposing said copper wiring to an external atmosphere, depositing an insulating film on said copper wiring; or
  • [0022]
    11) a method of manufacturing a semiconductor device characterized by comprising the steps of: forming a connection hole in an insulating film formed on a copper wiring; heating the substrate in a reductive gas to a temperature over 250 C., or reducing an oxide film on a surface of said copper wiring in a plasma of a reducing gas; and then depositing a metal for connection on said copper wiring.
  • [0023]
    [0023]FIG. 1 is a diagram for explaining the principle of this invention.
  • [0024]
    In the figure, an upper and a lower copper wirings 11, 15 formed by sputtering are connected with a plug of tungsten (W), which is refractory metal, to form an electrical contact.
  • [0025]
    Copper formed by sputtering has a high purity and a high resistance against electromigration.
  • [0026]
    However, the sputtered copper does not have a sufficient coverage to embed a via hole. If a CVD copper film having a good coverage is used, it is possible to embed a via hole, but the anti-electromigration characteristics becomes inferior.
  • [0027]
    Hence, this invention employs a tungsten plug 13 having a high anti-electromigration characteristics in a device which is required for a high current density (8105A/cm2 or above), or in a via hole where a current of higher current density than in the embedded copper wiring flows.
  • [0028]
    In the case of forming a tungsten plug 13 on a copper wiring 11, for preventing diffusion of WF6, which is a row gas of tungsten, to a copper wiring 11, a titanium nitride (TiN) film 12 of sufficient thickness and high density is deposited on the bottom of a via hole, to obtain a contact of low resistance.
  • [0029]
    If a step A of a recess is formed on a copper wiring 11, a TIN film 12 under a tungsten plug 13 remains as a residue after mechanical chemical polishing (CMP) at a neighborhood of a location B. This is due to the fact that the shape of the step A is directly transferred to an upper layer.
  • [0030]
    This step A can be planarized as shown in the figure by using a spin on glass (SOG) film 5. By this, no residue remains after CMP of the tungsten plug 13. This also holds in the case of a plug using copper, as well a tungsten plug.
  • [0031]
    When an insulating film 4 is deposited on a copper wiring 11, a native oxide film of copper is formed on the copper wiring 11. When a plasma silicon nitride (P-SiN) film is deposited thereon, for example, peel-off occurs ascribed to the native oxide film of copper. Therefore, the native oxide film of copper is reduced by using a gas having a reducing characteristics against an oxide film, such as hydrogen (H2) or ammonia (NH3) and keeping the substrate at a temperature of 200 C. or above, or in a plasma atmosphere, then a P-SiN film is deposited. Adherence between the copper wiring 11 and insulating film (P-SIN film) 4 can be secured by this.
  • [0032]
    As described above, a copper wiring having a high resistance against the electromigration can be obtained by this invention. Also, by inserting a planarizing process upon forming a plug on a trench wiring, residue of a plug after CMP is prevented from remaining on the wiring. Further, by reducing the native oxide film on a surface of a copper wiring, an insulating film having a good adherence can be formed on a copper wiring.
  • [0033]
    Mode for Carrying out the Invention
  • [0034]
    [0034]FIG. 2 is an explanatory drawing of the mode for carrying out this invention.
  • [0035]
    In the figure:
  • [0036]
    (1) By plasma CVD method, an LTO (low temperature deposition SiO)film of 500 nm thickness is formed as an interlayer insulation film 2 on silicon (Si) substrate 1.
  • [0037]
    Next, by plasma CVD method, a P-SIN film 2S of 50 nm thickness is formed as the etching stopper film during formation of the grooves for wiring.
  • [0038]
    (2.) Next, on top of it, by plasma CVD method, an LTO film of 350 nm thickness is formed as interlayer insulation film 3.
  • [0039]
    Here, it is acceptable for this film to contain a film of low dielectric constant, such as FSG (F doped silicate glass) or HSQ (Hydrogen silsesquioxane) and the like.
  • [0040]
    (3) Next, for forming the grooves for wiring in the interlayer insulation film 3, a photoresist film is coated, and exposed. By reactive ion etching (RIE), the LTO film of the interlayer insulation film 3 is etched using C4F8+CO+Ar gases and stopped by the layer of P-SIN film 2S underneath.
  • [0041]
    (4) Next, by sputtering method, a TiN film of 50 nm thickness is formed as a barrier metal film 10 for copper on the substrate. This barrier metal film 10 may also be nitrides of refractory metals like TaN, WN,TiSiN and the like. Also, in place of using the sputtering method, a TiN film by the method of metal organic chemical vapor deposition (MOCVD) is also acceptable.
  • [0042]
    (5) After the formation of the barrier metal film 10, without breaking the vacuum, by sputtering method, a copper film of 0.7 pm thickness is formed for forming a copper wiring 11.
  • [0043]
    At this time, the degree of vacuum reached is 9108 Torr. The sputtering conditions are as follows herein:
  • [0044]
    Ar gas pressure: 2mTorr
  • [0045]
    DC power: 12 kW
  • [0046]
    Distance between target/substrate: 150 mm
  • [0047]
    Substrate temperature: 150 C.
  • [0048]
    Film formation rate: 1.25μm /minute
  • [0049]
    (6) After the copper film is formed, it is annealed in an atmosphere of 100% hydrogen (H2), under a pressure of 100 mTorr, and at a temperature of 390 C., for 5 minutes, to make it re-flow.
  • [0050]
    (7) Next, by CMP method, the copper film and barrier metal film are polished, to form the copper wiring (groove wiring) 11.
  • [0051]
    (8) Next, the substrate is annealed in an atmosphere of 100% hydrogen, under a pressure of 20˜80 mTorr, and at a temperature of 250-350C., for 2 minutes, to reduce the natural oxide film on copper wiring 11. Then, by plasma CVD method, a SiN film of 50 nm thickness is formed as an insulation film 4 for preventing the diffusion of copper into the oxide film from the copper wiring.
  • [0052]
    (9) Next, an HSQ film is coated on the substrate to a thickness of 400 nm as planarization film 5, and cured at 400 C. for 30 minutes.
  • [0053]
    (10) Next, by plasma CVD method, an FSG (low temperature deposition SiO) film of 300 nm thickness is formed as interlayer insulation film 6.
  • [0054]
    (11) Next, by plasma CVD method, a P-SiN film 6S of 50 nm thickness is formed as the etching stopper film during the formation of the grooves for the upper layer wiring.
  • [0055]
    (12) Next, for forming via holes of 0.3μm φ, photoresist is coated, and exposed. By RIE method, 300 nm of the FSG film of interlayer insulation film 6, 400 nm of HSQ film of planarizing insulation film 5, and P-SiN film 4 underneath it are etched.
  • [0056]
    (13) Next, by Long Throw Method (method of forming a coated film of high density by separating the wafer and the target by over 300 mm, to make more perpendicular components of the flying sputtered particles), a sputtered TiN film of 50 nm thickness is deposited as a barrier metal film 12. After that, using CVD method, a tungsten film of 300 nm is deposited.
  • [0057]
    The orientation of this TiN film, (200) /(111) is 1.0˜3.0.
  • [0058]
    (14) Next, by CMP method, tungsten and TiN are polished, and tungsten plug 13 is formed in the via hole through TiN film 12.
  • [0059]
    (15) Next, through similar processes as (2) ˜(8) above, a copper wiring 15 is formed in grooves formed in an insulation film (LTO film) 7, through a barrier metal film 14.
  • [0060]
    (16) Next, as a cover film, a P-SiN film 8 of 1.0μm thickness is formed on the substrate.
  • [0061]
    By the above processes, a structure in which the upper and lower level buried copper wirings are connected with a tungsten plug 7 can be obtained.
  • [0062]
    The contact resistance of the connection between the upper and lower copper wirings with a tungsten plug formed by the embodiment is shown in FIG. 3.
  • [0063]
    The figure shows the cumulative occurrence (ordinate axis) with respect to the contact resistance (abscissa axis) in the via hole measured by the Kelvin method.
  • [0064]
    The diameter of the connection via hole is 0.44μm. The contact resistance is of the order of about 1ω,and the dispersion thereof is small (solid circles in the figure).
  • [0065]
    If a conventional TiN film having a strong (111) orientation is used in the step (13) in the embodiment, the dispersion of the contact resistance is large (open circles in the figure).
  • [0066]
    The result of electromigration of the upper and lower copper wirings with a tungsten plug formed by the embodiment is shown in FIG. 4.
  • [0067]
    The figure shows the time at which the failure rate becomes 50% (ordinate axis) with respect to the weight ratio of copper (abscissa axis) in the test at 200 C. and a current density of 2˜3 MA/cm2.
  • [0068]
    The two-layer wiring formed by the embodiment is shown by the solid circles. For comparison, the result with the conventional copper alloy with 0.5 ˜2.0% of A1 is shown by the solid rectangles.
  • [0069]
    As is apparent from this result, the copper wiring formed by the embodiment has a longer lifetime of about 1 digit longer than the conventional wiring of AlCu alloy wiring.
  • [0070]
    The Effect of the Invention
  • [0071]
    According to this invention, a low contact resistance can be obtained with respect to the connection between the upper and lower copper wirings. Also, the anti-electromigration characteristics of the wiring is improved. Further, when an insulation film is formed on the copper wiring, it will not be peeled off.
  • BRIEF DESCRIPTION of the DRAWINGS
  • [0072]
    [FIG. 1] diagram for explaining the principle of this invention.
  • [0073]
    [FIG. 2] diagram for explaining the embodiment of this invention.
  • [0074]
    [FIG. 3] diagram (1) illustrating the effect of this invention.
  • [0075]
    [FIG. 4] diagram (2) illustrating the effect of this invention
  • DESCRIPTION OF THE SYMBOLS
  • [0076]
    1 semiconductor substrate
  • [0077]
    2 insulation film
  • [0078]
    2S etching stopper film (SIN film)
  • [0079]
    3 insulation film (LTO film) at the same level as the wiring
  • [0080]
    4 insulation film (SIN film) for preventing diffusion of copper into the oxide film
  • [0081]
    5 planarizing insulation film (SOG film, HSQ film, etc)
  • [0082]
    6 interlayer insulation film (FSG film of LTO film with a low dielectric constant, etc.)
  • [0083]
    6Setching stopper film
  • [0084]
    7 insulation film (LTO film) at the same level as the wiring
  • [0085]
    8 cover film (SIN film)
  • [0086]
    10, 14 barrier metal film (TIN film, etc) 11,15 embedded copper wiring 12 barrier metal film (high density tin film with an orientation(200)/(111) of 1 or above) 13 tungsten plug
Referenced by
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US7498677 *Oct 14, 2005Mar 3, 2009Panasonic CorporationSemiconductor device
US7932187Feb 10, 2009Apr 26, 2011Panasonic CorporationMethod for fabricating a semiconductor device
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US20020119651 *Apr 24, 2002Aug 29, 2002Hitachi, Ltd.Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
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US20040197475 *Aug 13, 2002Oct 7, 2004Oliver StadelMethod for coating oxidizable materials with oxide containing layers
US20060081987 *Oct 14, 2005Apr 20, 2006Matsushita Electric Industrial Co., Ltd.Semiconductor device and method for fabricating the same
US20080138979 *Jan 23, 2008Jun 12, 2008Junji NoguchiSemiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
US20090149019 *Feb 10, 2009Jun 11, 2009Panasonic CorporationSemiconductor device and method for fabricating the same
US20160126185 *Jan 5, 2016May 5, 2016Taiwan Semiconductor Manufacturing Company Ltd.Semiconductor structure and method for manufacturing the same
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Classifications
U.S. Classification257/758, 257/E21.588, 438/622, 257/E21.576, 257/E23.145, 438/639, 257/E21.583, 257/762
International ClassificationH01L23/522, H01L21/768, H01L21/3205, H01L23/52, H01L23/532
Cooperative ClassificationH01L21/76882, H01L23/5226, H01L21/76835, H01L2924/0002, H01L23/53238, H01L21/76832, H01L21/76834, H01L21/7684
European ClassificationH01L21/768B12, H01L21/768B10M, H01L21/768B10S, H01L23/532M1C4, H01L21/768C4E, H01L21/768C2, H01L23/522E
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