Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20020030198 A1
Publication typeApplication
Application numberUS 09/923,711
Publication dateMar 14, 2002
Filing dateAug 6, 2001
Priority dateFeb 5, 1999
Also published asCN1267109A, DE19953588A1, DE19953588C2, US6320206, US6420199
Publication number09923711, 923711, US 2002/0030198 A1, US 2002/030198 A1, US 20020030198 A1, US 20020030198A1, US 2002030198 A1, US 2002030198A1, US-A1-20020030198, US-A1-2002030198, US2002/0030198A1, US2002/030198A1, US20020030198 A1, US20020030198A1, US2002030198 A1, US2002030198A1
InventorsCarrie Carter Coman, R. Scott Kern, Fred Kish, Michael Krames, Arto Nurmikko, Yoon-Kyu Song
Original AssigneeCarrie Carter Coman, R. Scott Kern, Kish Fred A., Krames Michael R., Nurmikko Arto V., Yoon-Kyu Song
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Methods for fabricating light emitting devices having aluminum gallium indium nitride structures and mirror stacks
US 20020030198 A1
Abstract
Light emitting devices having a vertical optical path, e.g. a vertical cavity surface emitting laser or a resonant cavity light emitting or detecting device, having high quality mirrors may be achieved using wafer bonding or metallic soldering techniques. The light emitting region interposes one or two reflector stacks containing dielectric distributed Bragg reflectors (DBRs). The dielectric DBRs may be deposited or attached to the light emitting device. A host substrate of GaP, GaAs, InP, or Si is attached to one of the dielectric DBRs. Electrical contacts are added to the light emitting device.
Images(10)
Previous page
Next page
Claims(23)
1. A device comprising:
a substrate;
an AlxGayInzN structure including a n-type layer, a p-type layer, and an active layer, positioned proximate to the substrate;
a first mirror stack, interposing the substrate and a bottom side of the AlxGayInzN structure;
a wafer bonded interface, interposing the first mirror stack and a selected one of the substrate and AlxGayInzN structure, having a bonding temperature; and
a p and an n contact, the p contact electrically connected to the p-type layer, the n contact electrically connected to the n-type layer.
2. A device, as defined in claim 1, further comprising:
at least one intermediate bonding layer, adjacent the wafer bonded interface; and
one of the intermediate bonding layer and the substrate is selected to be compliant.
3. A device, as defined in claim 2, wherein the AlxGayInzN device is a vertical cavity optoelectronic structure.
4. A device, as defined in claim 3, wherein the AlxGayInzN device further including a current constriction layer within the p-type layer.
5. A device, as defined in claim 2, wherein the substrate is compliant and is selected from a group that includes gallium phosphide (GaP), gallium arsenide (GaAs), indium phosphide (InP), and silicon (Si).
6. A device, as defined in claim 2, wherein the intermediate bonding layer is compliant and selected from a group that includes dielectrics and alloys containing halides, ZnO, indium, tin, chrome (Cr), gold, nickel, and copper, and II-VI materials.
7. A device, as defined in claim 2, further comprising a second mirror stack positioned adjacent a top side of the AlxGayInzN structure.
8. A device, as defined in claim 7, wherein at least one of the first and second mirror stacks is selected from a group that includes dielectric distributed Bragg reflectors and composite distributed Bragg reflectors.
9. A device, as defined in claim 1, further comprising a second mirror stack positioned adjacent the AlxGayInzN structure.
10. A device, as defined in claim 9, wherein at least one of the first and second mirror stacks is selected from a group that includes dielectric distributed Bragg reflectors and composite distributed Bragg reflectors.
11. A device, as defined in claim 1, wherein the AlxGayInzN device further including a current constriction layer within the p-type layer.
12. A device, as defined in claim 1, wherein the substrate is compliant and is selected from a group that includes gallium phosphide (GaP), gallium arsenide (GaAs), indium phosphide (InP), and silicon (Si).
13. A device, as defined in claim 1, wherein the AlxGayInzN device is a vertical cavity optoelectronic structure.
14. A method for fabricating a AlxGayInzN structure, comprising the steps of:
attaching a host substrate to a first mirror stack;
fabricating a AlxGayInzN structure on a sacrificial growth substrate;
creating a wafer bond interface;
removing the sacrificial growth substrate; and
depositing electrical contacts to the AlxGayInzN structure.
15. A method for fabricating an AlxGayInzN structure, as defined in claim 14, wherein the step for removing the sacrificial growth substrate comprises the step of laser melting.
16. A method for fabricating an AlxGayInzN structure, as defined in claim 14, further comprising the step of attaching an intermediate bonding layer at the wafer bond interface.
17. A method for fabricating an AlxGayInzN structure, as defined in claim 16, wherein one of the host substrate and the intermediate bonding layer is selected to be compliant.
18. A method for fabricating a AlxGayInzN structure, as defined in claim 14, further comprising the step of attaching a second mirror stack on top of the AlxGayInzN structure.
19. A method for fabricating a AlxGayInzN structure comprising the steps of:
fabricating a AlxGayInzN structure to a sacrificial growth substrate;
attaching a first mirror stack on top of a AlxGayInzN structure;
wafer bonding a host substrate to the first mirror stack to create a wafer bond interface;
removing the sacrificial growth substrate; and
depositing electrical contacts to the AlxGayInzN structure.
20. A method for fabricating an AlxGayInzN structure, as defined in claim 19, wherein the step for removing the sacrificial growth substrate comprises the step of laser melting.
21. A method for fabricating an AlxGayInzN structure, as defined in claim 19, further comprising the step of attaching an intermediate bonding layer at the wafer bond interface.
22. A method for fabricating an AlxGayInzN structure, as defined in claim 19, wherein one of the host substrate and the intermediate bonding layer is selected to be compliant.
23. A method for fabricating a AlxGayInzN structure, as defined in claim 19, further comprising the step of attaching a second mirror stack on top of the AlxGayInzN structure.
Description
    STATEMENT AS TO RIGHTS UNDER FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT
  • [0001] This invention was made with government support under Agreement Number MDA972-96-3-0014 awarded by the Defense Advanced Research Projects Agency (DARPA). The Federal Government has certain rights to this invention.
  • FIELD OF INVENTION
  • [0002]
    The invention is directed towards the field of light emission particularly towards providing high quality reflective surfaces to both sides of an AlxGayInzN device,
  • BACKGROUND
  • [0003]
    A vertical cavity optoelectronic structure consists of an active region that is formed by light emitting layer interposing confining layers that may be doped, un-doped, or contain a p-n junction. The structure also contains at least one reflective mirror that forms a Fabry-Perot cavity in the direction normal to the light emitting layers. Fabricating a vertical cavity optoelectronic structure in the GaN/AlxGayInzN/AlxGa1−xN (where x+y+z=1 in AlxGayInzN and where x≦1 in AlxGa1−xN) material systems poses challenges that set it apart from other III-V material systems. It is difficult to grow AlxGayInzN structures with high optical quality. Current spreading is a major concern for AlxGayInzN devices. Lateral current spreading in the p-type material is ˜30 times less than that in the n-type material. Furthermore, the low thermal conductivity of many of the substrates adds complexity to the device design, since the devices should be mounted junction down for optimal heat sinking.
  • [0004]
    One vertical cavity optoelectronic structure, e.g. a vertical cavity surface emitting laser (VCSEL), requires high quality mirrors, e.g. 99.5% reflectivity. One method to achieve high quality mirrors is through semiconductor growth techniques. To reach the high reflectivity required of distributed Bragg reflectors (DBRs) suitable for VCSELs (>99%), there are serious material issues for the growth of semiconductor AlxGayInzN DBRs, including cracking and electrical conductivity. These mirrors require many periods/layers of alternating indium aluminum gallium nitride compositions (AlxGayInzN/ Alx′Gay′Inz′N). Dielectric DBRs (D-DBR), in contrast to semiconductor DBRs, are relatively straightforward to make with reflectivities in excess of 99% in the spectral range spanned by the AlxGayInzN system. These mirrors are typically deposited by evaporation or sputter techniques, but MBE (molecular beam epitaxial) and MOCVD (metal-organic chemical vapor deposition) can also be employed. However, only one side of the active region can be accessed for D-DBR deposition unless the growth substrate is removed. Producing an AlxGayInzN vertical cavity optoelectronic structure would be significantly easier if it was possible to bond and/or deposit D-DBRs on both sides of a AlxGayInzN active region.
  • [0005]
    Wafer bonding can be divided into two basic categories: direct wafer bonding, and metallic wafer bonding. In direct wafer bonding, the two wafers are fuised together via mass transport at the bonding interface. Direct wafer bonding can be performed between any combination of semiconductor, oxide, and dielectric materials. It is usually done at high temperature (>400 C.) and under uniaxial pressure. One suitable direct wafer bonding technique is described by Kish, et al., in U.S. Pat. No. 5,502,316. In metallic wafer bonding, a metallic layer is deposited between the two bonding substrates to cause them to adhere. One example of metallic bonding, disclosed by Yablonovitch, et al. in Applied Physics Letters, vol. 56, pp. 2419-2421, 1990, is flip-chip bonding, a technique used in the micro- and optoelectronics industry to attach a device upside down onto a substrate. Since flip-chip bonding is used to improve the heat sinking of a device, removal of the substrate depends upon the device structure and conventionally the only requirements of the metallic bonding layer are that it be electrically conductive and mechanically robust.
  • [0006]
    In “Low threshold, wafer fused long wavelength vertical cavity lasers”, Applied Physics Letters, Vol. 64, No. 12, 1994, pp 1463-1465, Dudley, et al. taught direct wafer bonding of AlAs/GaAs semiconductor DBRs to one side of a vertical cavity structure while in “Room-Temperature Continuous-Wave Operation of 1.54-μm Vertical-Cavity Lasers,” IEEE Photonics Technology Letters, Vol. 7, No. 11, November 1995, Babic, et al. taught direct wafer bonded semiconductor DBRs to both sides of an InGaAsP VCSEL to use the large refractive index variations between AlAs/GaAs. As will be described, wafer bonding D-DBRs to AlxGayInzN is significantly more complicated than semiconductor to semiconductor wafer bonding, and was not known previously in the art.
  • [0007]
    In “Dielectrically-Bonded Long Wavelength Vertical Cavity Laser on GaAs Substrates Using Strain-Compensated Multiple Quantum Wells,” IEEE Photonics Technology Letters, Vol. 5, No. 12, December 1994, Chua et al. disclosed AlAs/GaAs semiconductor DBRs attached to an InGaAsP laser by means of a spin-on glass layer. Spin-on glass is not a suitable material for bonding in a VCSEL between the active layers and the DBR because it is difficult to control the precise thickness of spin on glass, and hence the critical layer control needed for a VCSEL cavity is lost. Furthermore, the properties of the glass may be inhomogeneous, causing scattering and other losses in the cavity.
  • [0008]
    Optical mirror growth of AlxGa1−xN/GaN pairs of semiconductor DBR mirrors with reflectivities adequate for VCSELs, e.g. >99%, is difficult. Referring to FIG. 1, theoretical calculations of reflectivity suggest that to achieve the required high reflectivity, a high index contrast is required that can only be provided by increasing the Al composition of the low-index AlxGa1−xN layer and/or by including more layer periods (material properties taken from Ambacher et al., MRS Internet Journal of Nitride Semiconductor Research, 2(22) 1997). Either of these approaches introduces serious challenges. If current will be conducted through the DBR layers, it is important that the DBRs be conductive. To be sufficiently conductive, the AlxGa1−xN layer must be adequately doped. Electrical conductivity is insufficient unless the Al composition is reduced to below approximately 50% for Si (n-type) doping and to below approximately 20% for Mg (p-type) doping. However, as shown in FIG. 1, the number of layer periods needed to achieve sufficient reflectivity using lower Al composition layers requires a large total thickness of AlxGa1−xN material, increasing the risk of epitaxial layer cracking (due to the relatively large lattice mismatch between AlN and GaN) and reducing compositional control. Indeed, the AlxGa1−xN/GaN stack of FIG. 1 is already ˜2.5 μm thick and is far from sufficiently reflective for a VCSEL. Thus, a high reflectivity DBR based on this layer pair requires a total thickness significantly greater than 2.5 μm and would be difficult to grow reliably given the mismatch between AlN and GaN growth conditions and material properties. Even though the cracking is not as great of an issue if the layers are un-doped, compositional control and the AlN/GaN growth temperatures still pose great challenges to growing high reflectivity DBRs. Hence, even in applications where the DBRs do not have to conduct current, semiconductor mirror stacks with reflectivities >99% in the AlxGayInzN material system have not been demonstrated. For this reason, dielectric-based DBR mirrors are preferred.
  • SUMMARY
  • [0009]
    At least one mirror stack, e.g. a dielectric distributed Bragg reflector (D-DBR) or composite D-DBR/semiconductor DBR interposes a AlxGayInzN active region and a host substrate. A wafer bond interface is positioned somewhere between the host substrate and the active region. An optional intermediate bonding layer is adjacent the wafer bond interface to accoimnodate strain and thermal coefficient mismatch at the wafer bond interface. An optional mirror stack is positioned adjacent the AlxGayInzN active region. Either the host substrate or intermediate bonding layer is selected for compliancy.
  • [0010]
    One embodiment of the aforementioned invention consists of a device having the wafer bond interface positioned adjacent the AlxGayInzN active region, the AlxGayInzN active region is fabricated on a sacrificial substrate, e.g. Al2O3. The mirror stack attached to a host substrate is direct wafer bonded to the AlxGayInzN active region. Next, the sacrificial substrate is removed. The optional mirror stack is attached to the top of the AlxGayInzN active region. Techniques for attaching include bonding, depositing, and growing. Electrical contacts are added to the n-type and p-type layers.
  • [0011]
    For an alternate embodiment having the wafer bond interface positioned adjacent the host substrate, the mirror stack is attached on top of the AlxGayInzN active region. If direct wafer bonding is employed, a host substrate, selected to have the proper mechanical properties, is wafer bonded to the mirror stack. Alternatively, metallic bonding may be used to bond the host substrate to the mirror stack. The sacrificial substrate is removed. An optional mirror stack is attached on top of the AlxGayInzN active region. Electrical contacts are added to the n-type and p-type layers. Selection of the host substrate in cases of direct wafer bonding to obtain the desired properties is a critical teaching. Additional embodiments include positioning the wafer bond interface within the DBR.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0012]
    [0012]FIG. 1 illustrates the theoretical reflectivity vs. wavelength for AlN/GaN and Al0.30Ga0.70N/GaN DBRs.
  • [0013]
    FIGS. 2A-BB illustrates preferred embodiments of the present invention.
  • [0014]
    FIGS. 3A-F pictorially depict the flow chart corresponding to the present invention.
  • [0015]
    FIGS. 4A-F pictorially depict an alternate flow chart corresponding to the present invention.
  • [0016]
    [0016]FIG. 5 shows a scanning electron microscope (SEM) cross sectional images of the direct wafer bonded interface between a D-DBR deposited on a GaN/Al2O3 structure and a GaP host substrate.
  • [0017]
    [0017]FIG. 6 shows a SEM cross section of an active region with a deposited D-DBR which was metallic bonded to a host substrate. The substrate has been removed and a second D-DBR deposited on the side of the AlxGayInzN active region opposite the first D-DBR.
  • [0018]
    [0018]FIG. 7 shows the optical emission spectrum from 400-500 nm from the device in described in FIG. 6. The modal peaks describe a vertical cavity structure.
  • DETAILED DESCRIPTION OF THE DRAWINGS
  • [0019]
    Dielectric distributed Bragg reflectors (D-DBR) consist of stacked pairs of low loss dielectrics where one of the pair materials has a low index of refraction and one has a high index of refraction. Some possible dielectric DBR mirrors are based on paired layers of silicon dioxide (SiO2) with titanium oxide (TiO2), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), or hafnium oxide (HfO2) can achieve the high reflectivities required for a blue vertical cavity surface emitting laser (VCSEL) e.g. >99.5%, or resonant cavity light emitting device (RCLED), e.g. ˜60% or higher. The SiO2/HfO2 stacked pairs are of special interest since they can be used to produce mirror stacks with reflectivities in excess of 99% in the wavelength range of 350-500 nm. D-DBRs made with alternating layers of SiO2 and HfO2 have been shown to be mechanically stable up to 1050 C., lending flexibility to subsequent processing.
  • [0020]
    A preferred embodiment is shown in FIG. 2. In FIG. 2, a first mirror stack 14 e.g. a DBR of high reflectivity, is attached to a suitable substrate. The mirror stack 14 can consist of one or more of the following materials: dielectric, semiconductor and metal. The first mirror stack 14 is wafer-bonded to a top p-layer 18 b in an AlxGayInzN active region 18 grown on a sacrificial substrate. The AlxGayInzN vertical cavity optoelectronic structure 18 has been designed for high gain at the desired wavelength. The wafer bonded interface 16 must be of excellent optical quality with very low scattering. The wafer bonded interface 16 may include an optional intermediate bonding layer (not shown). An optional second mirror stack 20, e.g. a D-DBR (shown in FIG. 2), is attached to the AlxGayInzN vertical cavity optoelectronic structure 18 on a side opposing the first mirror stack 14. The optional second mirror stack 20 and n- and p-type 18 a, 18 b layers of the AlxGayInzN active region 18 may be patterned and etched to provide areas for ohmic contacts. For a VCSEL, the mirror must have very high reflectivity >99%. For an RCLED, the reflectivity requirement of the mirror(s) is relaxed (>60%).
  • [0021]
    An alternate approach is for the mirror stack 14 to be attached to the AlxGayInzN active region. The wafer bond interface 16 is then between the mirror stack 14 and the host substrate 12. This structure may also have an optional second mirror stack 20. Yet another approach, to be used in conjunction with either of the first two, is to have a direct wafer bond in the middle of one or both of the mirror stacks. Several possible locations of a wafer bonded interface 16 are shown in FIG. 2.
  • [0022]
    Current constriction may be achieved in either the n-type or p-type active region material by inserting an AlxGayInzN layer that may be etched and/or oxidized to improve current and optical confinement and thus reduce lasing threshold or improve device efficiency. Incorporation of such a layer is important when a D-DBR and/or un-doped semiconductor DBR is used since no current is conducted through them. The cavity may be a single or multiple-wavelength cavity depending on the required thickness of the contacting layers to obtain a suitably low forward voltage. Many variations on the structures described above are possible. A similar structure can also be produced with the p- and n-type materials switched.
  • [0023]
    FIGS. 3A-F pictorially depict a flow chart corresponding to an embodiment of the present invention. In FIG. 3A, a AlxGayInzN active region is fabricated on a sacrificial substrate, e.g. Al2O3. In FIG. 3B, a first mirror stack is attached to a host substrate. Techniques for attaching include bonding, depositing, and growing. In FIG. 3C, the first mirror stack is attached via wafer bonding to the AlxGayInzN active region. For a VCSEL, direct wafer bonding should be used since it is critical to have low optical losses. In FIG. 3D, the sacrificial substrate is removed. In FIG. 3E, the optional second mirror stack is attached to the top of the AlxGayInzN active region. In FIG. 3F, electrical contacts are added to the optional second mirror stack or AlxGayInzN active region. Patterning to define the device area and to expose the contact layers can also be performed in the process flow.
  • [0024]
    FIGS. 4A-F pictorially depict an alternate process flowchart. In FIG. 4A, a AlxGayInzN active region is grown over on a sacrificial substrate. In FIG. 4B, the first mirror stack is attached to the AlxGayInzN active region. In FIG. 4C, a host substrate is attached via direct wafer bonding or metallic bonding to the first mirror stack. Since the wafer bond is outside of the optical cavity, losses due to the wafer bond are less critical. In FIG. 4D, the sacrificial substrate is removed. In FIG. 4E, the optional second mirror stack is attached to the AlxGayInzN active region. In FIG. 4F, electrical contacts are added to the optional second mirror stack or AlxGayInzN active region. Patterning to define the device area and to expose the contact layers can also be performed in the process flow.
  • [0025]
    The choice of host substrate for direct wafer bonding is critical and is effected by several properties: mass transport, compliancy, and stress/strain relief. The host substrate can be selected from a group that includes gallium phosphide (GaP), gallium arsenide (GaAs), indium phosphide (InP), or silicon (Si). For Si, the preferred thickness of the substrate is between 1000Å and 50 μm.
  • [0026]
    Mass transport plays an important role in direct wafer bonding. In standard III-V to III-V direct wafer bonding, or III-V to dielectric bonding, at least one surface exhibits significant mass transport at temperatures sufficiently low to preserve the quality of the layers. In contrast, AlxGayInzN and most dielectric materials do not exhibit significant mass transport at temperatures consistent with maintaining integrity of the high-In containing AlxGayInzN active layers (<1000 C.). Lack of mass transport in one or both of the bonding materials impedes wafer adhesion. A model for this is that when both materials exhibit significant mass transport at the bonding temperature, the bonds of both materials can rearrange into the strongest bond across the interface. When only one material exhibits significant mass transport, the bonds of only this one material can align with the surface bonds of the other material. It is difficult in this situation to form a wafer bond of high mechanical strength.
  • [0027]
    Compliancy is the ability of the material to change shape on an atomic or macroscopic scale to accommodate strains and stresses. For the purposes of this invention, compliancy is defined to be accomplished by materials that have a melting point less than the bonding temperature, or when materials have a ductile/brittle transition below the bonding temperature, or when the substrates are thinner than ˜50 μm.
  • [0028]
    Standard III-V wafer bonding for substrates of GaP, GaAs, and InP is generally performed at temperatures of 400-1000 C. where both substrates are compliant. Compliancy of at least one of the bonding materials is essential to wafer bonding since the materials have inherent surface roughness and/or lack of planarity on either and microscopic or macroscopic scale. At a temperature of 1000 C. a AlxGayInzN structure amealed in an N2 ambient for 20 minutes results in a reduction of PL intensity of approximately 20%. Thus it is desirable to keep the bonding temperature below 1000 C. GaN-based materials grown on Al2O3 substrates are not compliant at bonding temperatures below 1000 C. Dielectric materials that are used to make high reflectivity D-DBRs for wide band-gap semiconductors are typically not compliant below 1000 C. Hence, it is important that the bonding/support substrate and/or intermediate bonding be compliant at those temperatures.
  • [0029]
    Melting point is one property that determines the compliancy of materials. For example, for the following materials, GaAs (Tm=1510K), GaP (Tm=1750K), and InP (Tm=1330K), it can be seen that the relative order of compliancy is InP, GaAs, GaP, with InP being the most compliant. Materials generally undergo a ductile/brittle transition below the melting point. The compliancy of these materials at high temperatures has to be balanced with desorption of one of the elements. Even though InP is compliant at 1000 C., the material would be severely decomposed at that temperature because of the desorption of phosphorus. Bonding with such materials should be limited to temperatures less than approximately two times the desorption temperature at the ambient pressure during bonding. Thus, the selection of materials must be compatible both with the required compliancy and the bonding temperature.
  • [0030]
    Very thin substrates can also be compliant. Thin silicon, e.g. <50 μm, is compliant because, even at a high radius of curvature, the stresses are small if the substrate is thin. This technique works well for materials having a high fracture hardness, e.g. silicon (11270 N/mm2) or AlxGayInzN. However, materials that have a low fracture hardness, e.g. GaAs (2500 N/mm2) can easily fracture upon handling. For silicon having a thickness >50 μm, even a small radius of curvature causes high stresses in the material, causing the material to fracture. The same applies to other materials that are potential substrate candidates.
  • [0031]
    Stress and strain relief is exacerbated by the high mismatch strain in GaN grown on Al2O3 as well as the coefficient of thermal expansion (CTE) mismatch between AlxGayInzN and most other suitable support substrate materials. In contrast to other semiconductor materials that are wafer bonded, the CTE mismatch between AlxGayInzN and other semiconductor materials is greater; the stresses are compounded by the different CTE mismatch along the a and c planes of the wurzite material. The stresses in GaN (CTE=5.59, a-plane/3.1710−6, c-plane/ C.) wafer bonded to a different substrate (GaAs CTE=5.8, GaP CTE=6.8, InP=4.510−6/C) necessitates local stress relief since the CTE mismatch of the host substrate should closely match those of both GaN planes. This stress can be accommodated in a compliant material, in an intermediate bonding layer that is soft or a liquid at the bonding interface at the bonding temperature, or by providing local strain relief, e.g. patterning at least one of the bonded interfaces. The intermediate bonding layer is selected from a group that includes dielectrics and alloys containing halides (e.g. CaF2), ZnO, indium (In), tin (Sn), chrome (Cr), gold (Au), nickel (Ni), copper (Cu), and II-VI materials.
  • [0032]
    Current spreading is another major concern for GaN-based devices. Lateral current spreading in the p-type material is ˜30 less than that in the n-type material. While fabricating high reflectivity mirrors on both sides of the active layer is necessary for a good cavity, the problem of lateral p-layer current spreading is exacerbated because of the insulating nature of the D-DBRs. One way to improve the current spreading in the p-layer is to make a composite DBR of conductive transparent semiconductor and dielectric stacks. The semiconductor part of the stack improves current spreading by adding thickness to the p-layers while the dielectric stack improves the low semiconductor reflectivity to bring the total mirror reflectivity above 99%. This same procedure could be applied to the n-type mirror, though it is less crucial because of the higher conductivity of the n-type layers.
  • [0033]
    The addition of current constriction layers would further improve current spreading by directing the current only into the cavity, and may be necessary for a VCSEL. This can be applied to the vertical cavity optoelectronic structure with or without a composite semiconductor/dielectric DBR, and may be incorporated into the semiconductor part of a composite mirror. Although the current constriction layers may be included in both the p- and n-layers of the confining layers, it is most effective in the p-confining layers because of the lower conductivity.
  • [0034]
    The support substrate is necessary if a D-DBR is to be attached to both sides of the active region, since the original host substrate must be removed. There are several methods for removing the sapphire substrate, which is typically employed as a growth substrate. The methods outlined below are only a subset of the techniques that could be used to remove the growth substrate, which can also be a material other than sapphire.
  • [0035]
    In laser melting, a technique as disclosed by Wong, et al, and Kelley, et al., having a laser with a wavelength for which the sapphire substrate is transparent but the semiconductor layer adjacent the substrate is not, illuminates the back (sapphire side) of the structure. The laser energy cannot penetrate the adjacent semiconductor layer. If the laser energy is sufficient, the semiconductor layer adjacent the sapphire substrate heats to the point that it decomposes. For the case where GaN is the layer adjacent the sapphire substrate, the layer at the interface decomposes into Ga and N, leaving Ga behind at the interface. The Ga metal is then melted and the sapphire substrate is removed from the rest of the layer structure. The decomposition of the layer adjacent the sapphire substrate depends on laser energy, wavelength, material decomposition temperature, and the absorption of the material. The sapphire substrate may be removed by this technique to allow a D-DBR to be attached to the other side of the active region. However, it is critical that the VCSEL interfaces be minimally lossy (<0.5%) and very smooth to maximize cavity resonance characteristics. This laser melting technique has many design variables that may make the laser interface lack the flatness necessary for a VCSEL. Additionally, VCSELs have very tight thickness constraints. There are several ways that laser melting can be used to alleviate both of these problems.
  • [0036]
    The layer adjacent the sacrificial growth substrate is defined to be a sacrificial layer if the thickness of the layer is such that it will be completely decomposed by the laser. Published results in the literature (Wong, et al.) indicate that a layer thickness that will be completely decomposed is approximately sooA, but this value will be dependent on the laser energy, the laser wavelength, and material decomposition temperature and the absorption of the layer adjacent the substrate. The layer adjacent the sacrificial layer (opposite the substrate), the stopper layer, is chosen to have a higher decomposition temperature or lower absorption at the laser wavelength than sacrificial layer. The stopper layer, because it has a higher decomposition temperature or low absorption, will not be significantly affected by the laser energy. In this structure, the sacrificial layer is decomposed by the laser, leaving an abrupt interface at the stopper layer which has a higher decomposition temperature or lower absorption. That stopper layer can also then be subsequently etched, oxidized and etched, or decomposed using a laser with different energy and wavelength.
  • [0037]
    The preferred layer combinations are GaN/AlxGa1−xN, InGaN/ AlxGa1−xN, and InGaN/GaN. In the case of GaN/ AlxGa1−xN combination, the GaN sacrificial layer will decompose with the laser but the AlxGa1−xN stopper layer will be unaffected. The AlxGa1−xN can then be etched away using selective wet chemical etching to stop on a smooth AlxGayInzN interface. Alternatively, if the GaN layer described above is not completely decomposed, the remaining GaN can be etched away. Since a thick buffer layer is needed at the beginning of GaN growth and the VCSEL layer interfaces need to be of controlled thickness and very smooth, this technique can be especially valuable.
  • [0038]
    The thickness of a particular layer or cavity can be tailored by using one or more sacrificial layers and stopper layers. By laser melting and selective wet chemical etching, layer pairs can be decomposed and etched in sequence until the desire thickness is reached. A preferred layer combination is GaN/ AlxGa1−xN where the GaN is the sacrificial layer and the AlxGa1−xN stopper layer can be selectively wet chemical etched.
  • [0039]
    There are other alternative methods of removing the growth substrate. One method is to use AlN which can be selectively etched using wet chemical etching. AlN may be used as a sacrificial layer where the AlxGayInzN layers can be removed from the host substrate by using AlN selective etching to undercut the structure. Alternatively, the AlN layers can be oxidized using a wet oxidation process at elevated temperatures. The AlN-oxide can then be etched away using an etchant, e.g. HF. In another approach, the substrate may be exfoliated, e.g. implanted with a light ion into the material. This creates defects at a certain depth. When the substrate is heated, the material selectively cleaves through the dislocations and the substrate is separated from the active layers. Undercutting a ZnO or other dielectric buffer layer via chemical etchants can also be used to remove the substrate from the AlxGayInzN layers. This technique can be applied to 2-D or 3-D growth techniques (e.g. SiO2 or other dielectric used in ELOG) where the AlxGayInzN layer is continuous across the substrate or in patterned areas only.
  • [0040]
    Dielectric DBRs have been deposited on AlxGayInzN active regions grown on sapphire substrates. The DBR/ AlxGayInzN active region structure was then wafer bonded to a host substrate. In case 1, the DBR/ AlxGayInzN active region structure was direct wafer bonded to a GaP host substrate (see FIG. 3). In case 2, the DBR/ AlxGayInzN active region structure was wafer bonded to a GaP host substrate via an intermediate CaF2 layer (FIG. 3, where the intermediate layer is not shown). In case 3, the D-DBR was deposited on a host substrate (GaP) and direct wafer bonded to a AlxGayInzN active region (FIG. 4). For cases 1 and 3, the bonded area was much smaller than case 2 since no intermediate layer was used. FIG. 5 shows scanning electron microscope (SEM) cross sectional images of the bonded interface for a case 1 structure. The interface is smooth and there are no voids visible at this magnification. In case 4, the DBR/AlxGayInzN active region structure was bonded to a host substrate via a metallic intermediate layer consisting of a CrAuNiCu alloy. FIG. 6 shows a SEM cross section of case 4, the sapphire substrate as been removed and a second D-DBR deposited on the side of the AlxGayInzN active region opposite the first D-DBR. For all the devices, DDBR stacks were SiO2/HfO2, and the sapphire substrate was removed using the laser melting technique. FIG. 7 shows the optical emission spectrum from 400-500 nm from the device in described in FIG. 6. The modal peaks are characteristic of a vertical cavity structure.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6936486Nov 19, 2002Aug 30, 2005Jdsu Uniphase CorporationLow voltage multi-junction vertical cavity surface emitting laser
US7151284 *May 11, 2004Dec 19, 2006Shangjr GwoStructures for light emitting devices with integrated multilayer mirrors
US7638810 *Sep 9, 2005Dec 29, 2009Avago Technologies Ecbu Ip (Singapore) Pte. Ltd.GaN laser with refractory metal ELOG masks for intracavity contact
US7745931 *May 28, 2004Jun 29, 2010Sanyo Electric Co., Ltd.Semiconductor device and manufacturing method thereof
US7808011 *Mar 19, 2004Oct 5, 2010Koninklijke Philips Electronics N.V.Semiconductor light emitting devices including in-plane light emitting layers
US7910945Aug 23, 2007Mar 22, 2011Cree, Inc.Nickel tin bonding system with barrier layer for semiconductor wafers and devices
US7915624 *Aug 3, 2007Mar 29, 2011Lightwave Photonics, Inc.III-nitride light-emitting devices with one or more resonance reflectors and reflective engineered growth templates for such devices, and methods
US7986722Oct 21, 2009Jul 26, 2011Nichia CorporationNitride semiconductor light emitting element
US8101496 *May 12, 2010Jan 24, 2012Semiconductor Components Industries, LlcMethod of manufacturing ball grid array type semiconductor device
US8237761 *Oct 25, 2007Aug 7, 2012Canon Kabushiki KaishaSemiconductor member, semiconductor article manufacturing method, and LED array using the manufacturing method
US8247836Feb 25, 2011Aug 21, 2012Cree, Inc.Nickel tin bonding system with barrier layer for semiconductor wafers and devices
US8343782Sep 29, 2010Jan 1, 2013SoitecSemiconductor device having an InGaN layer
US8643195Jun 30, 2006Feb 4, 2014Cree, Inc.Nickel tin bonding system for semiconductor wafers and devices
US8670015Jul 16, 2012Mar 11, 2014Canon Kabushiki KaishaSemiconductor member, semiconductor article manufacturing method, and LED array using the manufacturing method
US8711893Jan 28, 2009Apr 29, 2014Osram Opto Semiconductors GmbhOptoelectronic component and method for producing an optoelectronic component
US8735197 *Oct 29, 2012May 27, 2014Epistar CorporationWafer-scaled light-emitting structure
US8735219Aug 30, 2012May 27, 2014Ziptronix, Inc.Heterogeneous annealing method and device
US9052535 *Oct 16, 2013Jun 9, 2015Sandia CorporationElectro-refractive photonic device
US9181633 *Oct 15, 2008Nov 10, 2015Freiberger Compound Materials GmbhDevice and process for heating III-V wafers, and annealed III-V semiconductor single crystal wafer
US20040095978 *Nov 19, 2002May 20, 2004Julian ChengLow voltage multi-junction vertical cavity surface emitting laser
US20040096996 *May 2, 2003May 20, 2004Julian ChengLow voltage multi-junction vertical cavity surface emitting laser
US20050003649 *May 28, 2004Jan 6, 2005Sanyo Electric Co., Ltd.Semiconductor device and manufacturing method thereof
US20050031005 *Sep 13, 2004Feb 10, 2005Jds Uniphase CorporationLow voltage multi-junction vertical cavity surface emitting laser
US20050100069 *May 11, 2004May 12, 2005Shangjr GwoStructures for light emitting devices with integrated multilayer mirrors
US20050205884 *Mar 19, 2004Sep 22, 2005Lumileds Lighting U.S., LlcSemiconductor light emitting devices including in-plane light emitting layers
US20060054919 *Aug 26, 2005Mar 16, 2006Kyocera CorporationLight-emitting element, method for manufacturing the same and lighting equipment using the same
US20060081858 *Oct 14, 2004Apr 20, 2006Chung-Hsiang LinLight emitting device with omnidirectional reflectors
US20070057270 *Sep 9, 2005Mar 15, 2007Bour David PGaN laser with refractory metal ELOG masks for intracavity contact
US20080003777 *Jun 30, 2006Jan 3, 2008Slater David BNickel Tin Bonding System for Semiconductor Wafers and Devices
US20080029773 *Aug 3, 2007Feb 7, 2008Jorgenson Robbie JIII-nitride light-emitting devices with one or more resonance reflectors and reflective engineered growth templates for such devices, and methods
US20080210971 *Aug 23, 2007Sep 4, 2008Matthew DonofrioNickel tin bonding system with barrier layer for semiconductor wafers and devices
US20090104423 *Oct 15, 2008Apr 23, 2009Freiberger Compound Materials GmbhDevice and process for heating iii-v wafers, and annealed iii-v semiconductor single crystal wafer
US20100026779 *Oct 25, 2007Feb 4, 2010Canon Kabushiki KaishaSemiconductor member, semiconductor article manufacturing method, and led array using the manufacturing method
US20100098127 *Oct 21, 2009Apr 22, 2010Nichia CorporationMethod of manufacturing nitride semiconductor light emitting element and nitride semiconductor light emitting element
US20100221892 *Sep 2, 2010Sanyo Electric Co., Ltd.Semiconductor device and manufacturing method thereof
US20100226404 *Sep 9, 2010Koninklijke Philips Electronics N.V.Semiconductor light emitting devices including in-plane light emitting layers
US20110051771 *Jan 28, 2009Mar 3, 2011Osram Opto Semiconductors GmbhOptoelectronic Component and Method for Producing an Optoelectronic Component
US20110134954 *Jun 9, 2011Letertre Fabrice MSEMICONDUCTOR DEVICE HAVING AN InGaN LAYER
US20110180839 *Jul 28, 2011Matthew DonofrioNickel Tin Bonding System with Barrier Layer for Semiconductor Wafers and Devices
WO2004047242A1 *Nov 18, 2003Jun 3, 2004Julian ChengLow voltage multi-junction vertical cavity surface emitting laser
WO2011116917A1 *Mar 21, 2011Sep 29, 2011Eth ZurichSurface emitting semiconductor laser and method of manufacture thereof
WO2014036407A1 *Aug 30, 2013Mar 6, 2014Enquist Paul MHeterogeneous annealing method and device
Classifications
U.S. Classification257/103, 257/E33.069, 438/22, 257/98
International ClassificationH01S5/343, H01S5/323, H01S5/183, H01L33/00, H01L33/10, H01L33/46
Cooperative ClassificationY10S438/977, B82Y20/00, H01L33/007, H01S5/1838, H01L33/0079, H01S5/34333, H01S5/0217, H01S5/18361, H01L33/465, H01S5/18341, H01L33/0075, H01S5/0216, H01L33/105
European ClassificationB82Y20/00, H01L33/00G3C, H01L33/00G3B2, H01L33/10C, H01L33/00G3D
Legal Events
DateCodeEventDescription
Jan 17, 2006FPAYFee payment
Year of fee payment: 4
Jan 14, 2010FPAYFee payment
Year of fee payment: 8
Jan 10, 2014FPAYFee payment
Year of fee payment: 12