|Publication number||US20020030229 A1|
|Application number||US 09/941,221|
|Publication date||Mar 14, 2002|
|Filing date||Aug 28, 2001|
|Priority date||Jan 5, 2000|
|Also published as||US6429099|
|Publication number||09941221, 941221, US 2002/0030229 A1, US 2002/030229 A1, US 20020030229 A1, US 20020030229A1, US 2002030229 A1, US 2002030229A1, US-A1-20020030229, US-A1-2002030229, US2002/0030229A1, US2002/030229A1, US20020030229 A1, US20020030229A1, US2002030229 A1, US2002030229A1|
|Inventors||Todd Christensen, John Sheets|
|Original Assignee||Christensen Todd Alan, Sheets John Edward|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (3), Classifications (31)|
|External Links: USPTO, USPTO Assignment, Espacenet|
 A related U.S. patent application Ser. No. ______, entitled “Method and Semiconductor Structure for Implementing Dual Plane Body Contacts for Silicon-on-Insulator (SOI) Transistors,” IBM Docket No. RO999-179 by Todd Alan Christensen and John Edward Sheets II which is owned by the assignee herein and which is being filed on the same day as the present patent application, and which is hereby incorporated by reference in its entirety.
 The present invention relates to a method to implement body contacts of transistors on semiconductor-on-insulator, especially silicon-on-insulator (SOI), semiconductor technology.
 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) scaling on bulk silicon has been the primary focus of the semiconductor and microelectronic industry for achieving Complementary Metal Oxide Semiconductor (CMOS) chip performance and density objectives. The shrinking of MOSFET dimensions for high density, low power and enhanced performance requires reduced power supply voltages. Because power consumption is a function of capacitance, voltage, and transition frequency, the focus has been on reducing both the capacitance and the voltage as the switching frequency increases. As a result, dielectric thickness and channel length are scaled with power supply voltage. Power supply reduction continues to be the trend for future low voltage CMOS, however, transistor performance is severely impacted by both junction capacitance and the MOSFET body effect at lower voltages. As technologies scale below 0.25 μm channel lengths, to 0.15 μm and 0.1 μm and shorter, short channel effects control, gate resistance, channel profiling and other barriers become an issue for advanced CMOS technologies. While significant success has been achieved with successive scaling of bulk CMOS technology, the manufacturing control issues and power consumption will become increasingly difficult.
 Silicon-on-insulator (SOI) technology is an enhanced silicon technology in which an insulating layer is situated above the bulk CMOS layer. SOI transistors are built in a thin layer of silicon on top of a buried insulator, typically silicon oxide or glass, with bulk silicon below the buried insulator. Using SOI technology eliminates many of the concerns and obstacles of bulk silicon CMOS at low power supply voltages. SOI has significant advantages over bulk CMOS technology and will achieve the scaling objectives of low power and high switching frequency for future technologies. SOI provides low power consumption, low leakage current, low capacitance diode structures, good subthreshold IN (current/voltage) characteristics, a low soft error rate from both alpha particles and cosmic rays, good SRAM access times, to name only some of the technology benefits offered by SOI. Because of these advantages, SOI technology is especially useful in portable and wireless applications.
 SOI technology allows for the mapping of standard advanced technologies into an SOI technology without significant modifications. SOI process techniques include epitaxial lateral overgrowth, lateral solid-phase epitaxy and full isolation by porous oxidized silicon. SOI networks can be constructed using the semiconductor process of techniques of separation by implanted oxygen and wafer-bonding and etch-back because they achieve low defect density, thin film control, good minority carrier lifetimes and good channel mobility characteristics. Structural features are defined by shallow-trench isolation. Shallow trench isolation eliminates planarity concerns and multidimensional oxidation effects, thereby allowing technology migration and scaling to sub-0.25 μm technologies.
FIGS. 1 and 2 illustrate a conventional SOI transistor. FIG. 1 illustrates a cross section through the width of a traditional SOI transistor. The SOI transistor has a polysilicon gate, a gate oxide over a thin silicon layer with isolation oxide, over a buried oxide, over the bulk silicon substrate. Performance of SOI transistors is increased due to reduced diffusion capacitance and due to floating body properties resulting in lower transistor threshold voltages. Since the voltage of the floating body can vary over time, the threshold voltage also varies. The floating body effects were considered beneficial because of the increased speed at which a transistor can switch. Performance, however, cannot be predicted using transistors in which the bodies are allowed to float. Floating body transistors, moreover, are extremely sensitive to nonperfect input voltage on the gates and to noise. Because of “history effects”, moreover, floating body transistors are difficult to match, in part because of this sensitivity described above and in part because the voltage on the floating body is dependent upon previous cycles and the time durations of the cyclic input. For instance, a high signal immediately after two or three other high signals might be output too fast in order to synchronize with other signals. Similarly, a low signal immediately after two or three high signals might be too slow.
 In situations and circuits in which the effects associated with floating bodies are undesirable, there are known structures that can be used to connect the body of the SOI transistor to a known voltage. However, the known structures add much capacitance to the device, particularly gate capacitance, thus degrading the performance of these transistors so that is worse than a traditional bulk transistor. FIG. 2 illustrates a traditional body contact of a SOI transistor. Increased polysilicon area is needed to fabricate the traditional body contact. The increased polysilicon results in a large increase in capacitance of the SOI transistor, thus degrading performance.
 In the past, electrically connecting the transistor body to a fixed voltage typically increased the size of SOI devices and as such it was considered undesirable. Other attempts have been made to allow body contact with non-uniformly doped channel regions, however, the use of non-uniformly doped channel regions may cause the devices' threshold voltage to change. Other techniques to contact the body of SOI transistors to a voltage are complex and involve multiple process steps using multiple films. These techniques, moreover, often exacerbate the problem that transistors bodies have high electrical resistance which generates heat. When switching transistors at high frequencies on the order of gigahertz, or once every tens, rather than hundreds of picoseconds, the resistance resulting from large contacts to the transistor bodies causes delay in the transitions because of the resistance-capacitive delay and it is difficult to keep the body at a fixed voltage, especially at ground voltage.
 Existing SOI transistors with body contacts require significantly more physical area than their counterpart transistors not having body contacts. Conventional body contacts involving a large “T” or “L” shaped gate where the horizontal layout segment(s) separate the active body region from the body contact region increase the total transistor physical area on the order of fifty percent. Given the same input signal on a non-body contacted transistor and depending on transistor width, the added gate area required by body contacts for SOI transistors typically doubles the total gate capacitance requiring twice the input rise time. The increased area and/or delay penalty render the body-contacted SOI transistors less desirable.
 And yet another undesirable result of traditional body contacts in a SOI transistor is a large resistance between the electrical connection between the desired power grid, typically ground for a NFET body, and the actual body itself. Because the connection is through thin lightly doped semiconductor levels, resistances on the order of tens of thousands of ohms are typical.
 There is thus a need in the semiconductor-on-insulator industry for a body contact that can operate at high frequencies but does not have high capacitance nor high resistance,
 A principal object of the present invention is to provide a method and semiconductor structure fabricated using the method for implementing body contacts for semiconductor-on-insulator transistors. Other important objects of the present invention are to provide such a method and semiconductor structure for implementing body contacts for silicon-on-insulator (SOI) transistors without substantial negative effect and that overcome many of the disadvantages of prior art arrangements.
 A method for implementing body contacts for semiconductor-on-insulator transistors is disclosed which comprises the steps of providing a bulk semiconductor substrate; implanting an insulator to the bulk semiconductor substrate to create a buried insulating layer while applying a mask to block the implantation in selected regions; the selected regions used to form body contacts for the transistors; forming holes extending into the buried insulating layer and the bulk semiconductor substrate; and filling the holes with an electrically conductive material to create stud contacts to the bulk semiconductor substrate. The steps of applying the mask to the selected regions and of implanting an insulator creates the buried insulating layer with the masked selected regions to create openings aligned with bodies of the transistors. The step of forming holes into the buried insulating layer and the bulk semiconductor substrate includes the step of etching holes into the buried insulating layer and the bulk semiconductor substrate.
 In a preferred embodiment, the semiconductor is silicon, the implanted insulator is oxygen and the buried insulating layer is a buried oxide layer, and the step of filling the etched holes with an electrically conductive material to create stud contacts to a bulk silicon substrate includes the step of filling the holes with tungsten to create stud contacts to the bulk silicon substrate. The etched holes may also be filled with copper; or aluminum; gold; or a doped semiconductor to create stud contacts to the bulk semiconductor substrate.
 The invention may also be realized by a method for implementing body contacts for silicon-on-insulator (SOI) transistors comprising the steps of providing a bulk silicon substrate; applying a mask to selected regions of the bulk silicon substrate; implanting oxygen to create a buried oxide layer above the bulk silicon substrate; the masked selected regions to create openings aligned with bodies of the transistors for body contacts of the SOI transistors; etching holes extending into the buried oxide insulator layer and the bulk silicon substrate; and filling the holes with an electrically conductive material selected from the group consisting of tungsten, copper, aluminum, gold, and doped semiconductor to create stud contacts to the bulk semiconductor substrate. The invention also extends to an integrated circuit having a silicon-on-insulator device made by the method above.
 The invention may also be considered a semiconductor structure for implementing body contacts for silicon-on-insulator (SOI) transistors comprising a bulk silicon substrate having SOI transistors formed on the bulk silicon substrate; a pattered oxygen implant layer in which the oxygen implant is blocked in selected regions; the selected regions to provide body contact for the SOI transistors; and electrically conductive contacts extending into the bulk silicon substrate. The semiconductor structure also includes connections for a selected voltage potential connected to the electrically conductive contacts extending into the bulk silicon substrate.
 The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:
FIG. 1 illustrates a conventional SOI transistor;
FIG. 2 illustrates a conventional SOI transistor with a conventional contact to the transistor body; and
FIGS. 3 through 6 are simplified diagrams of the process for implementing body contacts for semiconductor-on-insulator transistors in accordance with principles of the invention. It is suggested that FIG. 6 be printed on the cover of the patent.
 Having reference now to the drawings, in FIGS. 3 through 6, there are shown exemplary sequential steps for implementing body contacts for transistors in a semiconductor-on-insulator technology, preferably silicon-on-insulator (SOI) technology in accordance with the preferred embodiment. A contact to the body of the transistor is provided while maintaining performance advantage and without requiring any additional silicon area.
 In accordance with features of the invention, the body contact of the preferred embodiment is provided from underneath the transistor body through the buried insulating layer and the buried bulk semiconductor. By patterning the buried insulating layer, direct electrical connects from the bulk semiconductor up to the regions that will become the bodies of the transistors are provided.
 Referring now to FIG. 3, in the preferred embodiment, a blank P+/P−Epi doped silicon substrate including a bulk silicon 302 doped with P+, i.e., approximately 1020 to 1021 acceptor atoms, such as boron, and a P−Epi layer 304 of approximately 1015 to 1016 acceptors atoms per cubic centimeter can be used to create a structure of the invention. It should be understood that any semiconductor-on-insulator technology having a semiconductor insulator on the same or different semiconductor stack is possible to incorporate the body contacts of the invention herein. It will be appreciated, moreover, that if silicon technology is used, a blank N+/N−Epi doped silicon substrate can also be used to create a structure of the invention.
 Referring to FIG. 4, the insulating oxide formation is undesirable at the positions of the conductive body contacts 504 so a patterned mask is applied to define a plurality of openings or regions 504. The openings 504 become the body contacts in the bulk silicon layer 302. An appropriate insulator, such as oxygen, is implanted to create the buried insulating layer 502.
 Referring to FIG. 5, next conventional processing to build, e.g., a NFET SOI transistor is continued, including a device isolation layer 602, preferably an oxide layer, a thin gate oxide 604, a polysilicon gate 606, and a body 608. Openings 504 in the buried insulating layer are aligned with the bodies 608 of the transistors.
 Referring to FIG. 6, prior to applying a first metallization layer at the level where ground connections are shown, deep holes 702 are simultaneously etched into the bulk silicon 302 through the isolating layers 602 and the insulating layer 502. Next the holes 702 are filled with an electrically conductive material 704, such as tungsten, copper, doped silicon, gold, or aluminum, thus creating stud contacts to these layers 402 and 302 that can be connected to voltage supplies or in some cases a varying voltage. A body contact made according to principles of the invention would have a body resistance on the order of one ohm per square or less for a total resistance of approximately ten to twenty ohms or less, as opposed to the prior art of FIG. 2 which body contact would typically have a resistance of tens of thousands of ohm per square for a total resistance of hundreds of thousands of ohms. Typically the connection to the bulk silicon 302 would be tied to ground and body contacts to NFETs would utilize this connection. If the bulk silicon was N+bulk silicon, the bulk could be tied to a high voltage supply Vdd and PFETs could take advantage of the body contacts of the invention.
 While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8105924 *||Jan 21, 2010||Jan 31, 2012||International Business Machines Corporation||Deep trench based far subcollector reachthrough|
|US8680617 *||Oct 6, 2009||Mar 25, 2014||International Business Machines Corporation||Split level shallow trench isolation for area efficient body contacts in SOI MOSFETS|
|US20110079851 *||Apr 7, 2011||International Business Machines Corporation||Split level shallow trench isolation for area efficient body contacts in soi mosfets|
|U.S. Classification||257/347, 257/E29.021, 257/E21.346, 257/E21.703, 257/E21.339, 257/E21.563, 257/E21.538, 257/E27.112|
|International Classification||H01L21/74, H01L27/12, H01L21/84, H01L29/06, H01L21/762, H01L21/266, H01L21/265|
|Cooperative Classification||Y10S438/967, H01L21/266, H01L29/0653, H01L21/743, H01L21/84, H01L27/1203, H01L21/76243, H01L21/76267, H01L21/26533|
|European Classification||H01L21/762D20A, H01L21/762D2, H01L21/84, H01L21/74B, H01L29/06B3C2, H01L27/12B, H01L21/266|