US 20020033738 A1 Abstract Disclosed is a PLL circuit that makes fractional frequency division possible without causing spurious components to be produced in the output of a VCO. The PLL circuit comprises a frequency dividing circuit for frequency-dividing the output of a VCO; a phase adjusting circuit, to which are input two clocks of different phases obtained by frequency division performed by the frequency dividing circuit, for producing an output signal having a delay time defined by a time that is the result of internally dividing a timing difference between the two clocks; a charge pump for generating a voltage conforming to a phase difference output from the phase comparator circuit; and a loop filter for smoothing the voltage conforming to the phase difference and applying the voltage to the VCO, wherein the dividing value of the timing difference in the phase adjusting circuit is represented by MF/MD, and an accumulation operation is performed in units of MF every frequency-divided clock. If the cumulative result by MF is equal to or greater than MD, then a remainder obtained by dividing the cumulative result by MD is adopted as the cumulative result and the dividing ratio of the frequency dividing circuit is set to N+1. A control signal for setting the dividing ratio of the timing difference in the phase adjusting circuit is output to the phase adjusting circuit, and a clock obtained by frequency-dividing the output of the VCO in accordance with a dividing ratio N+MF/MD is input to a phase comparator.
Claims(18) 1. A PLL circuit comprising:
a phase comparator circuit which receives a reference clock from one input terminal thereof to output a phase difference; a charge pump which generates a voltage conforming to the phase difference output from said phase comparator circuit; a loop filter which performs smoothing the voltage conforming to the phase difference; a voltage-controlled oscillator which receives an output voltage of said loop filter as a control voltage to output a clock having an oscillation frequency determined by the control voltage; a frequency dividing circuit which performs integral frequency-division of an output clock output from said voltage-controlled oscillator; a phase adjusting circuit which receives two frequency-divided clocks of mutually different phases obtained by integral frequency division at said frequency dividing circuit to produce an output signal having a delay time defined by a time that is the result of dividing a timing difference between the two frequency-divided clocks in accordance with a prescribed interior division ratio, said interior division ratio being made variable; and control means which provides a signal for variably setting, every integral frequency dividing interval, the interior division ratio with which the timing difference is divided in the phase adjusting circuit; wherein a frequency-divided clock that is output from said phase adjusting circuit is fed to another input terminal of said phase comparator circuit so that a phase of the frequency-divided clock is compared with that of the reference clock. 2. The PLL circuit as defined in an integral dividing ratio of said frequency dividing circuit is set to either N or N+1; and said control means comprises an adder circuit for performing addition cumulatively in units of MF based upon the frequency-divided clock obtained by the integral frequency division; said PLL circuit further comprising: a control circuit which, if the result of cumulative addition by said adder circuit is equal to or greater than MD, adopts a remainder obtained by dividing said result by MD as a new cumulative result, and which if, the value obtained by adding MF to a present cumulative result, is equal to or greater than MD, sets to N+1 the dividing ratio of said frequency dividing circuit for defining the next integral frequency dividing interval; and a decoder circuit which provides, to said phase adjusting circuit, a weighting signal for deciding, based on the cumulative result, an interior division ratio for dividing the timing difference in said phase adjusting circuit; wherein a clock having at all times a frequency of fvco/(N+MF/MD), which is obtained by dividing a frequency fvco of the output of the voltage-controlled oscillator by the dividing ratio N+MF/MD, being output from said phase adjusting circuit is input to said phase comparator circuit. 3. A PLL circuit comprising:
a frequency dividing circuit which performs integral frequency-division of an output clock output from a voltage-controlled oscillator; a phase adjusting circuit which receives two frequency-divided clock signals of mutually different phases obtained by integral frequency division by said frequency dividing circuit, or two frequency-divided clock signals generated from one clock signal, which has been obtained by integral frequency division by said frequency dividing circuit, having mutually different phases and a period identical with that of said one clock signal, and produces an output signal which includes, as a delay time, a time component that is the result of dividing, in accordance with a prescribed interior division ratio, a timing difference between rising edges or falling edges of the two clock signals input thereto; a phase comparator circuit, which receives a reference clock and a frequency-divided clock that is output from said phase adjusting circuit and detects a phase difference between these two clocks; a charge pump which generates a voltage conforming to the phase difference detected by said phase comparator circuit; a loop filter which provides an output voltage, which is obtained by smoothing the voltage conforming to the phase difference, to said voltage-controlled oscillator as a control voltage; an accumulator which performs addition cumulatively in units of MF every integral frequency dividing interval, where MF represents an integer that defines the numerator of a fractional dividing ratio and MD represents an integer that defines the denominator of the fractional dividing ratio; a control circuit which, if a value obtained by adding MF to the present cumulative result is equal to or greater than MD, adopts a remainder obtained by dividing this cumulative result by MD as a new cumulative result MF′ and changes the integral dividing ratio from N to N+1, and which, if the value obtained by adding MF to the present cumulative result is less than MD, adopts this cumulative result as is, makes the integral dividing ratio equal to N and, on the basis of this cumulative result, generates and outputs a weighting signal for setting the interior division ratio of the timing difference in said phase adjusting circuit; and a decoder circuit which decodes the weighting signal from said control circuit and sets the decoded weighting signal to said phase adjusting circuit; wherein a clock obtained by frequency-dividing the output of said voltage-controlled oscillator by a value N+MF/MD, which is obtained by adding a fractional dividing ratio MF/MD to the integral dividing ratio N, is input to said phase comparator. 4. The PLL circuit as defined in 5. The PLL circuit as defined in said PLL circuit further comprises: a counter which counts a frequency-divided output of said prescaler up to a predetermined count value; and circuit means which exercises control, on the basis of the count value of said counter, so as to transfer, to the input of said phase adjusting circuit, at every elapse of time of the integral frequency dividing interval, rising edges or falling edges of two clock signals of different phases output from said prescaler or of two clock signals of different phases generated from one clock signal output from said prescaler. 6. The PLL circuit as defined in wherein said control circuit comprises a first control circuit, to which receives a cumulative result output from said accumulator, for outputting a fractional dividing value decided by the cumulative result and the denominator MD, for generating a timing control signal which is activated for a prescribed interval from a timing corresponding to the integral dividing interval, and for controlling said frequency dividing circuit to set the frequency dividing ratio thereof to N+1 if the cumulative result output from said accumulator is equal to or greater than the denominator MD; and said decoder circuit decodes a fractional dividing value from said first control circuit and provides the decoded value to said phase adjusting circuit as a weighting signal for deciding the internal ratio of the timing difference; said PLL circuit further comprising a timing control circuit, to which receives a timing control signal from said first control circuit, for performing control on the basis of the timing control signal to transmit the clock output from said frequency dividing circuit to the input of said phase adjusting circuit. 7. The PLL circuit as defined in said PLL circuit further comprising: a first counter which counts an M- or (M+1)-frequency-divided output of said prescaler up to a preset count value; and a second counter which receives a carry output from said first counter and counts the (M+1)-frequency-divided output of said prescaler up to the preset count value; said second counter which outputs a signal having a period obtained by frequency-dividing the output of said voltage-controlled oscillator in accordance with the dividing ratio N or N+1. 8. The PLL circuit according as defined in wherein said control circuit comprises a first control circuit which receives count values from said first and second counters and an output from said accumulator, outputs a fractional dividing value to said decoder as a weighting signal, generates a timing signal conforming to the frequency dividing ratio, and sets the values of said first and second counters to thereby set the integral dividing ratio to N+1 in a next integral frequency dividing interval when the numerator decided by the cumulative result from said accumulator exceeds the denominator of the fractional dividing ratio; and said decoder circuit decodes the weighting signal from said first control circuit and provides the decoded signal to said phase adjusting circuit; said PLL circuit further comprising a timing control circuit, which receives a timing control signal from said first control circuit and generates a timing control circuit for supplying a signal output from said prescaler to the input of said phase adjusting circuit for a prescribed timing interval from the integral dividing interval. 9. The PLL circuit as defined in 10. The PLL circuit as defined in 11. The PLL circuit according to a first D-type flip-flop having a data input terminal for receiving a signal from said ECL/CMOS circuit which receives the output of said prescaler; and a second D-type flip-flop having a data input terminal for receiving an output signal from a data output terminal of said first D-type flip-flop; clock input terminals of said first and second flip-flops being fed with a timing control signal from said timing control circuit, outputs from data output terminals of said first and second flip-flops being provided to respective ones of input terminals of an interpolator of said phase adjusting circuit. 12. A PLL circuit as defined in a logic circuit, which receives two clocks of mutually different phases from two input terminals as first and second input signals, for outputting the result of a prescribed logic operation of the first and second input signals; a first switch element, which is connected between a first power supply and an internal node and to a control terminal whereof an output signal from said logic circuit is input, for being turned on when both the first and second input signals are at a first value to thereby form a path that charges the internal node; a buffer circuit of a non-inverting or inverting type having the internal node connected to an input terminal thereof for changing an output logic value if a magnitude relationship between a voltage level at the internal node and a threshold value has been inverted; a second switch element turned on when the first input signal is at a second value and a group of a plurality of third switch elements, which are connected in parallel with the second switch element between the internal node and a second power supply, for being turned on and off based upon the weighting signal; and a fourth switch element turned on when the second input signal is at a second value and a group of a plurality of fifth switch elements, which are connected in parallel with the fourth switch element between the internal node and the second power supply, for being turned on and off based upon the weighting signal. 13. A PLL circuit as defined in claim 3; wherein said phase adjusting circuit includes an interpolator comprising:
a logic circuit, which receives two clocks of mutually different phases from two input terminals as first and second input signals, for outputting the result of a prescribed logic operation of the first and second input signals; a first switch element, which is connected between a first power supply and an internal node and to a control terminal whereof an output signal from said logic circuit is input, for being turned on when both the first and second input signals are at a first value to thereby form a path that charges the internal node; a plurality of series circuits, each of which comprises a second switch element turned on when the first input signal is at a second value and a third switch element turned on and off based upon the weighting signal, a plurality of series circuits being connected in parallel between the internal node and a second power supply; and a plurality of series circuits, each of which comprises a fourth switch element turned on when the second input signal is at the second value and a fifth switch element turned on and off based upon the weighting signal, a plurality of series circuits being connected in parallel between the internal node and the second power supply. 14. The PLL circuit as defined in 15. The PLL circuit as defined in 16. The PLL circuit as defined in L-number (where L is 0 to K) of said third switch elements are turned on by weighting signals applied to said group of third switch elements; (K−L)-number of said fifth switch elements are turned on by weighting signals applied to said fifth switch elements; and a signal is output that corresponds to a timing obtained by internally dividing the timing difference between the first and second input signals based upon K using 1/K of this timing difference as a unit, and the internal ratio of the timing difference is varied by varying the value of L. 17. The PLL circuit as defined in 13, wherein said phase adjusting circuit comprises a plurality of said interpolators arranged in at least two stages;
the two frequency-divided clocks obtained by integral frequency division are input to respective ones of two input terminals of each of two interpolators of a first stage; and two outputs from said two interpolators of said first stage are input to respective ones of two input terminals of an interpolator of a second stage. 18. The PLL circuit as defined in Description [0001] This invention relates to a phase-locked loop circuit and, more particularly, to a phase-locked loop circuit of fractional frequency-dividing type. [0002] In order to control the frequency of an output signal at a frequency interval smaller than the frequency of a reference signal, the conventional practice is to employ an arrangement which averages, in terms of time, a frequency dividing ratio of a programmable frequency dividing circuit with the frequency dividing ratio being variable in an ordinary phase-locked loop (PLL) to implement a frequency dividing ratio of an accuracy finer than a decimal-point by using the average value. A configuration in which the dividing ratio of a frequency dividing circuit is changed and averaged in terms of time to implement fractional frequency division in equivalent terms is also referred to as a fractional frequency-dividing system. [0003] If one period 1/fr of a reference signal of which frequency is fr is adopted as one clock, then, by switching the frequency dividing ratio from M to M+1 only once over L clocks (time T), the average value of the dividing ratio over the time T will be given by M+1/L. [0004] By extending the term 1/L of this fractional part to k/L, where k=0, 1, 2, . . . , the frequency dividing ratio can be set at steps of 1/L. The frequency-dividing ratio is given as follows. [0005]FIG. 15 is a block diagram illustrating the structure and principle of such a fractional frequency-dividing PLL circuit. A phase comparator, a charge pump, a loop filter and a voltage-controlled oscillator of the PLL circuit have been deleted from the diagram of FIG. 15; only a frequency dividing circuit and a control circuit thereof are shown. As illustrated in FIG. 15, the PLL circuit is constituted by an accumulator [0006] When the dividing ratio is changed periodically, as in the fractional frequency dividing scheme of the arrangement shown in FIG. 15, a spurious having frequency components of a period of this change is generated. In other words, if T represents a period of the change in the frequency dividing ratio of the frequency dividing circuit [0007] In order to reduce this spurious component, the specification of Japanese Patent Application Laid-Open No. 8-8741 discloses an arrangement of the kind shown in FIG. 16 as a frequency synthesizer (PLL circuit) for controlling output-signal frequency at frequency intervals that are smaller than a reference-signal frequency, thereby reducing spurious components in the vicinity of the center frequency of the output signal. The arrangement shown in FIG. 16 includes a phase comparator [0008] The frequency-division control circuit [0009] The fractional part calculating circuit [0010] The total sum of the values generated by the carry signals produced by each of the accumulators at each clock is output to the fractional part calculating circuit [0011] If M represents an integer data, K a fraction data and n the number of bits constituting the accumulator [0012] Though the frequency component of a change in dividing ratio appears as a spurious output from the VCO, the frequency of the change in dividing ratio resulting from connecting the accumulators in four stages increases and the low frequency component decreases. The periodic change is disturbed by always adding [0013] An arrangement of the kind shown in FIG. 17 (which uses the so-called “Delta-Sigma” technique) also is known as a PLL circuit of the fractional frequency-dividing type. Here a dividing-ratio control circuit [0014] Also known is a PLL circuit having means which compensates for the charge and discharge current of a charge pump resulting from the occurrence of a spurious signal caused by periodically varying a frequency dividing ratio. For example, as shown in FIGS. 18 and 19, charge pumps [0015] In all of the arrangements described above, fractional frequency division is achieved by changing and then averaging the dividing ratio of a variable frequency divider, and a spurious signal is produced in the output of a voltage-controlled oscillator due to the change in the dividing ratio of the frequency divider. The above-mentioned arrangements are for suppressing and compensating for such spurious signals. In other words, none of these arrangements has a construction that is free of spurious signals. [0016] As a consequence, a problem with the prior art is that the circuitry for reducing spurious signals becomes large in scale. For example, arrangements (FIGS. 18 and 19) for suppressing spurious signals by compensating charge-pump current involve circuitry of very large scale. [0017] Accordingly, it is an object of the present invention to provide an entirely novel PLL circuit that makes fractional frequency division possible without causing spurious signals to be produced in the output of a voltage-controlled oscillator. [0018] The foregoing object is accomplished in accordance with one aspect of the present invention by providing a PLL circuit comprising: a phase comparator circuit which receives a reference clock from one input terminal thereof to output a phase difference; a charge pump which generates a voltage conforming to the phase difference output from said phase comparator circuit; a loop filter which performs smoothing the voltage conforming to the phase difference; a voltage-controlled oscillator which receives an output voltage of said loop filter as a control voltage to output a clock having an oscillation frequency determined by the control voltage; a frequency dividing circuit which performs integral frequency-division of an output clock output from said voltage-controlled oscillator; a phase adjusting circuit which receives two frequency-divided clocks of mutually different phases obtained by integral frequency division at said frequency dividing circuit to produce an output signal having a delay time defined by a time that is the result of dividing a timing difference between the two frequency-divided clocks in accordance with a prescribed interior division ratio, said interior division ratio being made variable; and control means which provides a signal for variably setting, every integral frequency dividing interval, the interior division ratio with which the timing difference is divided in the phase adjusting circuit; wherein a frequency-divided clock that is output from said phase adjusting circuit is fed to another input terminal of said phase comparator circuit so that a phase of the frequency-divided clock is compared with that of the reference clock. [0019] In accordance with another aspect of the present invention, the dividing ratio for frequency dividing the clock output of the voltage-controlled oscillator is N+MF/MD, which is defined by an integral dividing ratio N and a fractional dividing ratio MF/MD. The frequency dividing circuit has its integral dividing ratio set to N or N+1, and the control means has an adder circuit for performing addition cumulatively in units of MF based upon the frequency-divided clock obtained by integral frequency division. [0020] In accordance with another aspect of the present invention, the PLL circuit further includes a control circuit which, if the result of cumulative addition is equal to or greater than MD, adopts a remainder obtained by dividing this result by MD as a new cumulative result, and which if, a value of addition of MF to the present cumulative result, is equal to or greater than MD, sets to N+1 the dividing ratio of the frequency dividing circuit for defining the integral frequency dividing interval; and a decoder circuit for outputting, to the phase adjusting circuit, a weighting signal for deciding, on the basis of the cumulative result, the interior division ratio for dividing the timing difference in the phase adjusting circuit. [0021] With the PLL circuit according to the present invention, a clock having a frequency of fvco/(N+MF/MD), which is obtained by dividing a frequency fvco of the output of the voltage-controlled oscillator by the dividing ratio N+MF/MD at all times, is input to the phase comparator circuit. [0022] In accordance with another aspect of the present invention, the phase adjusting circuit includes an interpolator comprises: a logic circuit, which receives two clocks of mutually different phases from two input terminals as first and second input signals, for outputting the result of a prescribed logic operation of the first and second input signals; a first switch element, which is connected between a first power supply and an internal node and to a control terminal whereof an output signal from said logic circuit is input, for being turned on when both the first and second input signals are at a first value to thereby form a path that charges the internal node; a plurality of series circuits, each of which comprises a second switch element turned on when the first input signal is at a second value and a third switch element turned on and off based upon the weighting signal, a plurality of series circuits being connected in parallel between the internal node and a second power supply; and a plurality of series circuits, each of which comprises a fourth switch element turned on when the second input signal is at the second value and a fifth switch element turned on and off based upon the weighting signal, a plurality of series circuits being connected in parallel between the internal node and the second power supply. [0023] Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive. [0024]FIG. 1 is a block diagram illustrating the basic structure of an embodiment of the present invention; [0025]FIG. 2 is a diagram useful in describing the operation of a first embodiment of the present invention; [0026]FIG. 3 is a block diagram illustrating the structure of the first embodiment; [0027]FIG. 4 is a diagram illustrating the connection relationship among signals of the first embodiment; [0028]FIG. 5 is a timing diagram useful in describing the operation of the first embodiment; [0029]FIG. 6 is a diagram useful in describing the operation of the first embodiment; [0030]FIG. 7 is a diagram showing an example of the circuitry of an interpolator; [0031]FIG. 8 is a diagram showing another example of the circuitry of an interpolator; [0032]FIG. 9 is a block diagram illustrating the structure of the second embodiment; [0033]FIG. 10 is a diagram illustrating the connection relationship among signals of a second embodiment of the present invention; [0034]FIG. 11 is a timing diagram useful in describing the operation of the second embodiment; [0035]FIG. 12 is a diagram illustrating an example of timing for setting the weighting signal of an interpolator in the second embodiment; [0036]FIG. 14 [0037] FIG. [0038]FIG. 14 [0039]FIG. 14 [0040]FIG. 15 is a block diagram useful in describing the principle of a frequency dividing circuit in a conventional fractional frequency-dividing PLL circuit; [0041]FIG. 16 is a block diagram illustrating an example of the structure of a conventional fractional frequency-dividing PLL circuit; [0042]FIG. 17 is a block diagram illustrating the structure of a conventional Delta-Sigma PLL circuit; [0043]FIG. 18 is a block diagram illustrating an example of the structure of a conventional current-compensated PLL circuit; and [0044]FIG. 19 is a diagram illustrating the details of the structure of a charge pump circuit in the conventional current-compensated PLL circuit shown in FIG. 17. [0045] A preferred embodiment of the present invention will now be described. [0046] In a first embodiment of the present invention, as shown in FIG. 1, a PLL circuit comprises: a frequency dividing circuit ( [0047] In a case where the cumulative result obtained by the adder circuit ( [0048] In accordance with the present invention as described above, a signal obtained by frequency-dividing, at all times, the output (frequency fvco) of the voltage-controlled oscillator ( [0049] The control circuit ( [0050] An arrangement may be adopted in which power consumption is controlled on the basis of a power control signal (POWW in FIG. 3) from a control circuit ( [0051] In the present invention, an arrangement may be adopted in which a signal output from a prescaler ( [0052] In an embodiment of the present invention, a phase adjusting circuit comprises an interpolator for producing an output signal the delay time of which is stipulated by a time obtained by dividing the timing difference between two input signals thereof at a prescribed internal ratio. The interpolator comprises: a logic circuit (NAND [0053] In the PLL circuit according to the present invention, the above-described interpolator constituting the phase adjusting circuit may be so arranged that a plurality of serially connected switch elements and capacitors are connected in parallel between the internal node (N [0054] In the PLL circuit according to this embodiment of the invention, the above-described interpolator constituting the phase adjusting circuit is such that each of the second, third, fourth and fifth switch elements comprises at least a prescribed number (K) of elements, L-number (where L is 0 to K) of the third switch elements (MN [0055] In accordance with this embodiment of the present invention, the dividing ratio of the frequency-divided clock applied to the phase comparator circuit is fixed at N+MF/MD, and spurious signals are not produced. That is, the present invention is not designed to obtain the dividing ratio by averaging, as in the conventional fractional frequency dividing technique. Since each frequency-divided clock cycle is the frequency-dividing period of N+MF/MD, in theory no spurious noise is produced. [0056] Embodiments of the present invention will now be described with reference to the drawings in order to explain the invention in more detail. [0057]FIG. 1 is a block diagram illustrating the structure of an embodiment of the present invention. As shown in FIG. 1, a PLL circuit according to this embodiment includes a phase comparator circuit [0058] The phase adjusting circuit [0059] The output clock of the phase adjusting circuit [0060] An adder circuit [0061] In a case where the result of accumulation from the adder circuit [0062] In a case where the sum obtained by adding MF to the present cumulative result is equal to or greater than MD, the adder circuit [0063] In the next integral frequency-dividing interval, the frequency dividing circuit [0064] The control circuit [0065] The resolution of the dividing value (interior division ratio ) of the timing difference between the two frequency-divided clocks of different phases output from the frequency dividing circuit [0066] An example of operation of the PLL circuit according to the embodiment of the invention shown in FIG. 1 will now be described for a case where the resolution of the timing difference of phase adjusting circuit [0067] The timing-difference dividing value of the phase adjusting circuit [0068] 5/16 (integral frequency dividing ratio 1800), [0069] 10/16, [0070] 15/16, [0071] 20/16=4/16 (integral frequency dividing ratio 1801), [0072] 9/16 (integral frequency dividing ratio 1800), [0073] 14/16, [0074] 19/16=3/16 (integral frequency dividing ratio 1801), [0075] 8/16, [0076] 13/16, [0077] 18/16=2/16 (integral frequency dividing ratio 1801), [0078] 7/16, [0079] 12/16, [0080] 17/16=1/16 (integral frequency dividing ratio 1801), [0081] 6/16, [0082] 11/16, [0083] 16/16=0/16 (integral frequency dividing ratio 1801), [0084] 5/16 [0085] At this time the value of the numerator is summed with modulo [0086] For example, if 5/16 is added when the present value is 15/16, we have 15/16+5/16=20/16, so that 4/16 (integral frequency dividing ratio 1801) is obtained. [0087] In this case, the control circuit [0088] The period of the frequency-divided clock obtained by frequency division using the frequency dividing circuit [0089] In the present invention, the period of the clock (period tCK) obtained by frequency-dividing the output of the voltage-controlled oscillator [0090]FIG. 2 is a diagram useful in describing the operation principle of the present invention. FIG. 2 schematically illustrates the operation principle for a case where the resolution at which the timing difference of the phase adjusting circuit [0091] The phase adjusting circuit [0092] 3/7 (frequency division number 3), [0093] 3/7+3/7=6/7 (frequency division number 3), [0094] 3/7+3/7+3/7=9/7=2/7[frequency division number 3+1; timing obtained by dividing, at 2/7, the timing difference (clock period tCK) from the rising edge of the clock whose frequency has been divided by 4], [0095] 2/7+3/7=5/7 (frequency division number 3), [0096] 5/7+3/7=8/7=1/7 [frequency division number 3+1; timing obtained by dividing, at 1/7, the timing difference (clock cycle tCK) from the leading edge of the clock whose frequency has been divided by [0097] 1/7+3/7=4/7 (frequency division number 4), [0098] 4/7+3/7=7/7=0/7 (frequency division number 3+1) [0099] Thus, seven cycles in 24 clock cycles, i.e., a frequency dividing ratio of 3+3/7 is obtained. [0100] As shown in FIG. 2, the phase adjusting circuit [0101] In FIG. 2, a main frequency dividing counter (a counter included in the control circuit of FIG. 1 for performing integral frequency division) exercises control through which the integral frequency dividing ratio N of the frequency dividing circuit [0102]FIG. 3 is a diagram illustrating the detailed structure of an example of a PLL circuit according to this embodiment of the present invention. As shown in FIG. 3, the PLL circuit according to this embodiment of the invention comprises an amplifier [0103] Further, 1/8 frequency-divided outputs of the 32/33 prescaler [0104] Further, a 32/33 frequency-divided output (24 MHz or 43 MHz) of the 32/33 prescaler [0105] The A counter [0106] By virtue of this counter arrangement, the B counter [0107] In order to make the integral dividing ratio equal to N+ [0108] The signal fvco/N, which is obtained by integral frequency-dividing the output signal (frequency fvco) of the voltage-controlled oscillator [0109] The output MC of the changes the dividing ratio of the 32/33 prescaler [0110] The integer MF, which defines the numerator of the fractional dividing ratio MF/MD, and the output (the current value from the adder [0111] The set count values A, B of the counters [0112] Upon receiving the control signal WIE in the active state, the timing/power control signal generator [0113] As a result of the foregoing, the interpolator [0114] Let MD represent a step(resolution) of the timing difference between two input clocks in the interpolator [0115]FIG. 4 illustrates the arrangement and signal line connection relationship of the interpolator [0116]FIGS. 5 [0117] Upon receiving the output of the A counter [0118] At the 0th clock, the POWW signal is deactivated (placed at the High level) to deactivate the ECL/CMOS circuit [0119] As shown in FIG. 4, the 32/33 prescaler [0120] With reference again to FIG. 3, the interpolator [0121] The principle of operation of this embodiment of the present invention will now be described with reference to FIG. 6. FIG. 6 is a diagram for describing the operating principle in a case where the dividing ratio has been made 4.25 (integral dividing ratio 4+fractional dividing ratio 1/4) for the sake of simplicity. [0122] The main frequency dividing circuitry ( [0123]FIG. 7 is a diagram showing an example of the structure of the interpolator [0124] Further, a capacitor C is connected between the internal node [0125] The operation of internally dividing a timing difference will be described for a case where N-number of the 16 parallel-connected N-channel MOS transistors are turned on by the input signal IN [0126] Let the current that flows into one of the parallel N-channel MOS transistors be I (the current value of the constant-current source [0127] Assume that the input signals IN [0128] First, at N=16, 16 of the 16 parallel N-channel MOS transistors MN [0129] If N=n (n<16) holds (N is set by the control signal C), n-number of N-channel MOS transistors to the gates of which the inverted signal of the input signal IN [0130] The time T′ is given by the following: (CV−n·I·T)/( [0131] Accordingly, the time T(n) from the moment the input signal IN [0132] Depending upon the value of n, there is obtained an output signal having a phase obtained by equally dividing the timing difference T between the input signals IN [0133] Two signals between which a timing difference is one clock cycle tCK, for example, are applied to the inputs IN [0134] It should be noted that a 16-step interpolator can be constructed by always turning off N-channel MOS transistors MN [0135] The capacitor C shown in FIG. 7, may be substituted by an arrangement in which a plurality of series circuits, each of which comprises a switch element constituted by an N-channel MOS transistor and a capacitor, are connected in parallel between the internal node N [0136] The interpolator shown in FIG. 7 is such that the internal node N [0137]FIG. 8 illustrates an example of the circuitry of the interpolator [0138] The capacitor C shown in FIG. 8, may be substituted by an arrangement in which a plurality of series circuits, each of which comprises a switch element constituted by an N-channel MOS transistor and a capacitor, are connected in parallel between the internal node N [0139] In the arrangements of FIGS. 7 and 8, the positions of the N-channel MOS transistors MN [0140]FIG. 9 illustrates a structure of a second embodiment of the present invention, FIG. 10 is a diagram illustrating the connections to the interpolator portion of FIG. 9, and FIG. 11 is a diagram illustrating the timing waveforms on principal signals. [0141] As shown in FIG. 9, the second embodiment of the invention has an interpolator [0142] This embodiment includes a 16/17 prescaler [0143] The signal WIE from a control circuit [0144] Signals R [0145] Signals S [0146] Signals T [0147] The interpolators [0148] In a case where a timing difference (tCK) of the two input clocks is divided at X/16 by the second interpolator [0149] As shown in FIG. 11, the control circuit [0150] Described next will be the timing at which the interior division ratio of the timing difference is variably set in the interpolator. FIGS. 12 and 13 are diagrams useful in describing the setting timing of the weighting signal from the decoders [0151] In a case where the numerator MF x m is equal to or greater than the denominator MD in the weighting signal applied to the interpolator, the increment (+1) of the dividing ratio in the frequency dividing circuit becomes the cycle (integral frequency dividing period) before one-cycle changeover of the interpolator. The control signal MC and weighting signal of the prescalers [0152] Referring now to FIG. 12 and FIG. 3, from the result 13/16 of fractional frequency division performed by the adder [0153] In the initial main dividing period, the weighting signal 13/16 supplied from the control circuit [0154] In the next main division period (N+1 division period), the ECL/CMOS circuit [0155] In FIG. 13 also, the weighting signal of the interpolator [0156] In the next main division period (N+1 division period), the weighting signal 1/16 is set in the interpolator over the time during which the WIE signal is at the low level, namely from the vicinity of about 1000th clock to −48th clock. [0157]FIG. 14 [0158] In the uncompensated fractional dividing-type PLL circuit (see FIG. 15), spurious components (720.025 MHz±m×25 kHz) appear conspicuously every 25 kHz on both sides of the frequency 720.025 MHz of the voltage-controlled oscillator, as shown in FIG. 14 [0159] As many apparently widely different embodiments of the present invention can be made without departing from the spirit and scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims. [0160] The meritorious effects of the present invention are summarized as follows. [0161] Thus, in accordance with the present invention, as described above, the structure of a PLL circuit for implementing fractional frequency division is simplified and there is no occurrence of spurious components inevitably produced in the prior art by the conventional fractional frequency division methods. [0162] The reason for this is that the output of the voltage-controlled oscillator is frequency-divided and input to the phase comparator so that the period of the frequency-divided clock compared with the reference signal is rendered a constant fractional dividing value, i.e., so that the frequency is rendered constant. [0163] It should be noted that other objects, features and aspects of the present invention will become apparent in the entire disclosure and that modifications may be done without departing the gist and scope of the present invention as disclosed herein and claimed as appended herewith. [0164] Also it should be noted that any combination of the disclosed and/or claimed elements, matters and/or items might fall under the modifications aforementioned. Referenced by
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