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Publication numberUS20020045279 A1
Publication typeApplication
Application numberUS 09/569,069
Publication dateApr 18, 2002
Filing dateMay 10, 2000
Priority dateJun 30, 1999
Also published asUS6391659
Publication number09569069, 569069, US 2002/0045279 A1, US 2002/045279 A1, US 20020045279 A1, US 20020045279A1, US 2002045279 A1, US 2002045279A1, US-A1-20020045279, US-A1-2002045279, US2002/0045279A1, US2002/045279A1, US20020045279 A1, US20020045279A1, US2002045279 A1, US2002045279A1
InventorsO-Sung Kwon, Chang-Ju Choi
Original AssigneeO-Sung Kwon, Chang-Ju Choi
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Methods for fabricating ferroelectric memory devices using pulsed-power plasma
US 20020045279 A1
Abstract
There is provided a method for fabricating a ferroelectric memory device, which can prevent the deterioration of the ferroelectric characteristics from etching damage generated during etching process of the interlayer-insulating layer formed over the capacitor to form a contact hole. The present invention is characterized by etching the interlayer-insulating layer with the use of time-modulated plasma, namely pulsed-power plasma. Accordingly, the present invention can prevent the deterioration of the ferroelectric characteristics from etching, omit or reduce the later separate thermal process for recovering the etching damage and enhance the reliability of device.
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Claims(10)
What is claimed is:
1. A method for fabricating a ferroelectric memory device, which comprises the steps of:
forming an interlayer-insulating layer over the entire structure completed with the formation of a ferroelectric capacitor including a bottom electrode, a ferroelectric layer and a top electrode; and
selectively etching the interlayer-insulating layer with pulsed-power plasma to form a contact hole exposing the top electrode of capacitor.
2. The method according to claim 1, further comprising the step of performing process for forming wire connected with the top electrode in the capacitor.
3. The method according to claim 1, wherein the interlayer-insulating layer is formed with silicon oxide.
4. The method according to claim 3, wherein the step of etching is performed with the conditions of a source power of about 800 W, a bias power of about 600 W, a pressure of about 5 mTorr, a temperature of about 40° C., a CF4 flow rate of about 15 sccm and an Ar flow rate of about 15 sccm.
5. The method according to claim 4, wherein the step of etching is performed with a frequency ranging form about 1 kHz to about 100 kHz.
6. A method for fabricating a ferroelectric memory device, which comprises the steps of:
forming a first interlayer-insulating layer over the entire structure completed with the formation of transistor;
forming a capacitor which includes a bottom electrode, a ferroelectric layer and a top electrode and in which the ferroelectric layer and the top electrode are superimposed on a part of the bottom electrode; forming a second interlayer-insulating layer over the ferroelectric capacitor; and
selectively etching the second interlayer-insulating layer with pulsed-power plasma to form a contact hole exposing the top electrode of capacitor.
7. The method according to claim 6, further comprising the step of performing process for forming wire connected with the top electrode in the capacitor.
8. The method according to claim 6, wherein the interlayer-insulating layer is formed with silicon oxide.
9. The method according to claim 8, wherein the step of etching is performed with the conditions of a source power of about 800 W, a bias power of about 600 W, a pressure of about 5 mTorr, a temperature of about 40° C., a CF4 flow rate of about 15 sccm and an Ar flow rate of about 15 sccm.
10. The method according to claim 9, wherein the step of etching is performed with a frequency ranging form about 1 kHz to about 100 kHz.
Description
FIELD OF THE INVENTION

[0001] The present invention relates to fabrication methods of semiconductor memory devices; and, more particularly, to fabrication methods of ferroelectric memory devices, which can reduce the damage from plasma etching by using a pulsed-power technique.

DESCRIPTION OF THE PRIOR ART

[0002] By using ferroelectric material into capacitors in semiconductor memory devices, there have been proceeded the developments of the devices which can overcome the limitation of refresh present in the conventional DRAM (Dynamic Random Access Memory) devices and have large capacitance of memory. FeRAM (ferroelectric random access memory) devices as non-volatile memory devices can store information even at the condition of power off and also are equitable in operating speed to the conventional DRAM. So, they are promising as a future generation of storage devices.

[0003] Thin films of SrBi2Ta2O9 (hereinafter, referred as SBT) and Pb(Zr, Ti)O3 (hereinafter, referred as PZT) are mainly used as capacitance material in FeRAM devices. The ferroelectric materials have hundreds or thousands of dielectric constant at room temperature and two stable remanent polarization states. So, they are applied to the practices of nonvolatile memory devices with the states of thin films. The nonvolatile device with the ferroelectric thin film uses the principle that if an electric field is applied to the device to adjust the orientation of polarization and to input a signal, then the orientation of remanent polarization remained when the electric field is removed makes the digital signal 1 or 0 be stored in the device.

[0004] After completed with the formation of a capacitor comprising of a bottom electrode, a ferroelectric thin film and a top electrode, an oxide layer for interlayer insulating is formed over the entire structure and selectively dry-etched to form contact holes exposing the top electrode and the bottom electrode.

[0005] In the conventional fabrication method of FeRAM device, the dry etching is performed with plasma generated by RF (radio frequency) or micro power of hundreds kHz or several GHz. This method necessarily induces electrical or physical damage in the device.

[0006] In case of DRAM, the etching damage from plasma may be recovered in any later thermal process, so it does not result in problems. However, in case of FeRAM using ferroelectric material such as SBT, the ferroelectric characteristics may be easily deteriorated with the plasma. This deterioration results in decreasing the reading and writing performances of FeRAM and reducing the lifetime of the device. Thus, a separate thermal treatment for recovering the ferroelectric characteristics should be performed at about 700° C. for about 30 minutes.

[0007] Accordingly, there are required process developments, which can reduce the damage of ferroelectric layer generated during dry etching with plasma for the oxide layer covered over the capacitor.

SUMMARY OF THE INVENTION

[0008] It is, therefore, an object of the present invention to provide a method for fabricating ferroelectric memory devices, which can prevent the deterioration of ferroelectric characteristics generated from conventional dry etching with continuous wave plasma for interlayer-insulating layer for forming capacitor contact.

[0009] In accordance with an embodiment of the present invention, there is provided a method for fabricating a ferroelectric memory device, which comprises the steps of forming an interlayer-insulating layer over the entire structure completed with the formation of a ferroelectric capacitor including a bottom electrode, a ferroelectric layer and a top electrode; and selectively etching the interlayer-insulating layer with pulsed-power plasma to form a contact hole exposing the top electrode of capacitor.

[0010] In accordance with another embodiment of the present invention, there is provided a method for fabricating a ferroelectric memory device, which comprises the steps of forming a first interlayer-insulating layer over the entire structure completed with the formation of transistor; forming a capacitor which includes a bottom electrode, a ferroelectric layer and a top electrode and in which the ferroelectric layer and the top electrode are superimposed on a part of the bottom electrode; forming a second interlayer-insulating layer over the ferroelectric capacitor; and selectively etching the second interlayer-insulating layer with pulsed-power plasma to form a contact hole exposing the top electrode of capacitor.

[0011] The present invention is characterized in that the interlayer-insulating layer covering the capacitor is etched with time modulated plasma, namely pulsed-power plasma. The pulsed-power plasma has lower electron temperature and ion energy within the plasma than the conventional continuous wave plasma. This is because high energetic electrons in the plasma are cooled during plasma off-period when the main power is adjusted with several decades microseconds.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:

[0013]FIG. 1 is a graph showing electron energy distribution functions of pulsed-power plasma at some duty ratios, compared with electron energy distribution function of continuous wave plasma.

[0014]FIG. 2 is a graph showing electron energy distribution functions of pulsed-power plasma at some modulation frequencies, compared with that of continuous wave plasma.

[0015]FIG. 3 is a cross-sectional view showing the fabrication processes for the ferroelectric memory device in accordance with one embodiment of the present invention.

[0016]FIG. 4 is a graph showing the ferroelectric polarization characteristics with input voltage at some modulation frequencies for generating the pulsed-power plasma.

[0017]FIG. 5 is a graph showing the cumulative possibility characteristics with the ferroelectric polarization at some modulation frequencies for generating the pulsed-power plasma.

[0018]FIG. 6 is a graph showing the ferroelectric polarization characteristics with the input voltage at some duty ratios for generating pulsed-power plasma.

[0019]FIG. 7 is a graph showing the cumulative possibility characteristics with the ferroelectric polarization at some duty ratios for generating the pulsed-power plasma.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The pulsed-power plasma as used herein means the plasma generated by using pulsed-power inductively coupled plasma technique with time modulation.

[0021] The electrical damage suppression method in ferroelectric capacitor contact etching is also described in a document entitled with “Electrical Damage Suppression Using a Pulsed-Power Inductively Coupled Plasma in Ferroelectric Capacitor Contact Etching” published by the th inventors on May 10, 1999 at 1999 4th International Symposium on Plasma Process-Induced Damage, which correlates with the present invention and is incorporated herein by reference.

[0022] The invention will be illustrated in detail by the following preferred embodiments with reference to the accompanying drawings.

[0023]FIG. 1 is a graph showing electron energy distribution functions of pulsed-power plasma at some duty ratios, compared with electron energy distribution function of continuous wave plasma. The duty ratio means the ratio of voltage inputting time for forming pulsed-power plasma among entire plasma generating time.

[0024]FIG. 2 is a graph showing electron energy distribution functions of pulsed-power plasma at some modulation frequencies, compared with that of continuous wave plasma.

[0025] As shown in the results of FIGS. 1 and 2, the pulsed-power plasma can generate the less etching damage than the continuous wave (CW) plasma.

[0026]FIG. 3 shows a fabrication method of a ferroelectric memory device in accordance with one embodiment of the present invention.

[0027] First, a first interlayer-insulating layer 11 is formed with SiO2 or the like over a semiconductor substrate (not shown) completed with the formation of transistor and the others (not shown). Then, a Pt bottom electrode 12, an SBT layer 13 and a Pt top electrode 14 are, in turn, formed on the first interlayer-insulating layer 11. At this time, the SBT layer 13 and the Pt top electrode 14 are superimposed on a part of the Pt bottom electrode 12.

[0028] Subsequently, a second interlayer-insulating layer 15 with SiO2 or the like is formed with a thickness of about 5500Å over the entire structure. A photoresist pattern 16 to define the region of contact hole is then formed on the second interlayer-insulating layer 15. The second interlayer-insulating layer is then selectively etched with pulsed-power plasma using the photoresist pattern 16 as an etching mask to form contact holes exposing the Pt top electrode 14 and the Pt bottom electrode 12.

[0029] At this time, the etching is performed with the conditions of a source power of 800 W, a bias power of 600 W, a pressure of 5 mTorr, a temperature of 40° C., a CF4 flow rate of 15 sccm, and an Ar flow rate of 15 sccm. The frequency for generating the pulsed-power plasma may range from 1 kHz to 100 kHz.

[0030] Later, metal wires (not shown) are formed to connect with the Pt top electrode 14 and the Pt bottom electrode 12, respectively.

[0031] Meanwhile, though the above-described embodiment explains the present invention with an example of exposing all of the top and bottom electrodes, the present invention may be applied to the process to expose only the top electrode.

[0032]FIG. 4 is a graph showing the ferroelectric polarization characteristics with input voltage at some modulation frequencies for generating the pulsed-power plasma. The ferroelectric characteristics such as remanent polarization 2 Pr and coercive voltage Vc at the pulsed-power mode is not changed from the values of initial capacitor. On the other hand, the hysteresis loop after CW contact etching is degraded greatly in term of polarization and coercive voltage.

[0033]FIG. 5 is a graph showing the cumulative possibility characteristics with the ferroelectric polarization at some modulation frequencies for generating the pulsed-power plasma. As shown in FIG. 5, when the cumulative possibility is 50%, while the value of 2 Pr is about 9.2 μC/cm2 in case of continuous wave (CW) plasma, the value of 2 Pr in case of pulsed-power plasma is about 10.2 μC/cm2 with regardless of frequency. Accordingly, when the etching is performed with the input of the pulsed-power plasma, the value of 2 Pr is less decreased by about 1 μC/cm2.

[0034]FIG. 6 is a graph showing the ferroelectric polarization characteristics with the input voltage at some duty ratios for generating pulsed-power plasma. The ferroelectric characteristics such as remanent polarization 2 Pr and coercive voltage Vc at the pulsed-power mode is not changed from the values of initial capacitor. On the other hand, the hysteresis loop after CW contact etching is degraded greatly in term of polarization and coercive voltage.

[0035]FIG. 7 is a graph showing the cumulative possibility characteristics with the ferroelectric polarization at some duty ratios for generating the pulsed-power plasma. As shown in FIG. 7, when the cumulative possibility is 50%, while the value of 2 Pr is about 9.2 μC/cm2 in case of continuous wave (CW) plasma, the value of 2 Pr in case of pulsed-power plasma is about 10.4 μC/cm2 with regardless of frequency. Accordingly, when the etching is performed with the input of the pulsed-power plasma, the value of 2 Pr is less decreased by about 1.2 μC/cm2.

[0036] The present invention is to etch the interlayer-insulating layer over the capacitor by using the pulsed-power plasma compared with the conventional continuous wave plasma. Accordingly, the present invention can reduce the etching damage of the ferroelectric layer with regardless of process window in consideration of the plasma properties. According to this, the present invention can prevent the deterioration of the ferroelectric characteristics from etching, omit or reduce the later separate thermal process for recovering the etching damage and enhance the reliability of device.

[0037] While the present invention has been described with respect to certain preferred embodiments only, other modifications and variations may be made without departing from the spirit and scope of the present invention as set forth in the following claims.

Classifications
U.S. Classification438/3, 257/E21.664, 257/E21.252, 257/E27.104, 257/E21.009, 257/E21.577
International ClassificationH01L21/311, H01L27/115, H01L21/02, H01L21/768, H01L21/8246
Cooperative ClassificationH01L27/11502, H01L28/55, H01L27/11507, H01L21/76802, H01L21/31116
European ClassificationH01L21/311B2B, H01L27/115C, H01L27/115C4
Legal Events
DateCodeEventDescription
Dec 27, 2013REMIMaintenance fee reminder mailed
Oct 21, 2009FPAYFee payment
Year of fee payment: 8
Oct 28, 2005FPAYFee payment
Year of fee payment: 4
May 10, 2000ASAssignment
Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, R
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KWON, O-SUNG;CHOI, CHANG-JU;REEL/FRAME:010803/0156
Effective date: 20000508
Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. BUBAL-EUB