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Publication numberUS20020047196 A1
Publication typeApplication
Application numberUS 09/420,817
Publication dateApr 25, 2002
Filing dateOct 19, 1999
Priority dateAug 17, 1999
Also published asUS6620648, US20020024151, US20040256708
Publication number09420817, 420817, US 2002/0047196 A1, US 2002/047196 A1, US 20020047196 A1, US 20020047196A1, US 2002047196 A1, US 2002047196A1, US-A1-20020047196, US-A1-2002047196, US2002/0047196A1, US2002/047196A1, US20020047196 A1, US20020047196A1, US2002047196 A1, US2002047196A1
InventorsJicheng Yang
Original AssigneeJicheng Yang
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Multi-chip module with extension
US 20020047196 A1
Abstract
A multi-chip module may include a pair of chips which are arranged one over the other on each side of a laminate layer. A central passage through the laminate layer provides a passage to wire bond a chip on a first side of the laminate layer to contacts on a second side of the laminate layer. A second chip is also placed on the second side of the laminate layer. By causing the laminate layer to extend outwardly beyond the first and second chips, and providing contacts on the extension, contact may be made to the laminate layer extension for electrically coupling the first and second chips to the outside world.
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Claims(37)
What is claimed is:
1. A multi-chip module comprising:
a laminate layer having top and bottom sides and a passage;
a first chip secured to the bottom side of said layer, said first chip wire bonded to the top side of said layer through said passage;
a second chip secured to the top side of the layer and coupled by bumps to said layer; and
said layer including an extension beyond at least one of said chips, said extension including solder ball contacts on said bottom side, electrically coupled to said first and second chips.
2. The module of claim 1 including a pair of opposed extensions each extending outwardly beyond the rest of the module and each having contacts.
3. The module of claim 1 wherein said extension extends all the way around said module.
4. The module of claim 1 wherein said first chip is bonded to said layer using adhesive securement.
5. The module of claim 4 wherein said adhesive securement is adhesive tape.
6. The module of claim 1 wherein the overall height of said module is approximately one millimeter or less.
7. The module of claim 1 wherein said first and second chips are aligned one over the other and centered over said passage.
8. The module of claim 7 wherein said passage is centered in said layer.
9. The module of claim 1 wherein said package has bilateral symmetry.
10. The module of claim 1 wherein said region between said first and second chips is filled with encapsulant.
11. The module of claim 1 wherein said extension extends outwardly beyond said first and second chips.
12. A method of forming a multi-chip module comprising:
adhesively securing a first chip to a first surface of a laminate layer;
inverting the assembly of said laminate layer and said first chip;
wire bonding said first chip to a second surface of said laminate layer;
securing a second chip to the second surface of said laminate layer using bumps;
positioning said first and second chips on said laminate layer so that at least a portion of said laminate layer extends outwardly beyond said first and second chips; and
providing solder ball contacts on said first surface of said extension electrically coupled to said first and second chips.
13. The method of claim 12 including aligning said first and second chips over one another.
14. The method of claim 13 including providing a pair of extensions extending outwardly beyond said first and second chips.
15. The method of claim 13 including aligning said chips so as to form an extension of said laminate layer that extends outwardly beyond said chips and completely around said module.
16. The method of claim 14 including providing solder balls on said contacts on said extensions.
17. The method of claim 12 including filling a region between said chips with an encapsulant.
18. The method of claim 17 including forming a passage through said laminate layer and forming wire bonds from said first chip through said passage to the second surface of said laminate layer.
19. The method of claim 17 including coupling said contact and said first and second chips through traces extending through said laminate layer.
20. A multi-chip module comprising:
a central support layer having a top side and a bottom side, a bonding pad on each of said sides and conductive interconnections extending through said layer;
a first chip secured to the bottom side of said layer;
a second chip secured to the top side of said layer, said second chip secured by bumps to said layer; and
said layer extending outwardly beyond said first and second chips, said layer including a solder ball pad on an extension extending outwardly beyond said first and second chips for electrically connecting said chips to external devices.
21. The module of claim 20 wherein said layer is a laminate layer.
22. The module of claim 20 wherein said first chip is adhesively secured to said layer.
23. The module of claim 22 wherein said first chip is secured by adhesive tape to said layer.
24. The module of claim 20 wherein said layer includes a central aperture, said first chip wire bonded to the top side of said layer through said aperture.
25. The module of claim 20 having an overall height of less than approximately 1 millimeter.
26. The module of claim 20 wherein said extension extends outwardly beyond said first and second chips in two directions.
27. The module of claim 20 wherein said layer extends beyond said chips completely around said chips.
28. The module of claim 20 wherein said first and second chips are aligned with one another and positioned centrally on said layer.
29. The module of claim 28 wherein a passage is formed centrally through said layer for wire bonding said first chip to said layer.
30. A method comprising:
coupling a first chip to a first side of a support structure;
coupling a second chip to a second side of said support structure;
causing said support structure to extend outwardly beyond the first chip; and
providing solder ball pads on the portion of said structure extending outwardly beyond said first chip, said pads electrically coupled to said first and second chips.
31. The method of claim 30 wherein coupling a first chip includes adhesively coupling a first chip to said support structure.
32. The method of claim 31 wherein coupling a first chip includes wire bonding said first chip to bonding pads on said second side of said support structure.
33. The method of claim 30 wherein coupling a second chip includes bump bonding said second chip to said second side of said support structure.
34. The method of claim 30 wherein causing said support structure to extend outwardly includes causing said support structure to extend outwardly from two opposed edges of the first chip.
35. The method of claim 34 wherein causing said support structure to extend outwardly includes causing said support structure to extend outwardly beyond four edges of said first chip.
36. The method of claim 30 wherein causing said support structure to extend outwardly includes causing said support structure to extend outwardly beyond said first and second chips.
37. The method of claim 30 including coupling said first and second chips to said solder ball pads on said portion via traces extending through said structure.
Description
BACKGROUND

[0001] This invention relates generally to multi-chip modules for coupling more than one chip together in a single package.

[0002] For a number of reasons, it is desirable to package more than one integrated circuit die or chip in a single package. In some cases, the two dice may necessitate different processing technologies. In such case, the two dice must be made independently and then combined thereafter. For example, one die may be made using a bipolar process and another may be made using a complementary metal oxide semiconductor (CMOS) process. Similarly, one die may use a logic process and the other die may use a memory process. For example, some dice may use stacked gate designs which may be incompatible with logic processes.

[0003] Thus, in a variety of situations, it may be desirable to put components in close proximity without making them on the same integrated circuit fabrication process. In addition, in some cases, the level of integration available may be such that to achieve the full capabilities, separate dice must be used. If separate dice are used, it may still be desirable to connect the dice together to the outside world through a single set of input and output connections. These input and output connections may be, for example, pins or solder balls. In some cases it may be desirable to interconnect the two dice to each other and then to interconnect them together to the outside world.

[0004] Thus, there is a need for packages which enable dice to be connected together before connection to the outside world.

SUMMARY

[0005] In accordance with one aspect, a multi-chip module includes a laminate layer having a top and a bottom sides and a passage. A first chip is secured to the bottom side of the layer. The first chip is wire bonded to the top side of the layer through the passage. A second chip is secured to the top side of the layer by bumps. The layer includes an extension accessible beyond one of the chips. The extension includes contacts on said bottom side, electrically coupled to said first and second chips.

[0006] Other aspects are described in the accompanying specification and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007]FIG. 1 is a greatly enlarged cross-sectional view of one embodiment of the present invention;

[0008]FIG. 2 is a greatly enlarged cross-sectional view of a subassembly, in accordance with the embodiment shown in FIG. 1, after a first chip has been connected to a laminate layer and the assembly wire bonded;

[0009]FIG. 3 is a greatly enlarged cross-sectional view of the embodiment shown in FIG. 2 after a second chip has been attached;

[0010]FIG. 4 is a greatly enlarged cross-sectional view of the package of FIG. 3 after it has been subject to encapsulation;

[0011]FIG. 5 is a greatly enlarged bottom plan view of one embodiment of the present invention; and

[0012]FIG. 6 is a greatly enlarged bottom plan view of another embodiment of the present invention.

DETAILED DESCRIPTION

[0013] Referring to FIG. 1, a multi-chip module 10 includes a first chip 16, a second chip 22 and a laminate layer 12 sandwiched between the first and second chips 16 and 22. The laminate layer 12 provides one or more layers of conductive traces separated by insulators and coupled by vias to enable interconnection between the first chip 16, the second chip 22 and external devices (not shown).

[0014] The laminate layer 12 includes an upper side 30, a lower side 32 and central passage 14. The central passage may extend along the length of the module 10 in a rectangular arrangement, in one embodiment of the invention.

[0015] As shown in FIG. 1, the laminate layer 12 may extend outwardly beyond both of the first and second chips 16 and 22 to form an extension 40. The extension 40 provides a contact surface to make contact with external devices.

[0016] The first chip 16 may be coupled to the laminate layer 12 by extending wire bond wires 20 through the central passage 14 to the pads 34 on the upper surface 30 of the laminate layer 12, as shown in FIG. 2. The first chip 16 may be physically coupled to the second chip 22 by an adhesive layer 18. The adhesive layer 18 may conventionally be an adhesive tape strip which adhesively secures the upper surface of the first chip 16 to the lower surface 32 of the laminate layer 12.

[0017] The second chip 22 may be coupled to the laminate layer 12 directly using bumps 24 which may be formed of solder balls. As illustrated, the bumps 24 may be of substantially smaller diameter than the bumps 28 provided for connecting the entire module 10 to external devices.

[0018] In this way, a relatively low profile multi-chip module may be fabricated. For example, by way of illustration only, in one embodiment of the present invention, the first and second chips 16 and 22 may be on the order of 0.25 millimeters thick, the laminate layer 12 may be on the order of 0.25 millimeters thick and the spacing between the first and second chips may be on the order of 0.1 millimeters in the case of the second chip 22 and 0.075 millimeters in the case of the first chip 16. This gives an overall height of less than one millimeter. If the solder bumps 28 are on the order of 0.5 millimeters in diameter, the overall height of the assembly may be on the order of about one millimeter, for example 0.85 millimeter. Thus, a relatively compact, low profile assembly may be fashioned using the winged extension 40.

[0019] Referring now to FIG. 2, the sequence of assembling the multi-chip module 10 is illustrated. Initially the first chip 16 is secured by adhesive tape 18 to the lower surface 32 of the laminate layer 12, wire bond wires 20 extend through the passage 14 to couple the pads 34 on the upper surface 30 of the laminate layer 12 to the first chip 16.

[0020] Turning next to FIG. 3, the second chip 22 may be surface mounted on the laminate layer 12 using solder balls 24. After a reflow step, the solder balls 24 soften sufficiently to secure the second chip 22 to be contacts 44 on the upper surface of the laminate layer 12.

[0021] Thereafter, the entire assembly is placed in an encapsulation mold, in one embodiment of the present invention, forming the encapsulant 26 in the regions between the first and second chips 16 and 22, as shown in FIG. 4. This leaves the extension 40 extending outwardly from the rest of the package. Alternatively, the gaps between the chips 16 and 22 may be filled up with underfill material.

[0022] For example, in one embodiment of the present invention, solder balls or bumps 28 may be electrically coupled by contacts 52 or 62 to a trace 48 or 58 by way of a via 50 or 60. The traces 48 and 58 in turn may be coupled to each of the contacts 54 or 44 on the upper surface 30 of the laminate layer 12 by way of a via, 56 or 46.

[0023] Finally, the solder balls 28 or other interconnection devices are secured to the extensions 40. In this way, external devices may be contacted by the solder balls 28, making electrical connections to the first and second chips 16 and 22 through the laminate layer 12.

[0024] Referring to FIG. 5, in one embodiment of the present invention, the extension 40 may extend outwardly from each opposed edges 41 of the module 10. Solder balls 28 may be aligned along each side in the length direction of the extension 40. In some embodiments, each extension 40 may extend outwardly beyond than the approximate width of one solder ball 28 so that a plurality of solder balls may be coupled, two or more solder balls deep, along the edges 41 of the module 10.

[0025] Referring to FIG. 6, in accordance with still another embodiment of the present invention, the extension 40 may extend around all four edges 41 of the module 10. In this way, solder balls 28 may be coupled along four edge portions 41 a-d to increase the number of connections that may be made. Again, the extension 40 may extend further outwardly to allow solder balls to be attached, two or more deep, along the edges 41 of the module 10.

[0026] While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7763961 *Apr 1, 2006Jul 27, 2010Stats Chippac Ltd.Hybrid stacking package system
Classifications
U.S. Classification257/723, 257/E23.035, 257/E23.052, 257/E23.039, 257/E25.013, 257/E23.125
International ClassificationH01L23/31, H01L23/495, H01L25/065
Cooperative ClassificationH01L24/48, H01L2924/14, H01L2224/48091, H01L2225/06572, H01L2224/4824, H01L2224/32014, H01L23/49575, H01L23/49527, H01L2924/1532, H01L2225/0651, H01L23/4951, H01L23/3121, H01L2225/06517, H01L2225/06575, H01L2924/15311, H01L2225/06586, H01L2224/16, H01L25/0657, H01L2224/73215
European ClassificationH01L23/31H2, H01L23/495C6, H01L23/495A4, H01L25/065S, H01L23/495L
Legal Events
DateCodeEventDescription
Oct 19, 1999ASAssignment
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YANG, JICHENG;REEL/FRAME:010330/0908
Effective date: 19990729