BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a semiconductor device, and more particularly to a method of forming a semiconductor device using shallow trench isolation (STI), thereby reducing the negative slope of the field region.
2. Description of the Related Art
Electrical isolation of circuit elements such as transistors, diodes, resistors, etc. is generally required during the initial steps of semiconductor device production, thus critically affecting the size of the active region as well as the procedural margin of subsequent processes. The customary method for providing such isolation is the LOCOS (LOCal Oxidation of Silicon) technique.
The LOCOS method of element isolation generally consists of sequentially depositing an oxide and nitride layer over a silicon substrate, patterning the nitride layer, and selectively subjecting the silicon substrate to oxidation to form the field oxide layer. According to this method, oxygen penetrates from beneath the nitride layer serving as the selective oxidation mask into the side of the pad oxide layer, generating a so-called “bird's beak” formation at the edges of the field oxide layer. Since such bird's beak extends the field oxide layer into the active region to its length, the channel length is shortened to bring about the so-called “narrow channel effect”, thereby increasing the threshold voltage. This, in turn, degrades the electrical characteristics of the transistor. Particularly, since LOCOS isolation results in a channel length below 0.3 μm, a phenomenon called “punch-through” occurs, connecting the field oxide layers at both sides of the active region, so that the active region is not correctly secured.
In view of this, the STI method is used for a semiconductor device fabrication according to the design rule of less than 0.25 μm. The STI process generally comprises the steps of etching a silicon substrate to form a trench with a given depth, depositing an oxide layer over the substrate including the trench, and etching the oxide layer by etch back or chemical mechanical polishing (CMP) process to form the active region with the trench filled flat with the oxide layer. The undoped silicate glass (USG) or ozone-tetraethylorthosilicate (O3-TEOS USG) has been primarily used as the oxide layer for filling the trench. However, as the aspect ratio of the trench increases so that the trench is not completely filled with the USG layer, voids occur within the trench. Hence, high-density plasma oxide tends to be used, having greater stability and more suitable properties for filling the gap, rather than the USG layer.
FIGS. 1 to 4 are cross sectional views of a conventional non-volatile memory device for illustrating the conventional method of forming a device using self-aligned shallow trench isolation (SA-STI), which may reduce the size of the memory cell by making the active pattern identical with the floating gate pattern.
Referring to FIG. 1, sequentially deposited over a silicon substrate 10 are a tunnel oxide layer 12, first polysilicon layer 14, nitride layer 16, and high-temperature oxide layer (not shown). The first polysilicon layer 14 is used for the floating gate.
Photolithography is performed on the high-temperature oxide layer of the active region to produce a patterned mask, according to which the nitride layer 16 and first polysilicon layer 14 are sequentially etched to produce the active pattern defining the active region. Then, the substrate 10 is etched to a predetermined depth to form a trench using the patterned mask of the high temperature oxide layer. Subsequently, although not shown, in order to treat the silicon damage caused by the impact of high-energy ions during etching the trench 18, the side walls of the trench are covered with a thermal oxidation layer, over which is deposited a nitride liner both to prevent leakage current and to improve the characteristics of the gate oxide layer.
Subsequently, deposited over the substrate is an oxide layer 20 of high-density plasma with enough thickness to completely fill the trench 18 by chemical vapor deposition (CVD). The oxide layer 20 of high density plasma may be deposited by generating a high density plasma based on a gas of SiH4, O2 and Ar. Namely, SiH4 and O2 are combined to form SiO2 deposited over the wafer, the back-side of which is applied with an RF bias voltage to attract the particles of Ar and O2 to the surface of the wafer, so as to generate the Ar sputter etch to fill the trench 18. However, during this process, the Ar sputter etch clips both the nitride layer 16 and the first polysilicon layer 14 so that the upper side-walls of the trench 18 form negative slopes at about 60°. Then, the oxide layer 20 of high density plasma is removed by CVD until the surface of the nitride layer 16 is exposed, so as to attain the field region of the STI structure filled flat with the oxide layer 20 of high density plasma.
Referring to FIG. 2, the nitride layer 16 is stripped off by phosphoric acid. This produces empty spaces at the lower edges of the field regions due to the negative slopes of the STI structure. Then, as shown in FIG. 3, a second polysilicon layer 22 is deposited over the substrate, which fills the empty spaces under region “A” with the second polysilicon layer 22, thus increasing the amount of polysilicon under the negative slopes of the field region. The second polysilicon layer 22 is provided to increase the area of the dielectric interlayer subsequently formed, serving as the floating gate together with the first polysilicon layer 14.
Referring to FIG. 4, photolithography is performed to remove the second polysilicon layer 22. Then, deposited over the substrate is a dielectric interlayer of ONO (not shown) both to isolate the control gate from the floating gate and to increase the static electric capacitance. Photolithography is performed to remove the dielectric interlayer, second polysilicon layer 22, and first polysilicon layer 14 in the peripheral circuit region. Then, sequentially deposited over the resulting formation are a third polysilicon layer and tungsten silicide layer (not shown), which in turn is subjected to photolithography to sequentially etch the tungsten silicide layer, third polysilicon layer, dielectric interlayer, second polysilicon layer 22, and first polysilicon layer 14 in the memory cell region and peripheral circuit region, thus forming the stacked gate of the memory transistor. Additional photolithography is performed to etch the tungsten silicide layer and third polysilicon layer in the peripheral circuit region to form the gate of the transistor.
However, the conventional method usually causes the oxide layer to block the polysilicon layer existing below the field region due to the anisotropic property of the dry etching and the selectivity between the polysilicon and the oxide layer. This results in the conductive stringer 24 of the polysilicon part not being etched in the form of a line as shown in FIG. 4. Such a stringer generates a bridge between the adjacent gate patterns, degrading the properties of the semiconductor elements and yield rate.
SUMMARY OF THE INVENTION
It is an object of the present invention to eliminate the effect of the negative slopes in the field region in formation of a semiconductor device using STI.
According to an aspect of the present invention, provided is a method for fabricating a semiconductor device, for example a non-volatile memory device having a stacked gate (memory cell) consisting of a floating gate, a control gate deposited over the floating gate, and a dielectric interlayer interposed between them. The method comprises the steps of sequentially depositing a tunnel oxide layer, a first polysilicon layer for the floating gate, and a nitride layer over a semiconductor substrate; sequentially etching the nitride layer, first polysilicon layer, and semiconductor substrate to form a trench, depositing an oxide layer over the substrate to fill the trench, removing the oxide layer to the level of the nitride layer to attain a field region of the trench isolation, removing the nitride layer, subjecting the field region to a wet-chemical treatment, and depositing a second polysilicon layer for the floating gate over the substrate.
Preferably, the wet chemical treatment is performed so as to etch the oxide layer by an amount in the range of 100 to 200 Å. It is also preferred to subject the field region to a wet chemical treatment before the step of removing the nitride layer.
The present invention provides a method of changing the negative slopes of the field region into approximately positive slopes by employing the isotropic etching effect of the wet chemical process after removing the nitride layer from the field region of the STI structure.