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Publication numberUS20020050403 A1
Publication typeApplication
Application numberUS 09/370,990
Publication dateMay 2, 2002
Filing dateAug 10, 1999
Priority dateMay 28, 1998
Also published asUS6410978
Publication number09370990, 370990, US 2002/0050403 A1, US 2002/050403 A1, US 20020050403 A1, US 20020050403A1, US 2002050403 A1, US 2002050403A1, US-A1-20020050403, US-A1-2002050403, US2002/0050403A1, US2002/050403A1, US20020050403 A1, US20020050403A1, US2002050403 A1, US2002050403A1
InventorsAkio Yasukawa, Hirohisa Yamamura, Tatsuya Shigemura
Original AssigneeAkio Yasukawa, Hirohisa Yamamura, Tatsuya Shigemura
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device
US 20020050403 A1
Abstract
A semiconductor device in which fatigue failure of a solder layer underneath a semiconductor chip mounted on a base can be prevented from occurring due to repetitions of turn-on and -off of power during operation thereof, is provided, that is, a recess is formed in the base in a part underneath the semiconductor chip so as to prevent occurrence of thermal expansion in the base.
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Claims(1)
What is claimed is:
1. A semiconductor device having a base on which a semiconductor chip is mounted, and a recess formed in said base in a part underneath said semiconductor chip.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Filed of the Invention

[0002] The present invention relates to a semiconductor device having a base on which a semiconductor chip is mounted.

[0003] 2. Related Art

[0004] In a conventional semiconductor device as disclosed in Japanese Laid-Open Patent No. H10-22428, a base to which a semiconductor chip is joined, is flat. With the repetitions of turn-on and -off of power in this device during use thereof, the temperature rise is repeated in a part of the base in which the semiconductor chip is joined, and accordingly, a solder layer underneath the semiconductor chip clacks by fatigue, resulting in a problem of damage thereof. Thus, there has been a premise of solving the above-mentioned problem.

SUMMARY OF THE INVENTION

[0005] The present invention is devised in order to solve the above-mentioned problem inherent to the above-mentioned prior art device, and accordingly, one object of the present invention is to provide a semiconductor device which can reduce strain caused in a solder layer joined to a semiconductor chip so as to be prevented from incurring a fatigue failure.

[0006] To the end according to the present invention, there is provided a semiconductor device comprising a base, and a semiconductor chip mounted on the base, wherein a recess is formed in the base in a part underneath the semiconductor chip.

[0007] The present invention will be detailed in the form of a preferred embodiment with reference to the accompanying drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a cross-sectional view illustrating a semiconductor device in an embodiment of the present invention;

[0009]FIG. 2 is a sectional view along line A-A′ show in FIG. 1;

[0010]FIG. 3 is sectional view for explaining the operation of the semiconductor device shown in FIG. 1; and

[0011]FIG. 4 is a characteristic view showing a temperature distribution in the base shown in FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0012] Referring to FIG. 1, a plurality of semiconductor chips 1 are joined onto an insulating substrate 2 through the intermediary of a solder layer 3, and the insulating substrate 2 is in turn joined onto a base 4 through the intermediary of a solder layer 5. The base 4 is formed therein with recesses 4 a in a surface thereof on the side remote from the semiconductor chips in parts corresponding respectively to the chips 1 mounted thereon. The base 4 is joined thereto with an intermediate board 7 for covering the recesses 4 a, by means of a blazing filler material. The thickness of the brazing filler material is very thin, and accordingly, the brazing filled material is not shown in the accompanying drawings. A plurality of nozzles 6 are joined to the intermediate board 7 by a brazing filler material. The nozzles 6 are located respectively at positions corresponding to the recesses 4 a, respectively. Further, a outflow pipe 8 is brazed to the intermediate board 7, and a lower board 10 to which an inflow pipe 9 is brazed, is brazed to the intermediate board 7 so as to cover inflow holes in the nozzles 6.

[0013] When the device is operated so as to generate a heat from the chips 1, cooling liquid 11 is led into the device from the inflow pipe 9, and then, the cooling liquid 11 flows through the nozzles 6 and impinges upon the bottoms of the recesses 4 a. Thereafter, the cooling liquid 11 flows around the nozzles 6 and is discharged from the device after flowing through the outflow pipe 8. In this embodiment, the insulating substrate 2 is made of AlN, and the base 4 is made of Cu or Al. With the combination of the materials having high heat-conductivity, the heat generated from the chips 1 can be effectively transmitted to the cooling liquid 11.

[0014] Since the heat generated from the chips 1 during the operation of the device, is transmitted to the cooling liquid 11 by way of the base underneath the chips 1, the temperature of the base 4 in parts underneath the chips 1 rises up. At this time, in the conventional device, great thermal expansion occurs in the base since no recesses are formed in these parts, and accordingly, the lower parts of the insulating substrate 2 underneath the chips 1 are expanded so as to produce large strain in the solder layer 3 between the insulating substrate 2 and the chips 1. With the repetitions of turn-on and -off of power, this strain is repeatedly effected. Thus, there has been presented a problem of occurrence of fatigue failure of the soldering layer.

[0015] On the contrary, in the instant embodiment, since the recesses 4 a are formed in the base 4, the parts 4 b of the base underneath the chips 1 are thin, and are surrounded therearound by parts 4 c having a thickness larger than that of the parts 4b. In this arrangement, the temperature is distributed so that it is high in the thin parts 4 b underneath the chips, but is low in the thick parts 4 c, as shown in FIG. 4 which shows a temperature distribution on a straight line passing through the center line of the chip as viewed at a plan B-B′ in FIG. 3 and from the above. Accordingly, with reference to FIG. 3, even though the thin parts 4 b tend to thermally expand, the thermal expansion of the thin part 4 b are restrained by the thick parts 4 c therearound, having a low temperature. That is, restraining force 12 is effected so as to restrain expansion. Thus, it is possible to prevent occurrence of fatigue failure of the solder layer.

[0016] With the provision of the recesses 4 a, as to the solder layer 5 for joining the insulating substrate, the strain can be decreased though a similar mechanism, thereby it is possible to exhibit such a technical effect and advantage that fatigue failure can be prevented.

[0017] In this embodiment, the shape of the recesses 4 a are circular in a plan view as shown in FIG. 2. With the circular shape, a plurality of recesses 4 a can be formed simultaneously by drilling. Accordingly, it is possible to manufacture the device in a short time in comparison with other shapes.

[0018] With the device according to the present invention, it is possible to prevent occurrence of large strain in the solder layers, thereby it is possible to prevent occurrence of fatigue failure in the solder layers.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7345353Dec 30, 2005Mar 18, 2008International Business Machines CorporationSilicon carrier having increased flexibility
US8763243 *Jun 18, 2012Jul 1, 2014Industrial Technology Research InstituteFabrication method of substrate
US20120258573 *Oct 11, 2012Industrial Technology Research InstituteFabrication method of substrate
WO2007077109A2 *Dec 15, 2006Jul 12, 2007IbmSilicon carrier having increased flexibility
Classifications
U.S. Classification174/260, 257/E23.004, 257/E23.098, 257/701
International ClassificationH01L23/13, H05K1/02, H05K3/34, H05K1/03, H05K3/00, H01L23/12, H05K7/20, H01L23/473
Cooperative ClassificationH05K1/0271, H05K2201/10674, H01L23/13, H01L2924/0002, H05K1/0306, H05K2201/09745, H05K3/341, H05K3/0061, H01L23/473
European ClassificationH05K1/02E, H01L23/473, H01L23/13
Legal Events
DateCodeEventDescription
Aug 10, 1999ASAssignment
Owner name: HITACHI, LTD., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YASUKAWA, AKIO;YAMAMURA, HIROSHISA;SHIGEMURA, TATSUYA;REEL/FRAME:010163/0432
Effective date: 19990723
Nov 29, 2005FPAYFee payment
Year of fee payment: 4
Feb 1, 2010REMIMaintenance fee reminder mailed
Jun 25, 2010LAPSLapse for failure to pay maintenance fees
Aug 17, 2010FPExpired due to failure to pay maintenance fee
Effective date: 20100625