Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20020058381 A1
Publication typeApplication
Application numberUS 09/987,391
Publication dateMay 16, 2002
Filing dateNov 14, 2001
Priority dateNov 15, 2000
Also published asUS6444525
Publication number09987391, 987391, US 2002/0058381 A1, US 2002/058381 A1, US 20020058381 A1, US 20020058381A1, US 2002058381 A1, US 2002058381A1, US-A1-20020058381, US-A1-2002058381, US2002/0058381A1, US2002/058381A1, US20020058381 A1, US20020058381A1, US2002058381 A1, US2002058381A1
InventorsDa Lee
Original AssigneeHynix Semiconductor Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for manufacturing a nonvolatile memory
US 20020058381 A1
Abstract
A method for manufacturing a nonvolatile memory includes steps of forming a first trench of a first width in a substrate of a first conductivity type, forming a second trench within the first trench, having a second width smaller than the first width of the first trench, injecting ions into a surface of the substrate and into sidewalls of the first and second trenches to adjust a threshold voltage, forming first insulating films sidewalls on the sidewalls of the first and second trenches, forming source and drain regions by injecting second conductive impurity ions into the substrate and bottom surfaces of the first and second trenches, depositing a second insulating film on the substrate, forming a floating gate and a gate electrode on sidewalls of the second insulating film within the first and second trenches, depositing a third insulating film on the substrate, and forming a control gate on sidewalls of the third insulating film at a sidewall of the first trench.
Images(10)
Previous page
Next page
Claims(11)
What is claimed is:
1. A method for manufacturing a nonvolatile memory comprising the steps of:
forming a first trench of a first width in a substrate of a first conductivity type;
forming a second trench within the first trench, having a second width smaller than the first width of the first trench;
injecting ions into a surface of the substrate and into sidewalls of the first and second trenches to adjust a threshold voltage;
forming first insulating film sidewalls on the sidewalls of the first and second trenches;
forming source and drain regions by injecting second conductive impurity ions into the substrate and bottom surfaces of the first and second trenches;
depositing a second insulating film on the substrate;
forming a floating gate and a gate electrode on sidewalls of the second insulating film within the first and second trenches;
depositing a third insulating film on the substrate; and
forming a control gate on sidewalls of the third insulating film at a sidewall of the first trench.
2. The method according to claim 1, wherein the step of injecting ions into a surface of the substrate and into sidewalls of the first and second trenches includes tilt ions.
3. The method according to claim 1, wherein the step of forming the floating gate and the gate electrode includes the steps of forming a conductive film on the second insulating film, and patterning the conductive film to remain only on the second insulating film within the first and second trenches.
4. The method according to claim 3, further comprising the step of adjusting a resistance of the conductive film after forming the conductive film using one of injecting ions and POCL3 processing.
5. The method according to claim 3, wherein the conductive film is formed of polysilicon.
6. The method according to claim 1, wherein the third insulating film is formed to fill the second trench.
7. The method according to claim 1, further comprising the steps of:
depositing a fourth insulating film on the substrate;
forming a contact hole by selectively removing the second, third, and fourth insulating films to expose the source and drain regions formed on the bottom surface of the second trench; and
forming a metal plug in the contact hole.
8. The method according to claim 7, wherein the fourth insulating film is formed of an oxide film.
9. The method according to claim 1, wherein the first insulating film, the second insulating film and the third insulating film are formed of an oxide film.
10. The method according to claim 1, wherein the control gate is formed by depositing a polysilicon film, and etching the polysilicon film to remain only on the sidewalls of the third insulating film.
11. The method according to claim 10, further comprising the step of adjusting a resistance of the polysilicon film by one of POCL3 processing and ion injection after the step of depositing the polysilicon film.
Description
  • [0001]
    The present invention claims the benefit of Korean Patent Application No. P2000-67718 filed in Korea on Nov. 15, 2000, which is hereby incorporated by reference.
  • BACKGROUND OF THE INVENTION
  • [0002]
    1. Field of the Invention
  • [0003]
    The present invention relates to a method for manufacturing a semiconductor memory, and more particularly, to a method for manufacturing a nonvolatile memory.
  • [0004]
    2. Background of the Related Art
  • [0005]
    In general, semiconductor memories, such as a static random access memory (SRAM), a dynamic random access memory (DRAM), and a read only memory (RAM), for example, have been widely used. The DRAM is most widely used due to the spread of personal computers. The DRAM commands more than 80% of the semiconductor memory market.
  • [0006]
    Presently, nonvolatile memories have begun to substitute for DRAM memories. In several years, nonvolatile memories, such as flash and electrically erasable programmable ROM (EEPROM), for example, may substitute for the DRAM memory. However, in a related art nonvolatile memory technology, an area of the nonvolatile memory is increased when a select gate is selected considering a size of a memory cell. Therefore, only a few ranking semiconductor corporations can mass-manufacture the nonvolatile memory due to sophisticated manufacturing process steps. Accordingly, it is most important to minimize the size of the nonvolatile memory and to simplify the manufacturing process steps.
  • SUMMARY OF THE INVENTION
  • [0007]
    Accordingly, the present invention is directed to a method for manufacturing a nonvolatile memory that substantially obviates one or more problems due to limitations and disadvantages of the related art.
  • [0008]
    An object of the present invention is to provide a method for manufacturing a vertical nonvolatile memory having two trenches to minimize size.
  • [0009]
    Another object of the present invention is provide a method for manufacturing a nonvolatile memory using a reduced number of masks, thereby simplifying manufacturing processing.
  • [0010]
    Additional features and advantages of the invention will be set forth in the description which follows, and in part will apparent from the description, or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
  • [0011]
    To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a method for manufacturing a nonvolatile memory includes forming a first trench of a first width in a substrate of a first conductivity type, forming a second trench within the first trench, having a second width smaller than the first width of the first trench, injecting ions into a surface of the substrate and into sidewalls of the first and second trenches to adjust a threshold voltage, forming first insulating film sidewalls on the sidewalls of the first and second trenches, forming source and drain regions by injecting second conductive impurity ions into the substrate and bottom surfaces of the first and second trenches, depositing a second insulating film on the substrate, forming a floating gate and a gate electrode on sidewalls of the second insulating film within the first and second trenches, depositing a third insulating film on the substrate, and forming a control gate on sidewalls of the third insulating film at a sidewall of the first trench.
  • [0012]
    It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0013]
    The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention. In the drawings:
  • [0014]
    [0014]FIG. 1 illustrates a circuit diagram and an operation characteristic table of a general nonvolatile memory according to a related art; and
  • [0015]
    [0015]FIGS. 2A to 2O are cross sectional views showing exemplary manufacturing process steps of a nonvolatile memory according to the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0016]
    Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
  • [0017]
    [0017]FIG. 1 illustrates a circuit diagram of a nonvolatile memory according to a related art and a table showing voltages applied according to operation of each mode. In FIG. 1, a nonvolatile memory cell includes a select transistor Q1 and an EPROM that includes a floating gate fg and a control gate cg, wherein the select transistor Q1 selects the nonvolatile memory cell.
  • [0018]
    To program data in the nonvolatile memory cell, a voltage of 0V is applied to a source terminal of the nonvolatile memory, a voltage of 5V is applied to a drain terminal, a voltage of 12V is applied to the control gate cg of the EPPROM, and a voltage of 2V is applied to a GATE of the select transistor Q1. Electric charge tunnels through to the floating gate fg according to the voltage applied to the drain terminal, and is stored in the floating gate fg. Accordingly, data 1 or 0 is programmed according to the electric charge of the floating gate fg.
  • [0019]
    To erase the data stored in the EEPROM, a voltage of 0V is applied to the source terminal, a voltage of 5V is applied to the drain terminal, a voltage of 11V is applied to the control gate cg of the EEPROM, and a voltage of 0V is applied to the GATE of the select transistor. Therefore, the electric charge stored in the floating gate fg is discharged.
  • [0020]
    To read the programmed data, a voltage of 0V is applied to the source terminal, a voltage of 2V is applied to the drain terminal, a voltage of 5V is applied to the control gate cg of the EEPROM, a voltage of 5V is applied to the GATE of the select transistor, so that data 1 or 0 is read according to the electric charge stored in the floating gate fg of the EPPROM.
  • [0021]
    [0021]FIGS. 2A to 2O illustrate exemplary manufacturing process steps of the nonvolatile memory according to the present invention.
  • [0022]
    In FIG. 2A, a first photoresist 2 may be deposited on a p-type silicon substrate 1, and partially removed by photolithographic processing, for example, to form a first trench 3.
  • [0023]
    In FIG. 2B, the first photoresist 2 is removed, and a second photoresist 4 may be deposited on an entire surface of the p-type silicon substrate 1. Then, exposure and developing processes may be performed to expose a bottom surface of the first trench 3. Subsequently, the bottom surface of the first trench 3 is partially removed, thereby forming a second trench 5 within the first trench, wherein the second trench 5 may be narrower than the first trench 3.
  • [0024]
    In FIG. 2C, the second photoresist 4 may be removed, and p-type and/or n-type ions may be injected, for example, into surfaces of the first and second trenches 3 and 5 to control a threshold voltage.
  • [0025]
    In FIG. 2D, a first oxide film 6 may be deposited, for example, on the entire surface of the p-type silicon substrate to fill the first and second trenches 3 and 5.
  • [0026]
    In FIG. 2E, the first oxide film 6 may be removed by an anisotropic etching process, for example, thereby forming sidewall oxide films 6 a at sidewalls of the first and second trenches 3 and 5.
  • [0027]
    In FIG. 2F, n-type impurity ions may be injected, for example, into surfaces of the exposed substrate and bottom surfaces of the first and second trenches 3 and 5, thereby forming source and drain regions 7. The n-type impurity ions may not be injected into the sidewall oxide films 6 a, and may be partially injected into the exposed portion from the sidewall oxide films 6 a.
  • [0028]
    In FIG. 2G, a second oxide film 8, functioning as a gate insulating film, may be deposited, for example, on the entire surface of the substrate including the source and drain regions 7.
  • [0029]
    In FIG. 2H, a first polysilicon film 9 may be formed on the second oxide film 8. The first polysilicon film 9 may be deposited, for example, to fill the second trench 5 using flow characteristic of the first polysilicon film 9. After depositing the first polysilicon film 9, POCL3 processing or ion injection, for example, may be performed on the substrate, thereby adjusting resistance of the polysilicon film 9.
  • [0030]
    In FIG. 2I, the first polysilicon film 9 may be etched, for example, to form portion on sidewalls of the first trench 3 and within the second trench 5.
  • [0031]
    In FIG. 2J, the first polysilicon film 9 formed within the second trench 5 may be selectively removed to form portions on both sidewalls of the second trench 5, thereby respectively forming a floating gate 9 a of the EEPROM, and a gate 9 b of a select transistor. Accordingly, the floating gate 9 a is formed at the sidewall of the first trench 3, and the gate 9 b of the select transistor may be formed at the sidewall of the second trench 5.
  • [0032]
    In FIG. 2K, a third oxide film 11 may be formed on the entire surface of the substrate 1 to fill the second trench 5. Accordingly, the third oxide film 11 may serve as an insulating interlayer between the floating gate 9 a and a control gate.
  • [0033]
    In FIG. 2L, a second polysilicon film 12 may be deposited, for example, on the entire surface of the substrate 1.
  • [0034]
    In FIG. 2M, the second polysilicon film 12 may be etched, for example, thereby forming a control gate 12 a of the EPPROM at the sidewalls of the first trench 3. After depositing the second polysilicon film 12, POCL3 processing or ion injection, for example, may be performed, thereby adjusting a resistance of the second polysilicon film 12.
  • [0035]
    In FIG. 2N, a fourth oxide film 13 may be deposited, for example, on the entire surface of the substrate 1.
  • [0036]
    In FIG. 2O, the second, third and fourth oxide films 8, 11 and 13 may be selectively removed to expose the source and drain regions 7 that are formed in the bottom surface of the second trench 5, thereby forming a contact hole. Then, a metal plug 14, for example, may be formed in the contact hole, thereby completing the nonvolatile memory of the present invention.
  • [0037]
    It will be apparent to those skilled in the art that various modifications and variations can be made in the method for manufacturing a nonvolatile memory of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6818939 *Jul 18, 2003Nov 16, 2004Semiconductor Components Industries, L.L.C.Vertical compound semiconductor field effect transistor structure
US7115474 *Jun 14, 2004Oct 3, 2006Kabushiki Kaisha ToshibaNonvolatile semiconductor memory and method of manufacturing the same
US7129540 *Feb 12, 2004Oct 31, 2006Infineon Technologies AgSemiconductor circuit arrangement with trench isolation and fabrication method
US7315059May 25, 2004Jan 1, 2008Fujio MasuokaSemiconductor memory device and manufacturing method for the same
US7326614 *Nov 23, 2004Feb 5, 2008Silicon Storage Technology, Inc.Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby
US7411246Feb 4, 2003Aug 12, 2008Silicon Storage Technology, Inc.Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby
US7514321Mar 27, 2007Apr 7, 2009Sandisk 3D LlcMethod of making three dimensional NAND memory
US7537996Jun 24, 2005May 26, 2009Silicon Storage Technology, Inc.Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate
US7575973Mar 27, 2007Aug 18, 2009Sandisk 3D LlcMethod of making three dimensional NAND memory
US7659159 *May 24, 2007Feb 9, 2010Hynix Semiconductor Inc.Method of manufacturing a flash memory device
US7745265Mar 27, 2007Jun 29, 2010Sandisk 3D, LlcMethod of making three dimensional NAND memory
US7808038Mar 27, 2007Oct 5, 2010Sandisk 3D LlcMethod of making three dimensional NAND memory
US7848145Mar 27, 2007Dec 7, 2010Sandisk 3D LlcThree dimensional NAND memory
US7851851Mar 27, 2007Dec 14, 2010Sandisk 3D LlcThree dimensional NAND memory
US8836020 *Oct 31, 2011Sep 16, 2014Samsung Electronics Co., Ld.Vertical nonvolatile memory devices having reference features
US20030227048 *Feb 4, 2003Dec 11, 2003Sohrab KianianSelf aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby
US20040197997 *Apr 13, 2004Oct 7, 2004Dana LeeMethod of manufacturing an isolation-less, contact-less array of bi-directional read/program non-volatile floating gate memory cells with independent controllable control gates
US20040232472 *Jun 14, 2004Nov 25, 2004Kabushhiki Kaisha ToshibaNonvolatile semiconductor memory and method of manufacturing the same
US20040238879 *May 25, 2004Dec 2, 2004Fujio MasuokaSemiconductor memory device and manufacturing method for the same
US20050045944 *Feb 12, 2004Mar 3, 2005Achim GratzSemiconductor circuit arrangement with trench isolation and fabrication method
US20050104115 *Nov 23, 2004May 19, 2005Sohrab KianianSelf aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby
US20050269624 *Jun 24, 2005Dec 8, 2005Hu Yaw WSelf-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate
US20080132016 *May 24, 2007Jun 5, 2008Hynix Semiconductor Inc.Method of manufacturing a flash memory device
US20080237602 *Mar 27, 2007Oct 2, 2008Sandisk 3D LlcThree dimensional nand memory
US20080237698 *Mar 27, 2007Oct 2, 2008Sandisk 3D LlcMethod of making three dimensional nand memory
US20080239818 *Mar 27, 2007Oct 2, 2008Sandisk 3D LlcThree dimensional nand memory
US20080242008 *Mar 27, 2007Oct 2, 2008Sandisk 3D LlcMethod of making three dimensional nand memory
US20080242034 *Mar 27, 2007Oct 2, 2008Sandisk 3D LlcMethod of making three dimensional nand memory
US20120193705 *Aug 2, 2012Samsung Electronics Co., Ltd.Vertical nonvolatile memory devices having reference features
EP1432040A2 *Dec 5, 2003Jun 23, 2004Fujio MasuokaSemiconductor memory device and its production process
EP1482555A2 *May 27, 2004Dec 1, 2004Fujio MasuokaSemiconductor memory device and manufacturing method for the same
WO2008118432A1 *Mar 26, 2008Oct 2, 2008Sandisk 3D LlcThree dimensional nand memory and method of making thereof
WO2008118433A1 *Mar 26, 2008Oct 2, 2008Sandisk 3D LlcThree dimensional nand memory and method of making thereof
Classifications
U.S. Classification438/259, 257/E21.69, 257/E21.209, 257/E21.422, 257/E27.081, 438/291, 257/E29.306, 257/E21.693
International ClassificationH01L27/105, H01L21/28, H01L29/423, G11C16/04, H01L29/792, H01L21/8247, H01L27/115, H01L29/788, H01L21/336
Cooperative ClassificationH01L27/11556, H01L29/7885, H01L29/42336, G11C16/0433, H01L27/11524, H01L29/66825, H01L27/11521, H01L27/105, H01L21/28273
European ClassificationH01L29/66M6T6F17, H01L27/115F10C2, H01L27/115F4N, H01L29/423D2B2D, H01L21/28F, H01L27/105, H01L29/788B6B, H01L27/115F4
Legal Events
DateCodeEventDescription
Nov 14, 2001ASAssignment
Jan 10, 2005ASAssignment
Mar 22, 2006REMIMaintenance fee reminder mailed
Sep 5, 2006LAPSLapse for failure to pay maintenance fees
Oct 31, 2006FPExpired due to failure to pay maintenance fee
Effective date: 20060903