US 20020063648 A1 Abstract A method for digital-to-analog conversion of a digital input code into a first output analog signal and a second output analog signal to be supplied to a first terminal and a second terminal, respectively, of an audio load, the conversion being performed by means of a DAC with N-level balanced output, the conversion method includes using N/2 positive generator elements supplying respective positive elementary contributions which are nominally equal to one another, and N/2 negative generator elements supplying respective negative elementary contributions which are nominally equal to one another and, in absolute value, equal to the positive elementary contributions; attributing the same progressive addresses to the positive generator elements and to the negative generator elements; defining a first index for the positive input codes and a second index for the negative input codes; and, in the presence of an input code at the input of the DAC, selecting between the first index and the second index, the index corresponding to the sign of the input code; activating a first set of positive generator elements and a second set of negative generator elements, the number of the positive generator elements activated and the number of the negative generator elements activated being equal to one another and proportional to the input code, and the addresses of the positive generator elements activated and of the negative generator elements activated being a function of the selected index; generating the first output analog signal by summing the positive elementary contributions supplied by the positive generator elements activated, and generating the second output analog signal by summing the negative elementary contributions supplied by the negative generator elements activated; and updating the selected index according to the input code.
Claims(18) 1. A method for digital-to-analog conversion of a digital input code into a first output analog signal and a second output analog signal to be supplied to a first terminal and a second terminal of a load, in particular an audio load, said conversion being performed by means of a digital-to-analog converter with an N-level balanced output, said method comprising the steps of:
providing N/2 positive generator elements supplying respective positive elementary contributions that are nominally equal to one another, and N/2 negative generator elements supplying respective negative elementary contributions that are nominally equal to one another and, in absolute value, equal to the positive elementary contributions; attributing the same progressive addresses to said positive generator elements and to said negative generator elements; defining a first index for positive input codes and a second index for negative input codes; and in the presence of an input code at the input of said digital-to-analog converter:
selecting, between said first index and said second index, the index corresponding to the sign of said input code;
activating a first set of positive generator elements and a second set of negative generator elements, the number of the positive generator elements activated and the number of the negative generator elements activated being equal to one another and a function of said input code, and the addresses of the positive generator elements activated and of the negative generator elements activated being a function of said selected index (I
_{P}, I_{N}); generating said first output analog signal as a function of the positive elementary contributions supplied by the positive generator elements activated, and said second output analog signal as a function of the negative elementary contributions supplied by the negative generator elements activated; and
updating said selected index according to said input code.
2. The digital-to-analog conversion method of 3. The digital-to-analog conversion method of 4. The digital-to-analog conversion method of 5. The digital-to-analog conversion method of 6. The digital-to-analog conversion method of 7. The digital-to-analog conversion method of 8. The digital-to-analog conversion method of 9. The digital-to-analog conversion method of 10. The digital-to-analog conversion method of supplying said first output signal and said second output signal to said first terminal and said second terminal of said load according to the sign of said input code. 11. The digital-to-analog conversion method of when the sign of the input code is positive, applying said first output signal to said first terminal of said load, and said second output signal to said second terminal of said load; and
when the sign of the input code is negative, applying said first output signal to said second terminal of said load, and said second output signal to said first terminal of said load.
12. The digital-to-analog conversion method of 13. The digital-to-analog conversion method of 14. The digital-to-analog conversion method of 15. A method for digital-to-analog conversion of a digital input code into first and second analog output signals to be supplied to a first and second terminal of a load, respectively, the method performed by a digital-to-analog converter with an N-level balanced output, the converter including N/2 positive and negative generator elements configured to supply positive and negative currents, the positive currents nominally equal to one another and the negative currents nominally equal to one another, and, in absolute value, the positive and negative currents equal to each other, the digital-to-analog converter having the same progressive addresses attributed to the positive and negative generator elements and further defining a first index for positive input codes and a second index for negative input codes; the method comprising:
receiving an input code at the input of the digital-to-analog converter; selecting between the first index and the second index, the index selected corresponding to the sign of the input code; in response to the input code, activating a first set of the positive generator elements and a second set of the negative generator elements, the number of negative and positive generator elements activated being equal to one another, the addresses of the positive and negative generator elements determined as a function of the selected index; generating the first output analog signal as a function of the activated positive currents supplied by the activated first set of positive generator elements and the second output analog signal generated as a function of the negative current supplied by the activated second set of negative generator elements; and updating the selected index according to the input code. 16. A method for digital-to-analog conversion of a digital input code into first and second analog output signals to be supplied to a first and second terminal of a load, respectively, the method performed by a digital-to-analog converter with an N-level balanced output, the converter including N/2 positive and negative generator elements configured to supply positive and negative currents, the positive currents nominally equal to one another and the negative currents nominally equal to one another, and, in absolute value, the positive and negative currents equal to each other, the converter having the same progressive addresses attributed to the positive and negative generator elements and further defining a first index for positive input codes and a second index for negative input codes; the method comprising:
receiving an input code at the input of the digital-to-analog converter; selecting between the first index and a second index, the index selected corresponding to the sign of the input code; in response to the input code, activating a first set of positive generator elements and a second set of negative generator elements, the number of negative and positive generator elements activated being equal to one another, the addresses of the activated positive and negative generator elements determined as a function of the selected index; generating the first output analog signal as a function of the positive currents supplied by the activated first set of positive generator elements and the second output analog signal generated as a function of the negative current supplied by the activated second set of negative generator elements activated; updating the selected index according to the input code; and supplying the first output signal and the second output signal to a first terminal and a second terminal of a load according to the sign of the input code. 17. A method for digital-to-analog conversion of a digital input code into first and second analog output signals to be supplied to a first and second terminal of a load, respectively, the method performed by a digital-to-analog converter having an N-level balanced output, the converter including N/2 positive generator elements and N/2 negative generator elements configured to supply positive and negative currents, the positive currents nominally equal to one another and the negative currents nominally equal to one another, and, in absolute value, the positive and negative currents equal to each other, the converter having the same progressive addresses attributed to the positive and negative generator elements and further defining a first index for positive input codes and a second index for negative input codes; the method comprising:
receiving an input code at the input of the digital-to-analog converter; selecting between the first index and the second index, the index selected corresponding to the sign of the input code; in response to the input code, activating a first set of positive generator elements and a second set of negative generator elements, the number of negative and positive generator elements activated being equal to one another, the addresses of the activated positive and negative generator elements determined as a function of the selected index; generating the first output analog signal as a function of the positive currents supplied by the activated first set of positive generator elements and the second output analog signal generated as a function of the negative current supplied by the activated second set of negative generator elements; updating the selected index according to the input code; and supplying the first output signal and the second output signal to a first terminal and a second terminal of a load according to the sign of the input code, further comprising: when the sign of the input code is positive, applying the first output signal to the first terminal of the load and the second output signal to the second terminal of the load; and when the sign of the input code is negative, applying the first output signal to the second terminal of the load and the second output signal to the first terminal of the load. 18. A method for digital-to-analog conversion in a digital-to-analog converter having an N-level balanced output, the converter including N/2 positive generator elements and N/2 negative generator elements configured to supply positive and negative currents, respectively, the method comprising:
receiving an input code on an input of the digital-to-analog converter; selecting between a first index and a second index associated with positive input codes and negative input codes, respectively, the selected index corresponding to the sign of the received input code; in response to the selected index, activating a first set of positive generator elements and a second set of negative generator elements, the number of positive and negative generator elements activated being equal to one another, the addresses of the activated positive and negative generator elements determined as a function of the selected index; generating the first output analog signal as a function of the positive currents supplied by the activated first set of positive generator elements and generating the second output analog signal as a function of the negative currents supplied by the activated second set of negative generator elements; and updating the selected index according to the input code. Description [0001] 1. Field of the Invention [0002] The present invention relates to a method for dynamic matching of the elements of an integrated multibit digital-to-analog converter with balanced output for audio applications. [0003] 2. Description of the Related Art [0004] As is known, multibit digital-to-analog conversion for audio applications is performed by generating the output analog signal as the sum, at each sampling instant, of a given number of elementary quantities or contributions, which may be, for example, currents supplied by current generators or generated by means of resistors, or charges stored in capacitors. [0005] It is also known that digital-to-analog conversion can be roughly divided into two major categories according to the approach adopted in the conversion. Belonging to the first category are those digital-to-analog conversions performed adopting an approach known in the literature as “thermometric coding”, whereas belonging to the second category are those digital-to-analog conversions performed adopting an approach known in the literature as “binary coding”. [0006] In particular, in thermometric coding the elementary contributions used for generating the output analog signal assume values identical to one another and are generated by distinct generator elements numbering N, where N represents the number of levels of the output analog signal. In addition, in order to obtain a balanced output analog signal, i.e., an output signal of mean value zero able to assume either positive values or negative values that are symmetrical with respect to zero, one half of the generator elements supplies a positive elementary contribution and one half of the generator elements supplies a negative elementary contribution, and the value of each elementary contribution is 2A [0007] In binary coding, instead, the number of distinct generator elements to be implemented for generating the elementary contributions is equal to n, where n represents the number of bits of the digital-to-analog converter and is equal to n=log [0008] It may be readily appreciated how the element generating the MSB has a larger area than the element generating the LSB, and hence, in terms of area occupied, binary coding does not differ much from thermometric coding on account of the increase in the size of the generating elements due to the decrease in their number. [0009] In addition, the heavy bearing that the errors on the most significant bits have in binary coding and the relatively high complexity of implementation, in said binary coding, of so-called “scrambling” techniques, i.e., ones through which the generator elements to be activated are appropriately chosen each time from the set of the ones available with the purpose of rendering the conversion error not correlated to the signal to be converted, have recently given a strong impulse to the development of thermometric coding. [0010] At the highest level of abstraction, a digital-to-analog converter, hereinafter designated for reasons of convenience by the term “DAC”, can be represented with the block diagram shown in FIG. 1, where s[n] designates the numerical sequence that is obtained from the sampling of the input audio signal, said sequence being then processed by the blocks downstream until the reconstruction s(t) of the signal is obtained at output from the power stage. [0011] In particular, in FIG. 1 the part of numerical processing of the DAC, designated by [0012] In detail, in order to maintain the high audio fidelity, the interpolator [0013] The interpolation is followed by the noise-shaping operation performed by the noise shaper [0014] The numerical processing part is then followed by a block [0015] It is moreover known that, in the context of thermometric coding, it is not possible to integrate N generator elements that are perfectly identical to each other, and this entails the need to arrange an additional block downstream of the noise shaper, the said additional block having the purpose of offsetting the effects of the mismatch between the components, represented particularly by a non-linearity of the transfer characteristic and by the consequent distortion of the signal. [0016] The complete block diagram of a DAC with mismatch compensation thus becomes the one shown in FIG. 3, in which the compensation block is designated by [0017] In the case, for instance, in which the generator elements are constituted by current generators formed by MOS transistors, the latter, although designed identical, have different dimensions and characteristics owing to the limited accuracy that characterizes any technological integration process; the causes can be diffusion imprecisions, irregularities in the masks used in the lithographic step, undesirable variations in the thicknesses of the oxide or metal layers, etc. [0018] In addition, one of the technological processes most widely used for integration of current generators, known as Bipolar CMOS DMOS 5 (BCD5)—the most recent one among the processes able to integrate logic, linear and power circuits on the same chip—is not a technological process devised exclusively for the integration of MOS signal circuits (as may instead be the technological process known as HCMOS), and thus from said technological process very low tolerance values cannot be expected on the dimensions of the MOS transistors forming the current generators. The mismatches that take place are in fact reflected in a substantially proportional way on the values of the currents supplied by the generators on account of the linearity of the link between the drain current of a MOS transistor and its W/L shape ratio. The error that modifies the behavior of the output with respect to the desired one is strongly correlated to the signal, and consequently worsens the quality of the signal above all in terms of harmonic distortion. [0019] Each of the generator elements supplies an elementary contribution different from the expected nominal contribution, and the error thus generated is transferred unaltered onto the output analog signal in so far as it is the sum of the various elementary contributions. [0020] Given the extent of the latter (but for drifts in time) and assuming as predefined the set of generator elements activated for the synthesis of a given level K of the output analog signal, there will always be superimposed on the latter an error δ [0021] The error δ [0022] In particular, the fact that the curve passing through the mean points of the levels of the transfer characteristic of the DAC is not a straight line is an index of the non-linearity of the converter itself, and from this there derives a distortion of the signal which is all the greater the more marked is the diversity between the generator elements used for the generation of the elementary contributions that concur to form the output analog signal. [0023] Since it is not possible to perform a “static” compensation of the non-ideality of the generator elements of the DAC (on account of the excessive increase in production costs, laser trimming of the values of the individual integrated elements proves impracticable), in order to minimize the effects of the mismatches on the output signal, improving as far as possible the in-band spectrum, it has been proposed to resort to a “dynamic” compensation, which envisages modification, instant by instant, of the set of the generator elements that is used for generating the output analog signal, whatever the pattern of the input signal. [0024] The philosophy lying at the basis of dynamic compensation of the non-ideality of the generator elements may be readily understood if the errors due to the mismatches are assumed as being zero-average random ones, and if a constant input signal, for example equal to K, is considered: by always activating the same set of generator elements, at output a constant signal equal to K+δ [0025] The methodology described above is known in the literature as “Dynamic Element Matching” (DEM) and has different applications according to the modalities with which the generator elements to be activated are each time chosen. [0026] Numerous DEM techniques have been proposed for compensating the non-linearity of a DAC, the simplest being known in the literature as “Randomization” or “Scrambling”. This envisages that the generator elements to be activated are chosen altogether at random among the ones available, thus determining a variable error even in the presence of a constant input. [0027] The aforesaid methodology, however, has proved unable to lead to satisfactory results for audio applications, in so far as the random choice of the generator elements to be activated results in a considerable increase of in-band background noise, which entails a worsening of the signal to noise-and-distortion (SINAD) ratio, often unacceptable for this type of application. [0028] In addition to the unacceptable increase in the amount of noise, a second aspect which renders the above methodology useful only at a theoretical level is the clear unrealizability of a block implementing it: at each sampling instant, a high number of random values must be generated simultaneously, and this is only possible with a logic of considerable dimensions, which is not integratable on a chip on which it is intended to implement also the filtering stage necessary for eliminating the aforesaid time-varying error (δ=δ(t)) presents on the output analog signal. [0029] In order to overcome the drawbacks referred to above, numerous other DEM methodologies have been proposed that are able to eliminate the effects of the non-idealities of a DAC, the said methodologies being known in the literature as “Full/Partial Randomization”, “Barrel Shifting”, “Clocked Averaging”, etc. A fair share of these, however, are not to be held satisfactory for an integrated audio design; acceptable performance can in fact be reached only at the expense of a considerable theoretical and implementational complexity. [0030] Two methodologies which, instead, have appeared advantageous in the context of digital-to-analog power conversion are known in the literature as “Individual Level Averaging” (ILA) and “Data Weighted Averaging” (DWA). [0031] The basic idea behind the above two methodologies is guaranteeing erasure of the error on the DAC output whatever the pattern of the input signal, and this may be possible if, for each level of the output signal, all the generator elements available are activated in turn. As the number of levels of the output signal increases, the time averaging operation that is necessary for eliminating undesired high-frequency fluctuations becomes more precise. [0032] In particular, if for example an n-bit DAC for audio applications with an N-level balanced output is considered, i.e., a DAC able to supply at output an N-level analog signal with zero-averaging value, N/2 levels being positive and N/2 levels being negative, and the levels being symmetrical with respect to zero, the ILA methodology can be represented schematically as in FIGS. 4 and 5, which respectively regard the case where the input code X is positive and the case where the input code X is negative. [0033] In particular, as illustrated in FIGS. 4 and 5, ILA envisages: [0034] a) using N/2 positive generator elements (positive current generators) and N/2 negative generator elements (negative current generators) for the first audio channel (channel +) and as many positive and negative generator elements for the second channel (channel −); the said generator elements are represented in FIGS. 4 and 5 by squares designated with EU; [0035] b) attributing to the positive generator elements and to the negative generator elements of each audio channel the same progressive addresses; this type of indexing is represented schematically in FIGS. 4 and 5 by organizing, for each audio channel, the positive generator elements in a first vector, designated by V [0036] c) defining an index Ix for each input code X supplied to the DAC, with (−N/2+1)≦X≦N/2. [0037] Whenever an input code X appears on the input of the DAC, according to the sign of the input code X, for each of the two audio channels a set of X generator elements belonging to the vector V [0038] In particular, the same index Ix is applied both to the vector V [0039] In particular, if the input code X is positive, then, as illustrated in FIG. 4, a first set of X positive generator elements belonging to the vector V [0040] If, instead, the input code X is negative, then, as illustrated in FIG. 5, a first set of X negative generator elements belonging to the vector V [0041] The positive output Y [0042] Before the arrival of a new input code X at input to the DAC, the index I [0043] When an updating of the index I [0044] The same reasoning applies to the set of generator elements to be activated: if these go beyond the (N/2)-th generator element, the remaining generator elements are activated from the initial part of the vectors V [0045] According to the procedure for updating the index I [0046] The assessment of the efficacy of the above-mentioned two methodologies derives from the consideration that has led to the definition of ILA: within the said methodology, an algorithm is all the more satisfactory the shorter is the duration of its “erasure cycle”, i.e., the time interval that must elapse for the index I [0047] In RILA, the law of updating of each index I [0048] In AILA, instead, the law of updating of each index I [0049] The implementation of a dynamic matching algorithm based on ILA is via a state logic which exploits the theory of state diagrams or trellis diagrams, the index of complexity of which (and consequently of the algorithm represented thereby), which is equal to the number of states characterizing the trellis diagram itself, is found to be equal to (N−1) [0050] Such a high complexity inevitably leads to somewhat long erasure cycles, and hence to a far from effective modulation of the undesired spectral components present in the band, and this applies above all to RILA on account not only of the longer time interval required by the algorithm for activation of all the generator elements, but also on account of the fact that the indices are updated with a constant quantity. [0051] To reduce the circuit complexity of the logic implementing the dynamic matching algorithm, the aforementioned Data Weighted Averaging (DWA) methodology has been then proposed, the aim of which is to cause all the generator elements of the DAC to be activated in the shortest time possible, at the same time ensuring that each of them is activated the same number of times, even in short time intervals. [0052] In particular, DWA is a simplification of AILA obtained by drastically reducing the “degrees of freedom” defined by the high number of indices used (one for each input code X supplied to the DAC input). In particular, in DWA only one index is used, which is each time modified by the input code X, and this methodology envisages selecting, at each sampling instant, |X| consecutive generator elements starting from the first element not used at the preceding sampling instant. Consequently, in this methodology only one index is required, which is each time updated according to the relation I(t+1)=I(t)+|X|, which is very similar to the relation of AILA, but no longer contains a distinction between the indices according to the input code X. [0053] Erasure of the error is controlled exclusively by the pattern of the input code X, whence the name of the methodology. With a single index, moreover, the circuit complexity of the logic implementing this methodology, evaluated according to the same criteria as those used for evaluating the complexity of the RILA and AILA methodologies, proves to be equal to (N−1) [0054] Although DWA presents a circuit complexity decidedly lower than those of RILA and AILA and a decidedly good performance in terms of SINAD ratio both in the presence of positive input signals (ie., encoded with levels of between 0 and N−1) and in the presence of zero-averaging input signals (i.e., characterized by a high number of zero crossings) having a sufficiently high amplitude (greater than −30 dB), it, however, affords a performance that becomes noticeably poorer as the amplitude of the zero-average signals decreases. Consequently, its use does not make it possible to render the non-linearities of the two branches, the positive one and the negative one, of the transfer characteristic uncorrelated as the amplitude of the input signal varies, and hence does not make it possible to achieve a SINAD ratio acceptable for audio applications. [0055] The disclosed embodiments of the present invention provide a digital-to-analog conversion method that enables the drawbacks described above to be overcome at least in part, and in particular that provides a good behavior of the digital-to-analog converter even in the presence of zero-average signals characterized by frequent zero crossings and reduced amplitudes, this being a fundamental constraint for audio devices with differential output, and hence zero-averaging value. [0056] In accordance with one embodiment of the invention, a method for digital-to-analog conversion of a digital input code into a first and a second output analog signal to be supplied to a first terminal and a second terminal of a load, the conversion being performed by a digital-to-analog converter with an N-level balanced output is provided. The method includes providing N/2 positive generator elements that supply respective positive elementary contributions that are nominally equal to one another, and N/2 negative generator elements supplying respective negative elementary contributions that are nominally equal to one another and, in absolute value, equal to the positive elementary contributions; attributing the same progressive addresses to the positive generator elements and to the negative generator elements; defining a first index for positive input codes and a second index for negative input codes; and, in response to an input code at the input of the digital-to-analog converter: selecting, between the first and second index, the index corresponding to a sign of the input code; activating a first set of positive generator elements and a second set of negative generator elements, the number of negative and positive generator elements activated being equal to one another and a function of the input code, the addresses of the negative and positive generator elements activated being a function of the selected index; generating the first output analog signal as a function of the positive elementary contributions and generating the second output analog signal as a function of the negative elementary contributions; and updating the selected index according to the input code. [0057] For a better understanding of the present invention, a preferred embodiment thereof is now described, purely to provide a non-limiting example, with reference to the attached drawings, in which: [0058]FIG. 1 shows a block diagram of a digital-to-analog converter represented at the highest level of abstraction; [0059]FIG. 2 shows a first block diagram of a block of FIG. 1 which performs digital-to-analog conversion; [0060]FIG. 3 shows a second block diagram of the block of FIG. 1 which performs digital-to-analog conversion; [0061]FIGS. 4 and 5 are schematic representations of the methodology referred to as “Individual Level Averaging” according to the prior art; [0062]FIGS. 6 and 7 are schematic representations of the methodology referred to as “Differential Data Weighted Averaging” according to the present invention; [0063]FIG. 8 shows the logic necessary for implementation of “Differential Data Weighted Averaging”; [0064]FIG. 9 shows a different schematic representation of the methodology referred to as “Differential Data Weighted Averaging” according to the present invention; [0065]FIG. 10 shows the circuit structure of a positive generator element; [0066]FIG. 11 shows the circuit structure of a negative generator element; [0067]FIG. 12 shows the circuit structure of a bidirectional generator element; and [0068]FIG. 13 shows the circuit structure of a double changeover switch. [0069] The embodiments of the present invention relate to a new methodology of digital-to-analog conversion devised for digital-to-analog conversion systems with symmetrical characteristic (i.e., systems receiving zero-average input signals characterized by frequent zero crossings) and includes the use of a number of generator elements equal to one half of those used in the methodologies according to the prior art, the use of two indices, one for the positive input codes and one for the negative input codes, and the application of the Data Weighted Averaging (DWA) methodology separately to both the branches of the characteristic of the DAC. For this reason, then, the methodology according to the embodiments of the present invention has been given the name of Differential Data Weighted Averaging (DDWA). [0070] In particular, the DDWA methodology according to the embodiments of the present invention can be schematically represented as in FIGS. 6 and 7, which are directed to the case in which the input code X is positive and the case in which the input code X is negative. [0071] In particular, considering again an n-bit DAC for audio applications, i.e. a DAC with an N-level balanced output, N/2 levels being positive and N/2 levels being negative, DDWA basically includes: [0072] a) using a number of generator elements equal to one half of those used in DWA, namely, N/2 positive generator elements for the first audio channel (channel +) and N/2 negative generator elements for the second audio channel (channel −); [0073] b) attributing to the positive generator elements and to the negative generator elements the same progressive addresses; this type of indexing is represented schematically in FIGS. 6 and 7 in a way similar to what was represented in FIGS. 4 and 5, i.e., by organizing the positive generator elements in a first vector, designated by V [0074] c) defining a first index I [0075] Whenever an input code X, whether positive or negative, appears on the DAC input, a first set of X positive generator elements belonging to the vector V [0076] When the input code X is positive, each of the two sets of generator elements activated is formed by the generator elements comprised between the one having index I [0077] The positive elementary contributions supplied by the X positive generator elements activated are then added together, thus giving rise to a positive output Y [0078] The positive output Y [0079] In particular, the sign of the input code X is used for selectively controlling connection of the first output and of the second output to the first input and to the second input in the way described in what follows. If the sign of the input code X is positive, the first output is connected to the first input and the second output is connected to the second input; consequently, to the first audio channel (+) is applied the sum Y [0080] Updating of the indices is performed in a way similar to what was described previously for DWA, the updating each time being applied to the index selected by the input code X; namely, I [0081]FIG. 8 shows the logic required for implementing DDWA for a 6-bit (plus one sign bit) DAC, in which the sign sgn(X) of the input code X is used by a decoding stage [0082] DDWA makes it possible to combine the positive aspects of AILA and of DWA. In fact, the methodology according to this embodiment of the present invention has the capacity of erasing the error of the pattern of the input signal, provided that it is possible to have a sufficiently long waiting time, this being a characteristic of AILA, and at the same time guaranteeing the intrinsic speed of use of all the generator elements, this being a characteristic of DWA. [0083] From simulations performed by the present applicant, if a reconstructed signal occupying one half of the output dynamics of the DAC is considered, an evident improvement has emerged in the performance, in terms of audio quality, that DDWA method of the present invention enables to be obtained as compared to DWA. In particular, in addition to eliminating the harmonic components of the signal due to the non-linearity of the transfer characteristic, DDWA significantly reduces, by means of an appropriate modulation, the level of in-band noise, thus giving rise to SINAD and dynamic-range (DR) values at least 20 dB higher than those afforded by any other methodology in the conditions considered. [0084] The simulations performed by the applicant have moreover shown how the improvement is even more evident if, instead of considering a signal occupying one half of the dynamics, signals of a decidedly lower amplitude that are characterized by numerous zero crossings are considered. [0085] Further advantages afforded by DDWA are represented by the simplicity of the logic necessary for implementing the algorithm and by the fact that the number of generator elements (current generators) is, for differential-output systems, reduced by a factor of 2 as compared to the number required for implementing DWA. [0086] These advantages are, however, obtained at the expense of a slightly greater circuit complexity of the logic of activation of the generator elements as compared to that of DWA, in so far as two indices are used instead of a single one; in addition, as compared to the latter methodology, it is necessary to provide the double changeover switch and to introduce the decoding stage, which, however, is constituted by a simple NOT gate. [0087] The area occupied on the silicon is in any case very limited and decidedly less than that required for implementing all the other methodologies referred to above. [0088] It is moreover emphasized that the DDWA is undoubtedly the simplest methodology from the standpoint of implementation as compared to all the other methodologies analyzed, except for DWA alone, which, however, presents a considerably poorer performance for zero-average signals. [0089] It is further emphasized that in DDWA the elementary contributions extracted from the vectors V [0090]FIG. 9 is a schematic representation, similar to the representation of FIG. 6, of the DDWA methodology according to the embodiments of the present invention, where V designates the vector of the N/2 “bidirectional” generator elements, and “+” and “−” respectively designate the positive output and the negative output of each of them. [0091] According then to the sign of the input code X, X generator elements are selected starting from the one having index I [0092]FIGS. 10, 11, [0093] In particular, FIG. 10 shows a positive generator element, designated as a whole by [0094] Operation of the positive generator element is as follows: when the activation voltage V [0095]FIG. 11 shows the circuit structure of a negative generator element, designated as a whole by [0096] Operation of the negative generator element is as follows: when the activation voltage V [0097]FIG. 12 shows the circuit structure of a bidirectional generator element, designated as a whole by [0098] In detail, the PMOS transistors [0099] The NMOS transistors [0100] Operation of the bidirectional generator element [0101] Finally, FIG. 13 shows the circuit structure of a double changeover switch used in the implementation of the methodology according to the present invention. [0102] In particular, the double changeover switch, designated by [0103] In detail, the PMOS transistors [0104] The drain terminals of the PMOS transistor [0105] Operation of the double changeover switch [0106] Finally, it is evident that modifications and variations may be made to the matching method described and illustrated herein without thereby departing from the sphere of protection of the present invention as defined by the attached claims. [0107] For example, the addresses of the positive generator elements activated could even not be the same as those of the negative generator elements activated, even though the number of positive generator elements activated and the number of negative generator elements activated must necessarily remain equal to one another. In this case, however, it is no longer possible to “join” at a circuit level the N/2 positive generator elements to the N/2 corresponding negative generator elements to form the N/2 bidirectional generator elements. [0108] In addition, the number of positive generator elements activated and the number of negative generator elements activated could not be equal to the input code X, but more generally be a linear function of said code, and in particular be proportional to said code. [0109] From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims, and the equivalents thereof. Referenced by
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