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Publication numberUS20020076850 A1
Publication typeApplication
Application numberUS 09/740,249
Publication dateJun 20, 2002
Filing dateDec 19, 2000
Priority dateDec 19, 2000
Also published asUS6444545
Publication number09740249, 740249, US 2002/0076850 A1, US 2002/076850 A1, US 20020076850 A1, US 20020076850A1, US 2002076850 A1, US 2002076850A1, US-A1-20020076850, US-A1-2002076850, US2002/0076850A1, US2002/076850A1, US20020076850 A1, US20020076850A1, US2002076850 A1, US2002076850A1
InventorsMichael Sadd, Sucharita Madhukar, Frank Baker
Original AssigneeSadd Michael A., Sucharita Madhukar, Baker Frank Kelsey
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Device structure for storing charge and method therefore
US 20020076850 A1
Abstract
A semiconductor device structure for storing charge has a silicon nitride layer, in which a plurality of nanoclusters are sandwiched between oxide layers. The nanoclusters and the silicon nitride make up a storage region, which is particularly useful in non-volatile memories. The nanoclusters provide a repository for holes or electrons that jump from trap to trap in the silicon nitride when the silicon nitride is heated. This results in much of the charge, which would normally leak off from the silicon nitride at high temperatures, remaining in the storage region due to trapping in the nanoclusters. The silicon nitride layer with nanoclusters therein is formed by depositing a silicon nitride layer, then nanoclusters, and then another silicon nitride layer or by depositing a silicon-rich silicon nitride layer and subsequent heating to cause it to transform to a regular silicon nitride layer with silicon nanoclusters therein.
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Claims(43)
1. A semiconductor device structure for storing charge, comprising:
a substrate having a semiconductor surface;
a first dielectric layer over the substrate;
a nitride layer over the first dielectric layer wherein the nitride layer contains a plurality of nanoclusters capable of storing charge;
a second dielectric layer over the nitride layer; and
a conductive layer over the second dielectric layer.
2. The semiconductor device structure of claim 1, wherein the conductive layer comprises polysilicon.
3. The semiconductor device structure of claim 2, wherein the plurality of nanoclusters comprise silicon.
4. The semiconductor device structure of claim 1, wherein the nitride layer comprises:
a first thin silicon nitride layer;
a second thin silicon nitride layer; and
wherein the plurality of nanoclusters are on the first thin silicon nitride layer.
5. The semiconductor device structure of claim 4, wherein the first thin silicon nitride layer is thinner than the second thin silicon nitride layer.
6. The semiconductor device structure of claim 5, wherein the first dielectric layer is thinner than the second dielectric layer.
7. The semiconductor device structure of claim 6, wherein the plurality of nanoclusters are about 25-50 Angstroms in diameter.
8. The semiconductor device structure of claim 4, wherein the first thin silicon nitride layer has a thickness of about 10-50 Angstroms.
9. The semiconductor device structure of claim 8, wherein the second thin silicon nitride layer has a thickness of about 50-150 Angstroms.
10. The semiconductor device structure of claim 1, wherein the nitride layer has a thickness of about 75-150 Angstroms.
11. The semiconductor device structure of claim 1, wherein the first and second dielectric layers are silicon oxide.
12. The semiconductor device structure of claim 1, wherein the nitride layer is silicon nitride.
13. A method for making a semiconductor device structure for storing charge, comprising:
providing a substrate having a semiconductor surface;
forming a first silicon oxide layer over the semiconductor surface;
forming a silicon-rich silicon nitride layer over the first silicon oxide layer;
heating the silicon-rich silicon nitride layer to form nanoclusters;
forming a second silicon oxide layer after forming the silicon-rich silicon nitride layer; and
forming a conductive layer over the second silicon oxide layer.
14. The method of claim 13, wherein the conductive layer is polysilicon.
15. The method of claim 14, wherein the silicon-rich silicon nitride layer has a thickness of about 75-200 Angstroms.
16. The method of claim 15, wherein the first silicon oxide layer is thinner than the second silicon oxide layer.
17. The method of claim 13, wherein the first silicon oxide layer has a thickness of about 25 Angstroms.
18. The method of claim 13, wherein the silicon-rich silicon nitride layer has a percentage of excess silicon of at least 5 per cent.
19. The method of claim 18, wherein the percentage of excess silicon is about 10-20 per cent.
20. A method for making a semiconductor device structure for storing charge, comprising:
providing a substrate having a semiconductor surface;
forming a first dielectric layer over the semiconductor surface;
forming a first silicon nitride layer over the first dielectric layer;
forming a plurality of nanoclusters over the first silicon nitride layer;
forming a second silicon nitride layer over the first silicon nitride layer after the step of forming the plurality of nanoclusters; and
forming a conductive layer over the second silicon nitride layer.
21. The method of claim 20, further comprising forming a second dielectric layer over the second silicon nitride layer.
22. The method of claim 21, wherein the second dielectric layer is silicon oxide.
23. The method of claim 20, wherein the first dielectric layer is silicon oxide.
24. The method of claim 20, wherein the conductive layer is polysilicon.
25. The method of claim 20, wherein the plurality of nanoclusters are on the first silicon nitride layer.
26. The method of claim 21, wherein the first dielectric layer is thinner than the second dielectric layer.
27. The method of claim 26, wherein the first dielectric layer has a thickness of about 25 Angstroms.
28. The method of claim 20, wherein the plurality of nanoclusters has a density of at least 1011 nanoclusters per square centimeter.
29. A structure for storing charge comprising a layer of silicon nitride having a plurality of nanoclusters therein, wherein each of the plurality of nanoclusters has a diameter of less than 100 Angstroms and wherein the layer of silicon nitride has a thickness less than 300 Angstroms.
30. The structure of claim 29, wherein the layer of silicon nitride is about 100 Angstroms and the plurality of nanoclusters has a density of at least 1011 nanoclusters per square centimeter.
31. The structure of claim 30, further comprising a first layer of oxide and a second layer of oxide, wherein the layer of silicon nitride is between the first and second layers of oxide.
32. The structure of claim 31, further comprising a substrate having a semiconductor surface, wherein the layer of silicon nitride is over the semiconductor surface.
33. The structure of claim 32, further comprising a conductive layer over the layer of silicon nitride.
34. A method of making a charge storage device comprising:
forming a first silicon nitride layer;
forming nanoclusters on the first silicon nitride layer; and
forming a second silicon nitride layer on the nanoclusters.
35. The method of claim 34, wherein the first silicon nitride layer has a thickness less than 50 Angstroms.
36. The method of claim 35, wherein the second silicon nitride layer has thickness of about 75 Angstroms.
37. The method of claim 34, wherein the nanoclusters are less than 100 Angstroms in diameter.
38. The method of claim 34 further comprising:
forming a first silicon oxide layer, wherein the first silicon nitride layer is over the first silicon oxide layer;
forming a second silicon oxide layer over the second silicon nitride layer; and
forming a conductive layer over the second silicon oxide layer.
39. A method of making a charge storage device comprising:
forming a silicon-rich silicon nitride layer; and
heating the silicon-rich silicon nitride layer to form a silicon nitride layer with silicon nanoclusters contained therein.
40. The method of claim 39, wherein the silicon-rich silicon nitride layer has a percentage of excess silicon of at least 5 percent.
41. The method of claim 40, wherein the nanoclusters have a diameter of less than 100 Angstroms.
42. The method of claim 41, further comprising:
providing a substrate having a semiconductor surface;
forming a first oxide layer over the substrate and under the silicon-rich silicon nitride layer;
forming a second oxide layer after forming the silicon-rich silicon oxide layer; and
forming a conductive layer over the second oxide layer.
43. The method of claim 42, wherein the first oxide layer is thinner than the second oxide layer.
Description
FIELD OF THE INVENTION

[0001] The invention relates generally to semiconductor devices and more particularly to a semiconductor storage device and a process for forming such a semiconductor storage device.

RELATED ART

[0002] Electrically erasable programmable read only memory (EEPROM) structures are commonly used in integrated circuits for non-volatile data storage. As is known, EEPROM device structures commonly include a floating gate that has charge storage capabilities. Charge can be forced into the floating gate structure or removed from the floating gate structure using control voltages. The conductivity of the channel underlying the floating gate is significantly altered by the presence of charges stored in the floating gate. The difference in conductivity due to a charged or uncharged floating gate can be current sensed, thus allowing binary memory states to be determined. The conductivity difference is also represented by a shift in the threshold voltage (Vt) associated with the device in the two different states.

[0003] As semiconductor devices continue to evolve, the operating voltages of such semiconductor devices are often reduced in order to suit low power applications. It is desirable for such operating voltage reductions to be accomplished while ensuring that the speed and functionality of the devices is maintained or improved.

[0004] One EEPROM device, which operates at lower operating voltages than a continuous floating gate device, uses a silicon-oxide-nitride-oxide-silicon (SONOS) structure, in which charge is stored in the nitride layer. Another advantage of SONOS over the continuous floating gate device is the ease of processing due to its simpler layer structure. In a SONOS structure, charge is forced from the substrate through the tunnel oxide into the nitride, which acts as a trapping layer. The trapping layer in SONOS is equivalent to the floating gate of other EEPROM devices. One problem that exists with the SONOS structure is that at temperatures greater than or equal to room temperature, the charge retention of the trapping layer can be a problem. The energy levels of the nitride traps are not deep enough to prevent, over the expected lifetime of the device, charge from thermally exciting into the nitride conduction band, then tunneling to the substrate layer through the first oxide (tunnel oxide). Hence, the charge retention and reliability of this structure is diminished. Therefore a need exists for a SONOS structure with a higher reliability, especially at temperatures equal to or greater than room temperature.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:

[0006] FIGS. 1-4 illustrate a cross-sectional view of an improved SONOS structure according to the present invention;

[0007] FIGS. 5-8 illustrate a cross-sectional view of an alternate embodiment of the improved SONOS structure according to the present invention;

[0008]FIG. 9 illustrates a band diagram of the traditional SONOS structure during charge retention; and

[0009]FIG. 10 illustrates a band diagram of the improved SONOS structure according to the present invention during charge retention.

[0010] Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.

DETAILED DESCRIPTION

[0011] Generally, the present invention pertains to a semiconductor memory device with a trapping layer that includes a plurality of nanoclusters or discrete storage elements and techniques useful in the manufacturing of such a device. By including a plurality of nanoclusters in the trapping layer of traditional SONOS, there is an improvement in charge retention, reliability characteristics and write/erase times. (As used herein, the term “traditional SONOS” is used to define the SONOS structure without nanoclusters.) In one embodiment, the nanoclusters are deposited on a nitride layer. In another embodiment, the nanoclusters are nucleated from the nitride layer. The invention can be better understood with references to FIGS. 1-10.

[0012] Turning to FIG. 1, the improved SONOS device is formed on a substrate 10. Substrate 10 typically is a single crystal silicon or other semiconductive material, such as GaAs. Alternatively, substrate 10 may be a silicon-on-insulator (SOI). In each case, a top surface of substrate 10 will be a semiconductor material. Over substrate 10 a tunnel oxide layer or first oxide layer 20 is formed. Typically, first oxide layer 20 is SiO2. First oxide layer 20 can also be aluminum oxide, nitrided SiO2, any other dielectric material or tunneling barrier material. First oxide layer 20 is typically formed by thermal growth. However, any other known method for forming dielectric materials can be used, such as CVD, PVD, combinations thereof, or the like. A first nitride layer 30 is formed over first oxide layer 20. Typically, first nitride layer 30 is deposited by using CVD, PVD, combinations thereof and the like. First nitride layer 30 is typically silicon nitride. First nitride layer 30 preferably has a thickness less than 50 Angstroms. Nanoclusters 40 are formed on first nitride layer 30, as shown in FIG. 1. Nanoclusters are preferably nanocrystals of silicon, however another suitable semiconductor material can be used. In addition, it is possible that the nanoclusters are amorphous. Nanoclusters 40 can be deposited through a controlled LPCVD, RTCVD or UHCVD process. Through these processes the density of nanoclusters 40 can be closely controlled. In embodiments utilizing LPCVD or RTCVD techniques a multi-step process may be utilized to ensure proper nucleation and growth selectivity for different phases of the nanocluster formation. As such, desired nanocluster densities can be achieved while ensuring uniformity in size and density in a manufacturable process. In embodiments where UHVCVD is utilized to grow the nanoclusters 40, additional advantages are achieved due to the reduction of background contamination in the environment within which the nanoclusters 40 formation occurs. Similar optimizations to the formation of the nanoclusters that were utilized in LPCVD techniques can be employed in UHVCVD techniques to produce the desired resulting nanoclusters 40. In UHVCVD techniques even lower pressures than those present in LPCVD techniques can provide a further reduction in growth kinetics such that a higher level control is obtained over the nanocluster formation. Furthermore, potential gradients in nanocluster growth rates due to precursor gas depletion effects are further minimized. Preferably, the nanoclusters 40 are approximately less than 100 Angstroms in the diameter. (For purposes of this specification, the nanocluster diameter is defined as the largest width of the nanocluster.) More preferably, they are approximately 35-50 Angstroms in diameter. As schematically shown in FIGS. 1-4, the nanoclusters 40 are usually approximately hemispherical in shape due to the deposition process. Thus, the nanoclusters 40, generally, have a height that is approximately half of their diameter. The density of nanoclusters 40 is at least 1011 nanoclusters per square centimeter. Using any of the above methods will result in the nanoclusters that are deposited during the same process, being substantially in the same row.

[0013] As shown in FIG. 2, a second nitride layer 50 is formed over nanoclusters 40 and the first nitride layer 30. Typically the second nitride layer 50 is silicon nitride. However, another material with a large density of isolated charge trapping centers can be used. In one embodiment, the first and second nitride layers (30 and 50) are the same material. The same processes used to form the first nitride layer 30 can also be used to form the second nitride layer 50. The sum of the first nitride layer 30 and the second nitride layer 50 is less than 300 Angstroms. Preferably, the first and second nitride layers (30 and 50) are between 50 and 300 Angstroms and more preferably between 75 to 150 Angstroms. The thickness of the nitride layers (30 and 50) cannot be too thick, or else the total voltage required to write or erase the device will increase to an undesirable level. This will increase the time required to write or erase the device. The thickness of the nitride layers (30 and 50) cannot be too thin as not to allow for enough charge to be stored in structure. In one embodiment both the first nitride layer 30 and the second nitride layer 50 will be 75 Angstroms. In another embodiment, the first nitride layer 30 will be less than 50 Angstroms and preferably between 10 to 50 Angstroms. The second nitride layer 50 will be between 50 and 150 Angstroms and preferably approximately 75 Angstroms. In the embodiments where first nitride layer 30 is thinner than second nitride layer 50, the nanoclusters 40 will be closer to the tunnel oxide layer 20. This will increase the speed of writing electrons to the structure relative to the case where the second nitride layer 50 thinner than the first nitride layer 30. Charge retention, however, will be better in the latter case. To see an improvement over traditional SONOS in write and erase speeds, the first nitride layer 50 should be less than 50 to 75 Angstroms. Charge retention will still improve when the first layer is 10 to 30 Angstroms or more.

[0014] In one embodiment, after forming the second nitride layer 50, a second row of nanoclusters (not shown) would be deposited over the second row of nanoclusters. In such cases, a third nitride layer (not shown) can be formed. Further multiple layers can be formed in such a manner, if desired. However, in general it is desirable for the overall nitride thickness not to exceed about 50-300 Angstroms. The benefit of a thicker overall nitride and additional nanoclusters is increased charge storage. The disadvantage is an increase in the voltage required for program and erase.

[0015] Turning to FIG. 3, the second oxide layer 60 is formed on the nitride layer 50. The second oxide layer 60 is preferably a SiO2 layer, but may be any other suitable dielectric material as well, such as aluminum oxide, nitrided SiO2, or a metal oxide. The second oxide layer 60 can be thermally grown or deposited by CVD, PVD, combinations thereof, or the like. First oxide layer 20 and second oxide layer 60 can be the same or different materials. Second oxide layer 60 is typically 40-50 Angstroms in thickness.

[0016] On the second oxide layer 60 a conductive layer 70 is formed, as shown in FIG. 4. Typically conductive layer 70 will be a polycrystalline silicon layer. However, any other conductive material, such as a metal, metal alloy and the like, can be used. The conductive layer 70 is typically at least 1000 Angstroms in thickness if it is polycrystalline silicon. Any known method for depositing a conductive material can be used such as CVD, PVD, combinations thereof and the like.

[0017] Another method for forming the improved SONOS structure will be described with references to FIGS. 5-8. In FIG. 5, the substrate 10 and the first oxide layer 20 are formed as previously discussed in the alternate embodiment. The same materials and thicknesses are used as previously discussed. Over the first oxide layer 20, a silicon-rich nitride layer 35 is formed. Preferably, the silicon-rich nitride layer 35 has a thickness between 75 to 200 Angstroms, and more preferably approximately 100 Angstroms. The silicon-rich nitride layer 35 should have at least 5% of excess silicon and preferably will have 10-20% excess silicon. Excess silicon is used herein to describe the amount of silicon that is present beyond the amount of silicon that is present in stoichiometric silicon nitride (Si3N4). Next, the silicon rich nitride layer is annealed in a thermal furnace at a temperature of approximately 600-1000 degrees Celsius. The annealing causes silicon precipitates to form in the silicon nitride layer 35. Through nucleation and growth, the precipitates will develop into approximately spherical silicon nanoclusters 32, as shown in FIG. 6. Typically the nanoclusters 32 are approximately less than 100 Angstroms in diameter. More typically they are approximately 35-50 Angstroms. The density of nanoclusters 32 is at least 1011 nanoclusters per square centimeter. Due to the processing, the nanoclusters 35 will be scattered throughout the silicon nitride layer 35 instead of forming rows as was described in the previous embodiment.

[0018] Turning to FIG. 7, the second oxide layer 60 is formed as was previously discussed in an alternate embodiment. However, the anneal previously discussed for forming the silicon precipitates does not have to be performed prior to forming the second oxide layer 60. Instead, the anneal can be performed after the formation of second oxide layer 60. As shown in FIG. 8, a conductive layer 70 is formed over second oxide layer 60.

[0019]FIG. 9 shows an energy band diagram of the traditional SONOS structure. Element 80 is the substrate. Element 90 is the first oxide layer. Element 100 is the nitride layer. Element 110 is the second oxide layer and element 120 is the gate or conductive material. This figure shows the SONOS structure in the high Vt state. The high Vt state is the state of the device after electrons have been trapped in the nitride layer. The x-axis is the distance along the SONOS stack from within the silicon substrate. The y-axis is an energy level expressed in electron volts (eV). Electron 200 is in a trap level or trap state in the nitride layer 100. This trapping level is at a lower energy level than the conduction band of the nitride 100. If electron 200 is thermally excited, the electron may move from one trap state to another trap state, which is at the same energy level. However, more typically, the electron 200 will move from the trapping level to the conduction band of the nitride layer when thermally excited. The electron can then travel to the nitride 100 and first oxide layer 90 interface. The electron 200 can then tunnel through the first oxide layer 90 to the substrate layer 80. This tunneling phenomenon in the SONOS structure is undesirable because it reduces the reliability and charge retention of the device.

[0020]FIG. 10 is an energy band diagram of the improved SONOS structure. Like the traditional SONOS energy band diagram in FIG. 9, there is a substrate layer 80, a first oxide layer 90, a second oxide layer 110 and a gate or conductive layer 120. However, in FIG. 10 there are two nitride layers. The first nitride layer 105 is below the nanoclusters in the SONOS stack and second nitride layer 109 is above the nanoclusters 210 in the SONOS stack. When thermally excited, electron 200 may tunnel from trap to trap in either nitride layer 109 or 105. More typically, electron 200, when thermally excited, will travel from the trap levels in the nitride layers 105 or 109 to the conduction bands of the nitride layers 105 and 109. Due to scattering in the nitride, the electron 200 may lose energy, then fall into a nanocluster 210. Because of the depth of the energy well introduced by the nanocluster, the rate of thermal activation into the conduction band is greatly reduced in comparison to the traditional structure in FIG. 9. Hence, the charge retention and reliability of the improved SONOS structure is superior to the traditional SONOS structure.

[0021]FIGS. 9 and 10 explain the charge retention characteristics of the SONOS structure and improved SONOS structure in regards to electrons. However, skilled artisans would appreciate that the same processes can be shown in regards to holes. However, the explanation will be with respect to the valence band of the SONOS stacks, as opposed to the conduction band as described above.

[0022] The improved SONOS stack also has the advantage of improving the process of writing holes, which will be referred to as erasing. During erasing, the traditional SONOS stack has the disadvantage that the excess of positive charge over negative charge that can be stored in the trapping layer is limited by the electron injection from the gate electrode. This problem is solved by the improved SONOS structure. When erasing with the improved SONOS structure, nanoclusters near the interface act as intermediate states. In the improved SONOS structure , the intermediate states increase the tunneling rate of holes from the substrate with respect to the tunneling rate of electrons from the conductive layer in comparison to these same relative rates in the traditional SONOS structure. This improved hole tunneling rate with respect to electron tunneling rate is due to the increase in the number of allowed states in the SONOS structure caused by the presence of nanoclusters. This improvement is also due to better energy alignment of the band diagram of the materials in the SONOS stack. Due to the increase in allowed energy states, the rate of writing holes to the improved SONOS stack is increased compared to the traditional SONOS stack under the same bias conditions. Alternately, the voltage can be decreased during erasing and this will keep the speed unchanged between traditional and improved SONOS stacks. The increase in allowed energy states also improves the write or writing of electron speed in the improved SONOS stack. Alternately, the advantage of decreasing the voltage for writing electrons in the improved SONOS stack can be performed.

[0023] Although writing, erasing and charge retention has been described with respect to a specific charge types (electrons/holes), skilled artisans appreciated that writing, erasing and charge retention can be expressed in terms of the other charge type (electrons/holes) instead.

[0024] In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.

[0025] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6567292Jun 28, 2002May 20, 2003Progressant Technologies, Inc.Negative differential resistance (NDR) element and memory with reduced soft error rate
US6727548Nov 18, 2002Apr 27, 2004Progressant Technologies, Inc.Negative differential resistance (NDR) element and memory with reduced soft error rate
US6795337Jun 28, 2002Sep 21, 2004Progressant Technologies, Inc.Negative differential resistance (NDR) elements and memory device using the same
US6812084Dec 17, 2002Nov 2, 2004Progressant Technologies, Inc.Adaptive negative differential resistance device
US6847562Jun 28, 2002Jan 25, 2005Progressant Technologies, Inc.Enhanced read and write methods for negative differential resistance (NDR) based memory device
US6849483Dec 9, 2002Feb 1, 2005Progressant Technologies, Inc.Charge trapping device and method of forming the same
US6853035Apr 26, 2004Feb 8, 2005Synopsys, Inc.Negative differential resistance (NDR) memory device with reduced soft error rate
US6861707Apr 26, 2004Mar 1, 2005Progressant Technologies, Inc.Negative differential resistance (NDR) memory cell with reduced soft error rate
US6864104Aug 8, 2002Mar 8, 2005Progressant Technologies, Inc.Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects
US6912151Jun 28, 2002Jun 28, 2005Synopsys, Inc.Negative differential resistance (NDR) based memory device with reduced body effects
US6955967 *Jun 27, 2003Oct 18, 2005Freescale Semiconductor, Inc.Non-volatile memory having a reference transistor and method for forming
US6969883 *Sep 27, 2004Nov 29, 2005Freescale Semiconductor, Inc.Non-volatile memory having a reference transistor
US6979580Dec 9, 2002Dec 27, 2005Progressant Technologies, Inc.Process for controlling performance characteristics of a negative differential resistance (NDR) device
US6980467Dec 9, 2002Dec 27, 2005Progressant Technologies, Inc.Method of forming a negative differential resistance device
US6990016Jul 2, 2004Jan 24, 2006Progressant Technologies, Inc.Method of making memory cell utilizing negative differential resistance devices
US7005711Dec 20, 2002Feb 28, 2006Progressant Technologies, Inc.N-channel pull-up element and logic circuit
US7012833Dec 17, 2002Mar 14, 2006Progressant Technologies, Inc.Integrated circuit having negative differential resistance (NDR) devices with varied peak-to-valley ratios (PVRs)
US7012842Dec 9, 2004Mar 14, 2006Progressant Technologies, Inc.Enhanced read and write methods for negative differential resistance (NDR) based memory device
US7015536Nov 4, 2004Mar 21, 2006Progressant Technologies, Inc.Charge trapping device and method of forming the same
US7016224Jul 2, 2004Mar 21, 2006Tsu-Jae KingTwo terminal silicon based negative differential resistance device
US7042045 *Jun 4, 2002May 9, 2006Samsung Electronics Co., Ltd.Non-volatile memory cell having a silicon-oxide nitride-oxide-silicon gate structure
US7060524Oct 15, 2004Jun 13, 2006Progressant Technologies, Inc.Methods of testing/stressing a charge trapping device
US7095659Oct 3, 2005Aug 22, 2006Progressant Technologies, Inc.Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device
US7098472Sep 15, 2005Aug 29, 2006Progressant Technologies, Inc.Negative differential resistance (NDR) elements and memory device using the same
US7113423Jan 28, 2005Sep 26, 2006Progressant Technologies, Inc.Method of forming a negative differential resistance device
US7186621Jan 28, 2005Mar 6, 2007Progressant Technologies, Inc.Method of forming a negative differential resistance device
US7187028Jan 13, 2005Mar 6, 2007Synopsys, Inc.Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects
US7220636Nov 4, 2004May 22, 2007Synopsys, Inc.Process for controlling performance characteristics of a negative differential resistance (NDR) device
US7221018 *Feb 10, 2004May 22, 2007Micron Technology, Inc.NROM flash memory with a high-permittivity gate dielectric
US7250653May 20, 2004Jul 31, 2007Samsung Electronics Co., Ltd.SONOS memory device having nano-sized trap elements
US7254050Nov 1, 2004Aug 7, 2007Synopsys, Inc.Method of making adaptive negative differential resistance device
US7265410 *Feb 16, 2006Sep 4, 2007Samsung Electronics Co., Ltd.Non-volatile memory cell having a silicon-oxide-nitride-oxide-silicon gate structure and fabrication method of such cell
US7550802Jan 12, 2005Jun 23, 2009Asahi Glass Company, LimitedNonvolatile semiconductor memory device and manufacturing process of the same
US7557009Apr 4, 2007Jul 7, 2009Synopsys, Inc.Process for controlling performance characteristics of a negative differential resistance (NDR) device
US7829938Jul 14, 2005Nov 9, 2010Micron Technology, Inc.High density NAND non-volatile memory device
US7851827Jul 22, 2008Dec 14, 2010Micron Technology, Inc.Back-side trapped non-volatile memory device
US7932189 *Jan 26, 2007Apr 26, 2011Freescale Semiconductor, Inc.Process of forming an electronic device including a layer of discontinuous storage elements
US8058118Nov 30, 2010Nov 15, 2011Micron Technology, Inc.Methods of forming and operating back-side trap non-volatile memory cells
US8093648 *Jul 10, 2009Jan 10, 2012Au Optronics Corp.Method for manufacturing non-volatile memory and structure thereof
US8462557Nov 8, 2010Jun 11, 2013Micron Technology, Inc.Methods of operating memory cell having asymmetric band-gap tunnel insulator using direct tunneling
US20120262985 *Apr 12, 2011Oct 18, 2012Globalfoundries Singapore Pte. Ltd.Mulit-bit cell
EP1480275A2 *May 19, 2004Nov 24, 2004Samsung Electronics Co., Ltd.SONOS memory device having nanocrystal layer
EP1536483A1 *Jul 23, 2003Jun 1, 2005Asahi Glass Company Ltd.Nonvolatile semiconductor storage device and manufacturing method
EP1571702A2 *Mar 4, 2005Sep 7, 2005Samsung Electronics Co., Ltd.Method of manufacturing memory device comprising gate having uniformly distributed silicon nano dots
WO2007011582A2 *Jul 12, 2006Jan 25, 2007Micron Technology IncHigh density nand non-volatile memory device
Classifications
U.S. Classification438/90, 257/E21.21, 257/E21.209
International ClassificationH01L29/423, H01L21/20, H01L21/28, H01L21/00
Cooperative ClassificationH01L21/28282, B82Y10/00, H01L29/42332, H01L21/28273
European ClassificationB82Y10/00, H01L21/28G, H01L29/423D2B2C, H01L21/28F
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Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129
Effective date: 20061201
Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129D
Owner name: CITIBANK, N.A. AS COLLATERAL AGENT,NEW YORK
Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP. AND OTHERS;US-ASSIGNMENT DATABASE UPDATED:20100525;REEL/FRAME:18855/129
Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP. AND OTHERS;REEL/FRAME:18855/129
Feb 28, 2006FPAYFee payment
Year of fee payment: 4
May 7, 2004ASAssignment
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657
Effective date: 20040404
Owner name: FREESCALE SEMICONDUCTOR, INC. 6501 WILLIAM CANNON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC. /AR;REEL/FRAME:015698/0657
Owner name: FREESCALE SEMICONDUCTOR, INC.,TEXAS
Dec 19, 2000ASAssignment
Owner name: MOTOROLA, INC., ILLINOIS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SADD, MICHAEL A.;MADHUKAR, SUCHARITA;BAKER, FRANK KELSEY;REEL/FRAME:011392/0859
Effective date: 20001219
Owner name: MOTOROLA, INC. INTELLECTUAL PROPERTY DEPT. 1303 EA