US 20020080860 A1 Abstract A correlator and matched filter for use with coded transmission, such as CDMA, form new codes from the sums and differences of the original codes, where only one of the new codes is non-zero for each element position and effect hardware savings using the new codes.
Claims(28) 1. A method of despreading an input signal spread with two original codes, comprising
forming two new multi-element codes from the two original codes such that only one of the corresponding elements of each code is zero; combining the new codes with the input signal by
forming partial results for each of the new codes, and
updating, for each element, the partial result corresponding to the new code for which the corresponding element is not zero; and
combining the partial results to form correlation values.
2. The method of taking one-half the sum of the original codes, and taking one-half the difference between the original codes. 3. The method of providing an XOR operation between the input signal and the new codes. 4. The method of adding the input signal to one of two partial sums according to the sign of the input signal. 5. The method of adding a new value to a previous partial result. 6. The method of forming a sum and a difference of the partial results. 7. A system for despreading an input signal spread with two original codes by forming two new multi-element codes from the two original codes such that only one of the corresponding elements of each code is zero, comprising:
first adder means for combining the new codes with the input signal including
means for forming partial results for each of the new codes, and
means for updating, for each element, the partial result corresponding to the new code for which the corresponding element is not zero; and
adder subtractor means for combining the partial results to form correlation values.
8. The system of one-half the sum of the original codes, and one-half the difference between the original codes. 9. The system of an XOR gate. 10. The system of a pair of adders, each corresponding to a different sign of the input signal. 11. The system of an adder. 12. The system of an adder, and a subtractor. 13. A dual-code correlator coupled to an input signal and a pair of multi-element codes designed such that only one of the corresponding elements of each code is zero, the correlator comprising
a decoder element receiving the input signal and the codes; an adder coupled to the output of the decoder element and a register bank containing partial results; and an adder/subtractor circuit to form correlation results from the partial results. 14. The correlator of first and second registers each corresponding to a different one of the codes; and wherein the correlator further includes
a demultiplexer coupled between the output of the adder and the inputs of the first and second registers to direct the output of the adder to one of the first and second registers according to a select signal, and
a multiplexer coupled between the outputs of the first and second registers and an input of the adder to direct the output of one of the first and second registers to the input of the adder according to the select signal; and
wherein the select signal indicates the one of the codes for which the current element is not zero.
15. The correlator of first and second registers each corresponding to a different one of the codes; and wherein the correlator further includes
a control circuit generating a first gated clock signal to direct the output of the adder to one of the first and second registers according to a select signal, and a second gated clock signal to direct the output of one of the first and second registers to the input of the adder according to the select signal.
16. The correlator of third and fourth registers coupled between the first and second registers, respectively, and the adder/subtractor circuit. 17. The correlator of an XOR gate. 18. A dual code correlator coupled to an input signal and a pair of multi-element codes designed such that only one of the corresponding elements of each code is zero, the correlator comprising
an adder circuit receiving the input signal and a partial result; a register bank containing a plurality of partial results; steering circuits for directing the output of the adder circuit to the register circuit and for directing the appropriate one of the partial results to the adder circuit; and an adder/subtractor circuit to form correlation results from the partial results. 19. The correlator of first, second, third, and fourth registers each corresponding to a different combination of the codes and the sign of the input signal; and wherein the steering circuits includes
an auxiliary demultiplexer circuit coupled between the output of the adder and the inputs of the first, second, third, and fourth registers to direct the output of the adder to one of the first, second, third, and fourth registers according to a select signal, and
a multiplexer circuit coupled between the outputs of the first, second, third, and fourth registers and an input of the adder to direct the output of one of the first, second, third, and fourth registers to the input of the adder according to the select signal; and
wherein the select signal corresponds to different combination of the codes and the sign of the input signal.
20. The correlator of first, second, third, and fourth registers each corresponding to a different combination of the codes and the sign of the input signal; and wherein the steering circuits includes
a control signal to generate a first gated clock signal to direct the output of the adder to one of the first, second, third, and fourth registers according to a select signal, and a second gated clock signal to direct the output of one of the first, second, third, and fourth registers to the input of the adder according to the select signal.
21. The correlator of the adder circuit includes a positive adder for adding positive values of the input signal and a negative adder for adding negative values of the input signal, wherein the demultiplexer circuit includes
a demultiplexer circuit coupled between the first, second, third, and fourth registers and the single adder; and
wherein the multiplexer circuit includes
a multiplexer circuit coupled between the first, second, third, and fourth registers and the single adder.
22. The correlator of wherein the demultiplexer circuit includes
a first demultiplexer coupled between the positive adder and the first and second registers, and
a second demultiplexer coupled between the negative adder and the third and fourth registers; and
wherein the multiplexer circuit includes
a first demultiplexer coupled between the first and second registers and the positive adder, and
a second demultiplexer coupled between the third and fourth registers and the negative adder.
23. The correlator of fifth, sixth, seventh, and eighth registers coupled between the adder/subtractor circuit and the first, second, third, and fourth registers, respectively. 24. The correlator of an adder; and a subtractor. 25. A matched filter comprising
a plurality of filter stages connected sequentially, each of the stages including
an adder receiving an input signal and an output from a previous stage, the first of the stages in the sequence receiving a fixed input, and
a register bank to hold the output of the adder as an output of that stage; and
an adder/subtractor circuit connected to the outputs of the last of the filter stages in the sequence for forming the filter output.
26. The filter of a register to hold the input signal. 27. The filter of two results registers. 26. The filter of an adder; and a subtractor. Description [0001] This application relates to an application by the same inventors entitled “A Low Complexity Correlator for Multi-code CDMA” filed on the same date as this application, and incorporated herein by reference. [0002] This invention relates generally to despreaders, and more particularly to a dual-code despreader that can despread pseudonoise (PN) sequences used for Code Division Multiple Access (CDMA) systems. [0003] The growing importance of wireless communications has increased the demand for data transmission over mobile radio channels. Although GSM standards have become very popular and data service specifications are developing, most current mobile communications still use CDMA technologies. Future multimedia transmission, however, will require wide bandwidths and high data rates, which in turn will require complex and expensive hardware. [0004] CDMA systems use a PN sequence to “spread” input data to resist data loss in a noisy wireless environment. The transmitted baseband signal is expressed as
[0005] where b [0006] Receivers must despread the received signal back into an original input symbol by correlating the received signal with the same PN code C [0007] The Sign function outputs a 1 if the input is positive and a −1 if the input is negative. [0008] Generally, [0009] where n represents the noise from the environment. Combining equations (1), (2), and (3) yields:
[0010] For orthogonal codes, [0011] Also, noise n is small compared with an original signal, and [0012] where m is the spreading factor. [0013] Because b [0014] In addition to the noise signal, other user data can be regarded as another source of interference for CDMA systems. [0015] Modern CDMA systems use either different orthogonal codes or the same code with different delays. This requires hardware that can despread several codes concurrently. Some researchers have tried to increase throughput by adding two PN sequences as the code input, with the two sequences coming from the same code with different delays. [0016] Another system to reduce power consumption uses sign-magnitude data format and two accumulators for positive and negative partial sums, respectively, with a specialized architecture. None of these systems, however, provides a complete solution to future problems facing CDMA systems. [0017] A method, consistent with this invention, of despreading an input signal spread with two original codes, comprises forming two new multi-element codes from the two original codes such that only one of the corresponding elements of each code is zero, combining the new codes with the input signal, and combining the partial results to form correlation values. Combining the new codes involves forming partial results for each of the new codes, and updating, for each element, the partial result corresponding to the new code for which the corresponding element is not zero. [0018] A system, consistent with this invention, for despreading an input signal spread with two original codes involves forming two new multi-element codes from the two original codes such that only one of the corresponding elements of each code is zero. The apparatus comprises first adder means for combining the new codes with the input signal, and adder subtractor means for combining the partial results to form correlation values. The first adder means includes means for forming partial results for each of the new codes, and means for updating, for each element, the partial result corresponding to the new code for which the corresponding element is not zero. [0019] A dual-code correlator, consistent with this invention, is coupled to an input signal and a pair of multi-element codes designed such that only one of the corresponding elements of each code is zero, and comprises a decoder element receiving the input signal and the codes, an adder coupled to the output of the decoder element and a register bank containing partial results, and an adder/subtractor circuit to form correlation results from the partial results. [0020] Another dual code correlator, consistent with this invention, is coupled to an input signal and a pair of multi-element codes designed such that only one of the corresponding elements of each code is zero, and comprises an adder circuit receiving the input signal and a partial result, a register bank containing a plurality of partial results, steering circuits for directing the output of the adder circuit to the register circuit and for directing the appropriate one of the partial results to the adder circuit, and an adder/subtractor circuit to form correlation results from the partial results. [0021] A matched filter, consistent with this invention, comprises a plurality of filter stages connected sequentially, and an adder/subtractor circuit connected to the outputs of the last of the filter stages in the sequence for forming the filter output. Each of the stages includes an adder receiving an input signal and an output from a previous stage, the first of the stages in the sequence receiving a fixed input, and a register bank to hold the output of the adder as an output of that stage. [0022] Both the foregoing general description and the following detailed description are exemplary and do not restrict the invention claimed. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate systems and methods consistent with the invention and, together with the description, explain the principles of the invention. [0023] In the drawings, [0024]FIG. 1 is a flow diagram of the operations for despreading consistent with this invention; [0025]FIG. 2 is a block diagram of a system, consistent with this invention, for a two's-complement representation of input signals; [0026]FIGS. 3A and 3B are block diagrams of systems consistent with the invention for signals in sign-magnitude representation of input signals; [0027]FIG. 4 is a block diagram of dual-code, chip-matched filter consistent with this invention; [0028]FIG. 5 is a block diagram of standard design of a correlator for purposes of comparing the complexity of conventional designs with systems consistent with this invention; and [0029]FIG. 6 is a block diagram of a standard design of a matched filter for purposes of comparing the complexity of conventional designs with systems consistent with this invention. [0030] A. Principles of Operation [0031] 1. Dual Code Despreading [0032] Systems and methods consistent with the present invention generate two new codes from two original PN codes that can be orthogonal or the same with different delays. Proper use of the new codes allows the correlator hardware to be designed with fewer elements and greater speed. [0033] The two new codes are generated from the original codes C [0034] The elements of C [0035] and [0036] If the transmitted signals include data from two users then: [0037] To simplify the process, assume noise is zero or negligible. As a result, correlating this signal with the redesigned new codes yields: [0038] Similarly, [0039] Therefore, the following results can be obtained by addition: [0040] The total number of computations for C [0041] 2. Despreading Process [0042]FIG. 1 is a flow diagram [0043] 3. Examples [0044] To demonstrate the equivalence of the new codes to the original codes, assume the two original codes are Walsh codes, [1−1 1−1] [1 0 0−1][4−2 3−3] [0−1 1 0][4−2 3−3] [0045] The operations for multiply and accumulate are the same as for single code despreading, so the correct correlation values can be obtained as (7+5)=12 and (7−5)=2 [0046] To verify the accuracies of these results, the conventional approach yields the same results: [1−1 1−1][4−2 3−3] [0047] B. Hardware Implementations [0048] 1. Two's-Complement Representation [0049]FIG. 2 shows a system [0050] System [0051] System [0052] In addition, the dynamic range of the adder can be reduced. This is because the non-zero portions of the sum or difference of orthogonal PN sequences are about half their length due to the nature of PN sequences and orthogonality. [0053] 2. Sign-Magnitude Representation [0054] A system consistent with this invention that can provide a lower power design uses sign-magnitude representation. Such a representation generally has fewer transitions between states, which will consume less power in most CMOS implementations. One known architecture reduces the power consumption of the receiver using two correlators, one for positive values and the other for negative values. That architecture can be adapted for use with the two new codes to provide improved receivers. [0055]FIG. 3A shows a system [0056] With regard to these elements, the sign magnitude implementation in FIG. 3A resembles the two's-complement circuits from FIG. 2 if one circuit is used for positive values and one circuit is used for negative values. Again, only two adders are needed because the value of one of the codes will always be 0. [0057] The final elements of system [0058]FIG. 3B shows a similar system [0059] Alternatively, a gated clock can also be applied to control the data flow and reduce power consumption. The dynamic range of elements [0060] 3. Chip-Matched Filter Architecture [0061] The use of two codes can also be applied to a chip-matched filter design. FIG. 4 shows one possible architecture for dual-code, chip-matched filter [0062] Filter [0063] Both two's-complement and sign-magnitude representations are possible, but only the two's-complement result is shown. Bit-serial techniques cannot be applied to the final adder/subtractor due to the pipelined constraint. [0064] C. Complexity Analysis [0065] Table 1 contains a hardware complexity analysis. Each heading, except the first and last, identifies the type of component used in the associated circuit, and the number in parentheses represents the number of transistor gates for the component. The numbers in the columns represent the number of gates needed for 1-bit implementation. The design of the multiplexer/demultiplexers assumes pass transistors are the word-length of the input is four bits, and the spreading factor is 16. As a result, an 8-bit adder is typically needed for the correlator. [0066] Only seven bits are used for system
[0067]FIG. 5 shows the standard design of a correlator for each code, and FIG. 6 shows a standard design of a matched filter for each code. The proper comparisons are between the 2×standard designs and systems [0068] D. Conclusion [0069] The specific hardware used to implement the correlators and the chip-matched filters is not critical to this invention. Persons of ordinary skill in the art will know to use whatever technologies or circuit designs are appropriate for their particular needs while still taking advantage of the savings attendant the present invention. Therefore, the scope of the appended claims is not to be limited to those specific examples. Referenced by
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