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Publication numberUS20020084842 A1
Publication typeApplication
Application numberUS 09/754,168
Publication dateJul 4, 2002
Filing dateJan 4, 2001
Priority dateJan 4, 2001
Also published asUS6407630
Publication number09754168, 754168, US 2002/0084842 A1, US 2002/084842 A1, US 20020084842 A1, US 20020084842A1, US 2002084842 A1, US 2002084842A1, US-A1-20020084842, US-A1-2002084842, US2002/0084842A1, US2002/084842A1, US20020084842 A1, US20020084842A1, US2002084842 A1, US2002084842A1
InventorsChi-Tai Yao, Wei-Chen Shen, Hung-Chih Liu
Original AssigneeChi-Tai Yao, Wei-Chen Shen, Hung-Chih Liu
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Dc offset canceling circuit applied in a variable gain amplifier
US 20020084842 A1
Abstract
The present invention discloses a DC offset canceling circuit applied in a variable gain amplifier. The DC offset canceling circuit comprises a transconductance amplifier and at least one internal capacitor to function as a filter. The input of the transconductance amplifier is electrically connected to the output of the variable gain amplifier, and the output of the transconductance amplifier and the at least one internal capacitor are electrically connected to the input of the variable gain amplifier to form a feedback loop. To cooperate with the function of the DC offset cancelation, the input stage of the variable gain amplifier comprises an auxiliary differential pair.
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Claims(3)
What is claimed is:
1. A DC offset canceling circuit applied in a variable gain amplifier, comprising:
a transconductance amplifier electrically connected to the output of the variable gain amplifier for transforming an input voltage to an output current based on a ratio;
at least one internal capacitor electrically connected to the output of said transconductance amplifier for generating a filtering function by working together with said transconductance amplifier; and
an auxiliary differential pair situated at the input of said variable gain amplifier and electrically connected to the output of said transconductance amplifier.
2. The DC offset canceling circuit applied in a variable gain amplifier of claim 1, wherein said variable gain amplifier comprises a first amplifier as an input stage, and said auxiliary differential pair is embedded in the input stage of said first amplifier.
3. The DC offset canceling circuit applied in a variable gain amplifier of claim 1, wherein said transconductance amplifier and said at least one internal capacitor are embedded in a chip.
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    The present invention relates to a DC offset canceling circuit applied in a variable gain amplifier, and particularly to a DC offset canceling circuit which uses internal capacitors inside an IC for generating a filtering function.
  • [0003]
    2. Description of Related Art
  • [0004]
    Variable gain amplifiers (VGA), which amplify input signals to necessary voltage levels of a system in demodulation process, are largely used in home network transceivers which transmit signals via cables. When the variable gain amplifier is used, a differential input end of an internal operational amplifier has the problem of intrinsic offset, and the intrinsic offset is always in the range of several mV to tens of mV. For wireless or wire communication, the maximum gain of the variable gain amplification is up to tens of dB; therefore, the intrinsic offset after amplification will affect the recovery ability of the received signal the characteristics of parameters of a dynamic range and signal noise ratio. A DC offset canceling circuit is shown in FIG. 1(a), disclosed by A. Parssinen et al., in “A 2-GHz Wide-Band Direct Conversion Receiver for WCDMA Application,” IEEE J.Solid-State Circuits, Vol. 34, pp. 1893-1903, December 1999. In FIG. 1, a closed loop feedback path 11 is formed by an operational amplifier, resistors and capacitors to cancel the intrinsic offset. Since the closed loop feedback path 11 executes the function of a low pass active-RC filter, the capacitors Cext 13 are huge and have to be put outside the chip. For designing a chip, it is necessary to provide more I/O pins to electrically connect to the external capacitors Cext 13. Consequently, both the design complexity and cost are increased.
  • [0005]
    Another prior art DC offset canceling circuit is shown in FIG. 1(b), disclosed by C. Dennis Hull et al., in “A Direct Conversion Receiver for 900 MHz (ISM Band) Spread-Spectrum Digital Cordless Telephone,” IEEE J. Solid-State Circuits, Vol. 31, No. 12, pp. 1955-1963, December 1996. The circuit is formed by cascading an operational amplifier, resistors and capacitors, and a closed loop feedback path 12 is formed to cancel the intrinsic offset. As mentioned above, the external capacitors Cext 13 contained in the closed loop feedback path 12 are huge and must be put outside the chip. For designing a chip, it is necessary to provide more I/O pins to electrically connect to the external capacitors. Consequently, both the design complexity and cost are increased.
  • SUMMARY OF THE INVENTION
  • [0006]
    A first object of the present invention is to cancel the intrinsic offset of a variable gain amplifier.
  • [0007]
    A second object of the present invention is to provide a DC offset canceling circuit having less I/O pins.
  • [0008]
    A third object of the present invention is to provide a simplified DC offset canceling circuit at a lower cost.
  • [0009]
    For achieving the above objects, the present invention proposes a DC offset canceling circuit applied in a variable gain amplifier, which comprises a transconductance amplifier and at least one internal capacitor to function as a filter. The input of the transconductance amplifier is electrically connected to the output of the variable gain amplifier, and the output of the transconductance amplifier and the at least one internal capacitor are electrically connected to the input of the variable gain amplifier to form a feedback loop. To cooperate with the function of the DC offset cancelation, the input stage of the variable gain amplifier comprises an auxiliary differential pair.
  • [0010]
    The DC offset canceling circuit applied in a variable gain amplifier according to the present invention comprises a transconductance amplifier, at least one internal capacitor and an auxiliary differential pair. The transconductance amplifier is electrically connected to the output of the variable gain amplifier for transforming an input voltage to an output current based on a ratio. The at least one internal capacitor is electrically connected to the output of the transconductance amplifier for generating a filtering function by working together with the transconductance amplifier. The auxiliary differential pair is situated at the input of the variable gain amplifier and electrically connected to the output of the transconductance amplifier to function as a current switch. Besides, the variable gain amplifier comprises a first amplifier to function as an input stage, and the auxiliary differential pair is embedded in the input end of the first amplifier. The transconductance amplifier and the at least one internal capacitor are embedded in a chip.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0011]
    The present invention will be described according to the appended drawings in which:
  • [0012]
    FIGS. 1(a) and (b) show prior art DC offset canceling circuits applied in a variable gain amplifier;
  • [0013]
    [0013]FIG. 2 shows a DC offset canceling circuit applied in a variable gain amplifier according to the present invention;
  • [0014]
    [0014]FIG. 3 shows a first amplifier containing an auxiliary differential pair according to the present invention; and
  • [0015]
    [0015]FIG. 4 shows a simulation diagram of frequency responses according to the present invention.
  • PREFERRED EMBODIMENT OF THE PRESENT INVENTION
  • [0016]
    [0016]FIG. 2 shows a DC offset canceling circuit 26 applied in a variable gain amplifier 25 according to the present invention. The variable gain amplifier 25 includes a first amplifier 21, a second amplifier 22, a plurality of switches 201-208, and a plurality of resistors. The DC offset canceling circuit 26 includes a transconductance amplifier 23 and at least one internal capacitor 24. The switches 201-204 are used to adjust the variable gain of the first amplifier 21. For example, if the switch 201 is closed, then the gain will be raised; and if the switch 202 is closed, then the gain will be reduced. The switches 205-208 are used to adjust the variable gain of the second amplifier 22. For example, if the switch 205 is closed, then the gain will be raised; and if the switch 207 is closed, then the gain will be reduced. The transconductance amplifier 23 is used to transform the output voltage of the second amplifier 22 to an output current based on a ratio. The output of the transconductance amplifier 23 is coupled to at least one internal capacitor 24, and then is fed back to the input of the first amplifier 21 for canceling the DC offset of the variable gain amplifier. The transconductance amplifier 23 is cooperated with the internal capacitors 24, only about 10 pF or even under 10 pF, as a Gm-C filter. Since the capacitance of the internal capacitors 24 is small, the internal capacitors 24 can be manufactured easily inside an IC, and do not occupy I/O pins.
  • [0017]
    [0017]FIG. 3 shows a first amplifier 21 containing an auxiliary differential pair according to the present invention. The first amplifier 21 is formed by cascading a well-known amplifier circuit 32 and an auxiliary differential pair 31 whose inputs INNX and INPX are electrically connected to the output of the transconductance amplifier 23.
  • [0018]
    [0018]FIG. 4 shows a simulation diagram of frequency responses according to the present invention. A first curve 41 is the frequency response of the variable gain amplifier 25, and a second curve 42 is the frequency response of the first amplifier 21. In FIG. 4, it is shown that the transconductance amplifier 23 cooperated with the internal capacitors 24 can generate a 10 MHz bandwidth.
  • [0019]
    The above-described embodiments of the present invention are intended to be illustrated only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6646509 *Jul 31, 2002Nov 11, 2003Broadcom CorporationLayout technique for matched resistors on an integrated circuit substrate
US6958654Jul 31, 2003Oct 25, 2005Broadcom CorporationLayout technique for matched resistors on an integrated circuit substrate
US7065336 *Jun 19, 2002Jun 20, 2006U-Blox AgAnalog base band unit for a RF receiver and method for using the same
US7157973 *Apr 12, 2005Jan 2, 2007Broadcom CorporationLayout technique for matched resistors on an integrated circuit substrate
US7161752 *Nov 5, 2003Jan 9, 2007Marvell International Ltd.Asymmetric compensation circuit
US7242545Dec 28, 2006Jul 10, 2007Marvell International Ltd.Asymmetric compensation circuit
US7369820 *Apr 1, 2005May 6, 2008Freescale Semiconductor, Inc.System and method for DC offset correction in transmit baseband
US20030017815 *Jun 19, 2002Jan 23, 2003Mu-Blox AgAnalog base band unit for a RF receiver and method for using the same
US20040078771 *Jul 31, 2003Apr 22, 2004Sobel David A.Layout technique for matched resistors on an integrated circuit substrate
US20050179497 *Apr 12, 2005Aug 18, 2005Broadcom CorporationLayout technique for matched resistors on an integrated circuit substrate
US20060223457 *Apr 1, 2005Oct 5, 2006Freescale Semiconductor, Inc.System and method for DC offset correction in transmit baseband
USRE43776Dec 30, 2008Oct 30, 2012Broadcom CorporationLayout technique for matched resistors on an integrated circuit substrate
Classifications
U.S. Classification330/9
International ClassificationH03F3/45
Cooperative ClassificationH03F3/45659, H03F3/45188
European ClassificationH03F3/45S3B1A4, H03F3/45S1B1A
Legal Events
DateCodeEventDescription
Nov 9, 2001ASAssignment
Owner name: SILICON INTEGRATED SYSTEMS CORPORATION, A CORPORAT
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YAO, CHI-TAI;SHEN, WEI-CHEN;LIU, HUNG-CHIH;REEL/FRAME:012425/0018
Effective date: 20001228
Oct 21, 2005FPAYFee payment
Year of fee payment: 4
Jan 25, 2010REMIMaintenance fee reminder mailed
Jun 18, 2010LAPSLapse for failure to pay maintenance fees