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Publication numberUS20020084867 A1
Publication typeApplication
Application numberUS 09/418,020
Publication dateJul 4, 2002
Filing dateOct 14, 1999
Priority dateOct 19, 1998
Also published asDE69932908D1, EP1001480A2, EP1001480A3, EP1001480B1, US6448866, US20030062968
Publication number09418020, 418020, US 2002/0084867 A1, US 2002/084867 A1, US 20020084867 A1, US 20020084867A1, US 2002084867 A1, US 2002084867A1, US-A1-20020084867, US-A1-2002084867, US2002/0084867A1, US2002/084867A1, US20020084867 A1, US20020084867A1, US2002084867 A1, US2002084867A1
InventorsShigeru Watanabe
Original AssigneeShigeru Watanabe
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Microwave semiconductor variable attenuation circuit
US 20020084867 A1
Abstract
Microwave semiconductor variable attenuation circuit includes a coupler, two series circuits of inductors and a plurality of means having controllable resistance. Each Inductor of the series circuits has a defined inductance, where one end of the series circuit is connected to a terminal of the coupler. Each of means having controllable resistance respectively being connected to a junction point between two respective inductors of the series circuit. All of means having controllable resistance are controlled on the basis of a common signal is provided at a single terminal.
By the above features provided that inductors of defined inductance between the coupler and the means having controllable resistance (e.g. a transistor or diode), the total impedance of the attenuation circuit can be properly set and a performance degradation at high frequency can be avoided.
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Claims(33)
What is claimed is:
1. A circuit for the variable attenuation of microwave signals, comprising;
(a) at least a first coupler,
(b) a first series circuit of inductors, each inductor having a defined inductance, where one end of said first series circuit is connected to a first terminal of said first coupler,
(c) a second series circuit of inductors, each inductor having a defined inductance, where one end of said second series circuit is connected to a second terminal of said first coupler, and
(d) a plurality of means having controllable resistance, each of said means respectively being connected to a junction point between two respective inductors of said first or second series circuit.
2. A circuit according to claim 1, characterized in that a second coupler is provided, where the other end of said first series circuit is connected to a first terminal of said second coupler, and the other end of said second series circuit is connected to a second terminal of said second coupler.
3. A circuit according to claim 2, characterized in that inductors at the ends of said first and second series circuits have a predetermined inductance represented as L, the remaining inductors have an inductance 2L, and said first and second series circuits satisfy Z0 2=2L/C, where the characteristic impedance of said first coupler is represented as Z0, and the capacity of said means having controllable resistance is represented as C.
4. A circuit according to claims 2, characterized in that each series circuit contains two inductors of equal inductance represented as L.
5. A circuit according to claim 4, characterized in that said first and second series circuits satisfy Z0 2=2L/C, where the characteristic impedance of said first coupler is represented as Z0, and the capacity of said means having controllable resistance is represented as C.
6. A circuit according to claim 2, characterized in that said second coupler has an impedance equal to the impedance of said first coupler.
7. A circuit according to claim 6, characterized in that said first and second series circuits satisfy Z0 2=2L/C, where the characteristic impedance of said first coupler is represented as Z0, and the capacity of said means having controllable resistance is represented as C.
8. A circuit according to claims 6, characterized in that each series circuit contains two inductors of equal inductance represented as L.
9. A circuit according to claim 8, characterized in that said first and second series circuits satisfy Z0 2=2L/C, where the characteristic impedance of said first coupler is represented as Z0, and the capacity of said means having controllable resistance is represented as C.
10. A circuit according to claim 2, wherein said means having controllable resistance is a field-effect-transistor.
11. A circuit according to claim 10, characterized in that said first and second series circuits satisfy Z0 2=2L/C, where the characteristic impedance of said first coupler is represented as Z0, and the capacity of said means having controllable resistance is represented as C.
12. A circuit according to claims 10, characterized in that each series circuit contains two inductors of equal inductance represented as L.
13. A circuit according to claim 12, characterized in that said first and second series circuits satisfy Z0 2=2L/C, where the characteristic impedance of said first coupler is represented as Z0, and the capacity of said means having controllable resistance is represented as C.
14. A circuit according to claim 2, characterized in that the means having controllable resistance is a diode.
15. A circuit according to claim 14, characterized in that said first and second series circuits satisfy Z0 2=2L/C, where the characteristic impedance of said first coupler is represented as Z0, and the capacity of said means having controllable resistance is represented as C.
16. A circuit according to claims 14, characterized in that each series circuit contains two inductors of equal inductance represented as L.
17. A circuit according to claim 16, characterized in that said first and second series circuits satisfy Z0 2=2L/C, where the characteristic impedance of said first coupler is represented as Z0. and the capacity of said means having controllable resistance is represented as C.
18. A circuit according to claim 1, characterized in that the other end of said first series circuit is grounded through a first termination resistor, and the other end of said second series circuit is grounded through a second termination resistor.
19. A circuit according to claim 18, characterized in that inductors at the ends of said first and second series circuits have a predetermined inductance represented as L, the remaining inductors have an inductance 2L, and said first and second series circuits satisfy Z0 2=2L/C, where the characteristic impedance of said first coupler is represented as Z0, and the capacity of said means having controllable resistance is represented as C.
20. A circuit according to claims 18, characterized in that each series circuit contains two inductors of equal inductance represented as L.
21. A circuit according to claim 20, characterized in that said first and second series circuits satisfy Z0 2=2L/C, where the characteristic impedance of said first coupler is represented as Z0, and the capacity of said means having controllable resistance is represented as C.
22. A circuit according to claim 18, wherein said means having controllable resistance is a field-effect-transistor.
23. A circuit according to claim 22, characterized in that said first and second series circuits satisfy Z0 2=2L/C, where the characteristic impedance of said first coupler is represented as Z0, and the capacity of said means having controllable resistance is represented as C.
24. A circuit according to claims 22, characterized in that each series circuit contains two inductors of equal inductance represented as L.
25. A circuit according to claim 24, characterized in that said first and second series circuits satisfy Z0 2=2L/C, where the characteristic impedance of said first coupler is represented as Z0, and the capacity of said means having controllable resistance is represented as C.
26. A circuit according to claim 18, characterized in that the means having controllable resistance is a diode.
27. A circuit according to claim 26, characterized in that said first and second series circuits satisfy Z0 2=2L/C, where the characteristic impedance of said first coupler is represented as Z0, and the capacity of said means having controllable resistance is represented as C.
28. A circuit according to claims 26, characterized in that each series circuit contains two inductors of equal inductance represented as L.
29. A circuit according to claim 28, characterized in that said first and second series circuits satisfy Z0 2=2L/C, where the characteristic impedance of said first coupler is represented as Z0, and the capacity of said means having controllable resistance is represented as C.
30. A circuit according to claim 1, characterized by being a Monolithic-Microwave-Integrated-Circuit structure on a semiconductor board.
31. A circuit according to claim 30, characterized in that the circuit is of symmetrical structure with respect to said first series circuit and said second series circuit.
32. A circuit according to claim 31, characterized by common through holes for grounding pairs of said means having controllable resistance, each pair consisting of one means connected to a junction between two inductors of said first series circuit and one means connected to a junction between two inductors of said second series circuit.
33. A circuit according to claim 1, characterized in that every junction point between two inductors in said first or second series circuit is connected to a means having controllable resistance, and all of the means having controllable resistance are controlled on the basis of a common signal is provided at a single terminal.
Description
BACKGROUND OF THE INVENTION

[0001] This invention relates to the variable attenuation circuit used for microwave communication device, for example. Microwave communication device is controlling high frequency characteristics, such as a power gain of apparatus and an output power level by using the variable attenuation circuit. As an attenuation circuit, a variable resistor network linked to the T type or I type is constituted, and a diode or a field effect transistor is used as a variable resistor.

[0002] However, it is necessary for realizing desired attenuation and desired impedance to decide each resistance of the variable resistor connected in series in parallel as any resistance according to attenuation. when above attenuation circuit is used, and the control circuit setting up resistor of a variable resistance becomes complicated.

[0003] Therefore, a circuit using the directivity coupler shown in FIG. 1 or FIG. 2 is used much as a circuit of microwave. Referring now to the attenuation circuit shown in FIG. 1, a passage terminal 13, and a coupling terminal 14 of a first directional coupler 10 connect to a coupling terminal 24, and a passage terminal 23 of a second directional coupler 20 respectively. Field-Effect-Transistor (FET) 30 a, 30 b are connected in parallel between the passage terminal 13 and the coupling terminal 24, and the coupling terminal 14 and the passage terminal 23 respectively. An input terminal 11 of the first directional coupler 10, and an input terminal 21 of the second directional coupler 20 are a signal input, and a signal output of this attenuation circuit respectively. And isolation terminals 12 and 22 of respective directional couplers 10 and 20 terminate in termination resistors 15 and 25 respectively. Signals inputted from the input terminal 11 as signal input are distributed to the passage terminal 13 and coupling terminal 14 by first directional coupler 10. After passing through the parallel circuit of the FETs 30 a and 30 b, the distributed signals are inputted into the coupling terminal 24 and the passage terminal 23 of the second directional coupler 20 respectively, is compounded, and is outputted from the input terminal 21 of the second directional coupler 20 as signal output. FET 30 a and 30 b that voltage between drain 31 a, 31 b and source 32 a, 32 b is 0 [V] are used as variable resistor by gate bias provided for gate 33 a, 33 b through resistor 16 a, 16 b from control terminal 41. The power absorbed by FET 30 a and 30 b is changed, passage loss is controlled according to changing the resistance of FET 30 a and 30 b compared with the characteristic impedance (for example, 50 [Ω]) of a directional coupler, as a result, the variable attenuation circuit is realized with it.

[0004] Moreover, Since the reflective power produced by the mismatching with the impedance of FET and the characteristic impedance of a directional coupler is absorbed by the terminus resistance 15 connected to the isolation terminal 12, it can realize a matching state without returning to the input terminal 11.

[0005] Next referring now to the attenuation circuit shown in FIG. 2, this circuit uses the mismatching with impedance of the directional coupler 10 and FET 30 a or 30 b. And as a result, a variable attenuation circuit is realized by compounding the reflected signal, making it output from the isolation terminal 12, changing the impedance of FET 30 a and 30 b, and controlling reflection. Therefore, in the variable attenuation circuit using the directional coupler, the matching state is realized by using only gate bias of FET connected in parallel as control voltage, and using the character of a directional coupler. In the circuit shown in FIG. 1 as mentioned above, in order to obtain the desired attenuation, the resistance of variable resistor, such as FET, is changed.

[0006] However, since reactance component of the impedance by influence of the parasitic capacity of FET or a parasitic inductance becomes large According frequency becomes high, even if gate bias changes, it is not able to change enough in the impedance of FET. Referring now to FIG. 3, FIG. 3 is a passage characteristic diagram of the variable attenuator in consideration of parasitic capacity of FET. FIG. 3 shows the passage characteristic of the case, for example, in the composition of FIG. 1, used High-Electron-Mobility-Transistor (HEMT) that gate length is 0.3 micrometers and gate width is 300 micrometers. Moreover, it uses four fingers Lange couplers of main frequency 25 GHz as directional coupler. There is a problem that the variable range becomes small remarkably, in high frequency domain, as passage loss becomes large.

[0007] Accordingly, it is an object of the present invention to provide a microwave variable attenuation circuit, in the variable attenuation circuit using a coupler, preventing increase of the passage loss and decrease of the variable attenuation by the parasitic capacity of a variable resistor, and having good transmission characteristic.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a circuit diagram of a variable attenuator according to the prior art:

[0009]FIG. 2 is a circuit diagram of a variable attenuator according to the prior art; and

[0010]FIG. 3 is a passage characteristic diagram of a variable attenuator according to the prior art.

[0011]FIG. 4 is a circuit diagram of first embodiment of a variable attenuator according to the present invention;

[0012]FIG. 5 is an equivalent circuit diagram of a Field-Effect-Transistor;

[0013]FIG. 6 is a passage characteristic diagram of variable attenuator according to the present invention;

[0014]FIG. 7 is a circuit diagram of second embodiment of a variable attenuator according to the present invention;

[0015]FIG. 8 is a circuit diagram of third embodiment of a variable attenuator according to the present invention;

[0016]FIG. 9 is a circuit diagram of fourth embodiment of a variable attenuator according to the present invention;

[0017]FIG. 10 is a circuit diagram of fifth embodiment of a variable attenuator according to the present invention;

[0018]FIG. 11 is a monolithic microwave integrated circuit diagram of fifth embodiment of a variable attenuator according to the present invention;

[0019]FIG. 12 is a circuit diagram of sixth embodiment of a variable attenuator according to the present invention;

[0020]FIG. 13 is a circuit diagram of seventh embodiment of a variable attenuator according to the present invention;

[0021]FIG. 14 is a circuit diagram of eighth embodiment of a variable attenuator according to the present invention;

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] This invention will be described in further detail with reference to the accompanying drawings.

[0023] (First Embodiment)

[0024] Referring now to FIG. 4, there is shown a variable attenuator circuit using Field-Effect-Transistors (referred to as FET below). Inductors 51 a, 51 b, 52 a, and 52 b are respectively equal inductance, the inductors 51 a and 52 a are connected in series to a passage terminal 13 of first directional coupler 10 (for example, 3 dB directional coupler) and a coupling terminals 24 of second directional coupler 20, and the inductors 51 b and 52 b are connected in series to a coupling terminal 14 of first directional coupler 10 and a passage terminal 23 of second directional coupler 20. Drain terminals 31 a and 31 b of FET 30 a and 30 b are respectively connected to connection parts of the inductors 51 a and 52 a and inductors 51 b and 52 b, gate terminals 33 a and 33 b connect to the control terminal 41 through resistors 16 a and 16 b, and source terminals 32 a and 32 b are grounded. Moreover, in this circuit, an input terminal 11 of the first directional coupler 10 is as a signal input, an input terminal 21 of the second directional coupler 20 is as a signal output, and isolation terminals 12 and 22 of directional couplers 10 and 20 terminate termination resistors 15 and 25 respectively.

[0025] By the way, an equivalent circuit of FET 30 (Both 30 a and 30 b) in FIG. 5(a) is shown a parallel circuit having a variable resistor 34 controlled by control voltage VC and a parasitic capacitor (capacity C) in FIG. 5(b). In present invention, when the characteristic impedance of directional couplers 10 and 20 is Z0, the inductance C of the inductors 51 a, 52 a, 51 b, and 52 b is defined by equation 1.

Z0 2=2L/C  (1)

[0026] A signal inputted from the signal input (the input terminal 11) is distributed by the first directional coupler 10 to the passage terminal 13 and the coupling terminal 14, distributed signals are passing through the parallel circuits of FET 30 a and 30 b through the inductors 51 a, 52 a and inductors 51 b, 52 b, the distributed signals are inputted into the coupling terminal 24 and the passage terminal 23 of the second directional coupler 20 respectively, and a signal is outputted from the signal output (the input terminal 21). The power absorbed by the FETs 30 a and 30 b is changed, passage loss is controlled according to changing the resistance of the FETs 30 a and 30 b controlled by voltage impressed to the control terminal 41, as a result, this variable attenuation circuit is realized with it. Moreover, since the reflective power produced by the mismatching with the impedance of FET 30 and the characteristic impedance of directional couplers 10, 20 is absorbed by the termination resistor 15 connected to the isolation terminal 12, it can realize a matching state without returning to the input terminal 11.

[0027] Accordingly, since inductance L of the inductors 51 a, 52 a, 51 b, and 52 b satisfy Formula 1, a parallel circuit can be regarded as a circuit comprising a transmission line with same characteristic impedance as the directional couplers 10, 20 and a variable resistor. Thus since the impedance by the influence of the parasitic capacity 35 of the FET 30 can be made small in high frequency domain, the variable range of attenuation increases as the passage loss decreases.

[0028] Referring now to FIG. 6, there is shown a passage characteristic drawing of variable attenuator. Compared with FIG. 6 of the prior art, the passage loss is small, the variable range is large, and the frequency band which can be used as an attenuator becomes large.

[0029] (Second Embodiment)

[0030] Referring now to second embodiment of the present invention shown in FIG. 7, the same part as FIG. 7 is shown in the same mark.

[0031] A coupling terminal 14 and a passage terminal 13 of a directional coupler 10 are connected to ends of in-series circuits which connected in-series to inductors 61 a and 52 a, and inductors 51 b and 52 b, respectively. Another ends of in-series circuits connect termination resistors 17 a and 17 b, respectively. Inductance of the inductors 51 a and 52 a, and inductors 61 b and 52 b is equal respectively, connection parts of the inductors 51 a and 52 a, and inductors 51 b and 52 b are connected to drain terminals 31 a and 31 b of FET 30. and source terminals 32 a and 32 b of FET 30 are grounded. A control terminal is connected to gate terminals 32 a and 32 b of FET 30 through resistors 16 a and 16 b, and FET 30 a and 30 b are controlled by voltage impressed to the control terminal 41. Accordingly, reflected signals are outputted from a isolation terminal 12 by using mismatching with impedance of the directional coupler 10 and FET 30. and it is realized a variable attenuation circuit to control reflection by changing impedance of FET30.

[0032] In above variable attenuation circuit, there is the same effect as description of first embodiment. Since inductors 51 a and 52 a, and inductor 51 b and 52 b of second embodiment also satisfy Formula 1, the passage loss of a reflective signal decreases in a high frequency domain, the variable range of attenuation can enlarge, and the frequency range which can use as an attenuator becomes large.

[0033] (Third and Fourth Embodiments)

[0034] The present invention is embodied the variable attenuation circuit used the diode instead of FET, but the attenuation variable circuit used FET as a variable resistor is explained in above first and second embodiments.

[0035] Referring now to FIG. 8 and FIG. 9 of third and fourth embodiments, diodes 60 a and 60 b are used instead of FET 30 a and 30 b of FIG. 4 or FIG. 7. Anode terminals of diodes 60 a and 60 b connect to connection parts of inductors 51 a and 52 a, and inductor 51 b and 52 b respectively, and cathode terminals of 60 a and 60 b are grounded. One ends of choke coils 61 a and 61 b connect anode terminals of diodes 60 a and 60 b respectively, another ends connect control terminal 41. Moreover, resistance of diodes 60 a and 60 b are controlled by voltage impressed to choke coil 61 a and 61 b (control terminal 41).

[0036] Accordingly, since inductance L of inductor 51 a, 52 a, 51 b, and 52 b and connecting capacity Cp of diode 60 a and 60 b are decided as satisfy Formula. 2, the passage loss of a reflective signal decreases in a high frequency domain, the variable range of attenuation can enlarge, and the frequency range which can use as an attenuator becomes large.

Z0 2=2L/Cp  (2)

[0037] (Fifth Embodiment)

[0038] Referring now to FIG. 10 of fifth embodiment, ends of first and second ladder type circuits are connected to a coupling terminal 14 and a passage terminal 13 of the first directional coupler respectively, and another ends are connected a passage terminal 23 and coupling terminals 24 of the second directional coupler respectively. A First ladder type circuit is in-series circuit connected in-series to inductors 70 a-7 na (natural numbers of arbitrary n) of at least two or more, and drain terminals of FET 301 a-30 na are connected to each connecting point of inductors 70 a-7 na respectively. A Second ladder type circuit is also in-series circuit connected in-series to inductors 70 b-7 nb of at least two or more, and drain terminals of FET 301 b-30 nb are connected to each connecting point of inductors 70 b-7 nb respectively. All of source terminals of FET 301 a-30 na and FET 301 b-30 nb are grounded, and gate terminals of FET 301 a-30 na and FET 301 b-30 nb are connected to a control terminal 41 through resistor 161 a-16 na and resistor 161 b-16 nb respectively. When characteristic impedance of directional couplers 10 and 90 are Z0 respectively and each parasitic capacity of FET 301 a-30 na and FET 301 b-30 nb is C, inductors 70 a, 7 na, 70 b, and 7 nb set as inductance L, and other inductors set as inductance 2L. These characteristic impedance Z0, parasitic capacity C, and inductance L, 2L satisfy Formula. 1. Moreover, referring now to FIG. 11 of fifth embodiment, there is shown a Monolithic Microwave Integrated Circuit (MMIC) formed on a half-insulation semiconductor board. MMIC in FIG. 11 shows the case where n is three, source terminals of FET 301 a and 301 b, FET 302 a and 302 b, and FET 303 a and 303 b are connected to common through holes 81-83 respectively, and the common through holes 81-83 are grounded. FET and through holes of MMIC are symmetrical with a line A-A′ passing through the through holes 81-83 by a and b side.

[0039] Accordingly, in above variable attenuation circuit, the passage loss of a reflective signal decreases in a high frequency domain, the variable range of attenuation can be enlarged, and the frequency ranges which can use as an attenuator becomes large. Since number of components of MMIC can be reduced by communalizing through holes 81-83, the size of MMIC can become small. And since FET of MMIC is set up symmetry, characteristic of the whole attenuator is improved.

[0040] Moreover, since each FET can be set up small by using two or more FET, parasitic capacity and inductance of inductors become small. Therefore as the whole circuit, the variable range of attenuation can be enlarged according as the minimum insertion loss can become smaller.

[0041] (Sixth Embodiment)

[0042] Referring now to sixth embodiment of the present invention shown in FIG. 12, ends of first and second ladder type circuits are connected to a coupling terminal 14 and a passage terminal 13 of the first directional coupler respectively, and another ends are connected to termination resistors 17 a and 17 b. The first ladder type circuit is an in-series circuit connected in-series to inductors 70 a-7 na of at least two or more, and drain terminals of FET 301 a-30 na are connected to each connecting point of inductors 70 a-7 na respectively. The second ladder type circuit is also an in-series circuit connected in-series to inductors 70 b-7 nb of at least two or more, and drain terminals of FET 301 b-30 nb are connected to each connecting point of inductors 70 b-7 nb respectively. All of source terminals of FET 301 a-30 na and FET 301 b-30 nb are grounded, and gate terminals of FET 301 a-30 na and FET 301 b-30 nb are connected to a control terminal 41 through resistor 161 a-16 na and resistor 161 b-16 nb respectively. When characteristic impedance of directional couplers 10 is Z0 and each parasitic capacity of FET 301 a-30 na and FET 301 b-30 nb is C, inductors 70 a, 7 na, 70 b, and 7 nb set as inductance L, and other inductors set as inductance 2L. These characteristic impedance Z0, parasitic capacity C, and inductance L, 2L satisfy Formula. 1.

[0043] In above variable attenuation circuit, reflected signals are outputted from a isolation terminal 12 by using mismatching with impedance of the directional coupler 10 and FET 301 a-30 na, 301 b-30 nb, and it is realized a variable attenuation circuit to control reflection by changing impedance of FET 301 a-30 na, 301 b-30 nb.

[0044] Moreover, when the circuit of this embodiment forms as MMIC as shown in FIG. 11, the common through hole is not connected to only the gate terminal of FET but also the termination resistor. In this embodiment, FET and through holes of MMIC are also symmetrical with a passing line through the through holes.

[0045] Accordingly, since number of components of MMIC can be reduced by communalizing through holes, the size of MMIC can become small. And since the FET of the MMIC is set up symmetry, characteristic of the whole attenuator is improved.

[0046] Moreover, since each FET can be set up small by using two or more FET, parasitic capacity and inductance of inductors become small. Therefore for the whole circuit, the minimum insertion loss can become smaller, and the variable range of attenuation can be enlarged.

[0047] (Seventh and Eighth Embodiments)

[0048] Referring now to FIG. 13 and FIG. 14, seventh and eighth embodiments of the present invention use diodes 601 a-60 na, 601 b-60 nb instead of FET 301 a-30 na, 301 b-30 nb used fifth and sixth embodiments shown in FIG. 10 and FIG. 12. The resistance of the diodes is controlled by voltage impressed to Choke coils 61 a-6 na, 61 b-6 nb connected to anode terminals of the diode. When characteristic impedance of the directional couplers is Z0 and each connection capacity of the diode is Cp, inductors 70 a, 7 na, 70 b, and 7 nb set as inductance L, and other inductors set as inductance 2L.

[0049] In above embodiments like the fifth and sixth embodiments, the passage loss of a reflective signal decreases in a high frequency domain, the variable range of attenuation can be enlarged, and the frequency range that can use as an attenuator becomes large. When these embodiments form MMIC like FIG. 11, the size of MMIC can reduce by using common through holes. Since diodes of MMIC are set up symmetry, characteristic of the whole attenuator is improved.

[0050] Accordingly, since each diode can be set up small by using two or more diodes, connection capacity of the diode and inductance of the inductor become small. Therefore as the whole circuit, the minimum insertion loss can be reduce, and the variable range of attenuation can be enlarged.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6911853Mar 22, 2002Jun 28, 2005Rambus Inc.Locked loop with dual rail regulation
US7535271May 18, 2005May 19, 2009Rambus Inc.Locked loop circuit with clock hold function
US7902890May 12, 2009Mar 8, 2011Rambus Inc.Locked loop circuit with clock hold function
US8120399Mar 7, 2011Feb 21, 2012Rambus Inc.Locked loop circuit with clock hold function
US8319580Nov 30, 2011Nov 27, 2012Huawei Technologies Co., Ltd.Attenuator
US8680903Feb 6, 2012Mar 25, 2014Rambus Inc.Locked loop circuit with clock hold function
WO2011060740A1 *Nov 22, 2010May 26, 2011Huawei Technologies Co., Ltd.Attenuator
Classifications
U.S. Classification333/81.00R, 333/117
International ClassificationH01P1/22, H03H11/24, H03H7/25
Cooperative ClassificationH01P1/227, H03H7/25
European ClassificationH01P1/22D, H03H7/25
Legal Events
DateCodeEventDescription
Feb 12, 2014FPAYFee payment
Year of fee payment: 12
Jan 29, 2010FPAYFee payment
Year of fee payment: 8
Feb 13, 2006FPAYFee payment
Year of fee payment: 4
Nov 19, 1999ASAssignment
Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WATANABE, SHIGERU;REEL/FRAME:010391/0379
Effective date: 19991102
Owner name: KABUSHIKI KAISHA TOSHIBA 72, HORIKAWA-CHO, SAIWAI-