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Publication numberUS20020086462 A1
Publication typeApplication
Application numberUS 09/751,475
Publication dateJul 4, 2002
Filing dateDec 28, 2000
Priority dateDec 28, 2000
Also published asUS6432760, WO2002058147A2, WO2002058147A3
Publication number09751475, 751475, US 2002/0086462 A1, US 2002/086462 A1, US 20020086462 A1, US 20020086462A1, US 2002086462 A1, US 2002086462A1, US-A1-20020086462, US-A1-2002086462, US2002/0086462A1, US2002/086462A1, US20020086462 A1, US20020086462A1, US2002086462 A1, US2002086462A1
InventorsChandrasekharan Kothandaraman, Michael Stetter, Sundar Iyer
Original AssigneeChandrasekharan Kothandaraman, Michael Stetter, Iyer Sundar K.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method and structure to reduce the damage associated with programming electrical fuses
US 20020086462 A1
Abstract
An improved fuse structure in an integrated circuit (IC) structure is made by forming a gate stack comprised of layers of polysilicon and a silicide. Subsequent to the formation of the silicide layer, an etch stop silicon nitride layer is deposited over the silicide layer. The silicon nitride layer is patterned to expose the silicide layer. A soft passivation layer is deposited over the exposed silicide layer. The soft passivation layer has a low thermal conductivity which confines energy in the silicide layer, minimizing the current needed to program the fuse. The inherent ductility of the soft passivation layer prevents the generation of cracks in the surrounding layers.
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Claims(13)
Having thus described our invention, what we claim as new and desire to secure by Letters Patent is as follows:
1. A method of making an improved fuse structure in an integrated circuit (IC) formed in a silicon substrate comprising the steps of:
forming a gate stack comprised of layers of polysilicon and a silicide;
subsequent to the formation of the silicide layer, depositing an etch stop silicon nitride layer over the silicide layer;
covering the nitride layer with an oxide layer;
depositing and patterning a photoresist layer to define an opening over the oxide layer;
etching the oxide layer and the silicon nitride layer to expose the silicide layer of the gate stack; and
depositing a soft passivation layer over the exposed silicide layer, the soft passivation layer having a low thermal conductivity which confines energy in the silicide layer.
2. The method of making an improved fuse structure recited in claim 1, further comprising the step of planarizing the soft passivation layer.
3. The method of making an improved fuse structure recited in claim 1, wherein the step of forming the gate stack comprises the steps of:
depositing a layer of polysilicon over a silicon substrate;
depositing a layer of silicide over the layer of polysilicon; and
patterning the polysilicon and silicide to a desired dimension and shape.
4. The method of making an improved fuse structure recited in claim 3, further comprising the step of applying passivation to sidewalls of the patterned polysilicon and silicide.
5. The method of making an improved fuse structure recited in claim 4, further comprising the step of planarizing the soft passivation layer.
6. The method of making an improved fuse structure recited in claim 1, wherein the soft passivation layer is “SILK” (Silicon Low K).
7. The method of making an improved fuse structure recited in claim 1, wherein the soft passivation layer is a “spin-on” dielectric.
8. The method of making an improved fuse structure recited in claim 7, wherein the soft passivation layer is selected from the group consisting of “SILK” (Silicon Low K), fluorosilicate glass, and siloxane containing polymers.
9. An improved fuse structure for an integrated circuit (IC) formed in a silicon substrate comprising:
a gate stack formed on the silicon substrate, said gate stack comprised of layers of polysilicon and a silicide;
a nitride layer deposited over the silicide layer and an oxide layer covering the nitride layer;
metal contacts extending through the oxide layer and the nitride layer to the silicide layer to provide electrical contracts for the fuse; and
a soft passivation material filling a hole formed between the metal contacts and extending to the silicide layer, the soft passivation material having a low thermal conductivity which confines energy in the silicide layer.
10. The improved fuse structure recited in claim 9, further comprising a passivation applied to sidewalls of the gate stack prior to deposition of the nitride layer.
11. The improved fuse structure recited in claim 9, wherein the soft passivation layer is “SILK” (Silicon Low K).
12. The improved fuse structure recited in claim 9, wherein the soft passivation layer is a “spin-on” dielectric.
13. The improved fuse structure recited in claim 12, wherein the soft passivation layer is selected from the group consisting of “SILK” (Silicon Low K), fluorosilicate glass, and silocane containing polymers.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to programming electrical fuses in integrated circuit (IC) devices and, more particularly, to an improved method and structure to reduce the damage associated with programming electrical fuses.

[0003] 2. Background Description

[0004] Fuses are fabricated on various IC devices, such as memory arrays, to improve the yield during manufacturing. They are also used in some devices, such as field programmable arrays (FPGAs), to allow customization of the IC device for a particular application. Commonly, fuse structures are realized by patterning a gate stack (polysilicon and cobalt/tungsten silicide) to the appropriate dimensions. An etch-stop silicon nitride layer is deposited over the silicide as part of the fabrication process. The fusing process passes an electrical current through the fuse element to melt the fuse link by the resistive heating of the element. The location of the breakage is dependent on the defect structure in the fuse link.

[0005] Significant energy is needed to blow the fuse manufactured according to the current process. This leads to the generation of cracks in the surrounding layers. To prevent damage to other structures, the fuses are often laid out in a guarded area.

SUMMARY OF THE INVENTION

[0006] It is therefore an object of the present invention to provide an improved fuse structure which does away with the need to isolate the fuse structure to prevent damage to other structures.

[0007] It is another object of the invention to provide a fuse structure which exhibits improved reliability, efficiency, yield and packing density.

[0008] According to the invention, there is provided a new fuse structure which replaces the brittle and relatively inert nitride and silicon dioxide layer in current fuses with a soft passivation layer. The inherent ductility present in the soft passivation layer prevents the generation of cracks. In addition, this reduces pressure on the silicide link, allowing it to melt easily, lowering the current required to blow the fuse.

[0009] Specifically, during the manufacture of the fuse structure, the brittle and relatively inert silicon nitride and silicon dioxide layer is removed and a soft passivation layer is applied. A preferred material for the soft passivation layer is known in the art as “SILK” for Silicon Low K. Other possible materials could be various “spin-on” dielectrics such as fluorosilicate glass or siloxane containing polymers.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:

[0011]FIG. 1 is a cross-sectional view of the current fuse structure;

[0012]FIG. 2 is a cross-sectional view of the new fuse structure according to the invention; and

[0013]FIGS. 3A to 3E are cross-sectional view illustrating the process of manufacturing the fuse structure of FIG. 2.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

[0014] Referring now to the drawings, and more particularly to FIG. 1, there is shown a cross-section view of the current fuse structure. The current fuses are realized by patterning a gate stack (polysilicon 11 and cobalt/tungsten silicide 12) on a silicon substrate 13 to the appropriate dimensions. After passivation 14 has been applied to the patterned sidewalls of the polysilicon 11 and silicide 12, an etch-stop nitride 15 is deposited over the silicide as part of the standard process. Metal contacts 16, typically tungsten, are formed within holes formed in an overlying oxide layer 17.

[0015] The fusing process melts the fuse link by the resistive heating of the fuse element comprising the polysilicon 11 and silicide 12. Significant energy is needed to blow the fuse, as a portion of the energy is conducted away into other adjacent layers. This leads to the generation of cracks in the surrounding layers. These cracks could propagate under the cyclic stresses present in the chip operating environment leading to poor reliability in the field.

[0016]FIG. 2 shows the new fuse structure according to the invention. The process of manufacture is similar to that of the current process except that in the new structure, a lithographic patterning step and an etch is performed to open the fuse area, removing the oxide 17 above the fuse. The brittle and relatively inert silicon nitride layer 15 directly over the fuse is also removed in the etch. Then, a soft passivation layer 18 is applied. A suitable material for the soft passivation layer is “SILK” (Silicon Low K).

[0017]FIG. 3A shows the results of the first steps in the process to manufacture the structures shown in FIGS. 1 and 2. A polysilicon layer 31 and an overlying silicide layer 32 are deposited on a silicon substrate 33. The polysilicon layer 31 and the silicide layer 32 are patterned to form the desired shape and size of the fuse. Then, in FIG. 3B, sidewall passivation 34 is applied to the patterned polysilicon and silicide layers, and after passivation of the sidewalls, a layer of silicon nitride 35 is applied over the structure. In the next steps shown in FIG. 3C, an oxide layer 36 is applied over the structure, and then contact holes are etched through the oxide layer 36 and the underlying nitride layer 35 to the silicide layer 32. These contact holes are then filled with a metal, such as tungsten, to provide the electrical contacts 37.

[0018] The process to this point is conventional and yields the structure shown in FIG. 1. The invention takes the process further. Specifically, in FIG. 3D, a photoresist 38 is applied over the top surface of the structure. This photoresist is patterned over the fuse area. The oxide 36 and the nitride 35 are etched to expose the underlying silicide 32. Finally, in FIG. 3E, the photoresist masking layer is removed and the opening is filled with a “soft-passivation” material 39. The preferred material is “SILK” for Silicon Low K. Other possible materials could be various “spin-on” dielectrics such as fluorosilicate glass or silocane containing polymers. The application of this material is preferably done by spinning on the low k dielectric. The material is cured and planarized to complete the process.

[0019] The inherent ductility present in the soft passivation layer 39, as opposed to the brittle and inert silicon nitride and silicon dioxide, prevents the generation of cracks. Further, this reduces the pressure on the silicide link, allowing it to melt easily. Specifically, in the case of SILK, its smaller thermal conductivity confines the energy more efficiently, resulting in a decrease in the current needed to program the fuse.

[0020] While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6642135 *Oct 29, 2002Nov 4, 2003Samsung Electronics Co., Ltd.Method for forming semiconductor memory device having a fuse
US6642601 *Oct 25, 2001Nov 4, 2003Texas Instruments IncorporatedLow current substantially silicide fuse for integrated circuits
US6653710 *Feb 16, 2001Nov 25, 2003International Business Machines CorporationFuse structure with thermal and crack-stop protection
US7106164Dec 3, 2003Sep 12, 2006International Business Machines CorporationApparatus and method for electronic fuse with improved ESD tolerance
US7334320Dec 7, 2004Feb 26, 2008International Business Machines CorporationMethod of making an electronic fuse with improved ESD tolerance
US7442626 *Jun 24, 2004Oct 28, 2008Texas Instruments IncorporatedRectangular contact used as a low voltage fuse element
US7732898Feb 2, 2007Jun 8, 2010Infineon Technologies AgElectrical fuse and associated methods
US7943437Oct 12, 2007May 17, 2011International Business Machines CorporationApparatus and method for electronic fuse with improved ESD tolerance
US7977230Sep 17, 2008Jul 12, 2011Texas Instruments IncorporatedRectangular contact used as a low voltage fuse element
US8174091Jul 15, 2009May 8, 2012Taiwan Semiconductor Manufacturing Co., Ltd.Fuse structure
US8629050Apr 10, 2012Jan 14, 2014Taiwan Semiconductor Manufacturing Company, Ltd.E-fuse structure design in electrical programmable redundancy for embedded memory circuit
Classifications
U.S. Classification438/132, 257/E23.149, 257/529
International ClassificationH01L23/525
Cooperative ClassificationH01L23/5256
European ClassificationH01L23/525F
Legal Events
DateCodeEventDescription
Oct 10, 2006FPExpired due to failure to pay maintenance fee
Effective date: 20060813
Aug 14, 2006LAPSLapse for failure to pay maintenance fees
Mar 1, 2006REMIMaintenance fee reminder mailed
Jun 26, 2002ASAssignment
Owner name: INFINEON TECHNOLOGIES AG, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES NORTH AMERICA CORP.;REEL/FRAME:013030/0583
Effective date: 20020620
Owner name: INFINEON TECHNOLOGIES AG ST. MARTIN-STR. 53 81541
Owner name: INFINEON TECHNOLOGIES AG ST. MARTIN-STR. 5381541 M
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES NORTH AMERICA CORP. /AR;REEL/FRAME:013030/0583
Jan 3, 2002ASAssignment
Owner name: INFINEON TECHNOLOGIES NORTH AMERICA CORP., CALIFOR
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KOTHANDARAMAN, CHANDRASEKHARAN;STETTER, MICHAEL;REEL/FRAME:012430/0259;SIGNING DATES FROM 20010123 TO 20010129
Owner name: INFINEON TECHNOLOGIES NORTH AMERICA CORP. 1730 NOR
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KOTHANDARAMAN, CHANDRASEKHARAN /AR;REEL/FRAME:012430/0259;SIGNING DATES FROM 20010123 TO 20010129
Mar 19, 2001ASAssignment
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IYER, SUNDAR K.;REEL/FRAME:011708/0822
Effective date: 20010124
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION ARMONK
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATIONARMONK,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IYER, SUNDAR K. /AR;REEL/FRAME:011708/0822