The present invention concerns a thin layer semi-conductor structure and processes for embodying such a structure.
By thin layer semi-conductor structure is understood a structure having on the surface a fine semi-conductor layer in which will be manufactured electronic devices (this layer is called an active layer) and a substrate performing a mechanical support role. This substrate is generally electrically insulated form the surface layer. The substrate is constituted either from a solid insulating material (a dielectric in the case of the SOS), or from a conductor or semi-conductor material. In this latter case, it may be of the same material as that of the surface layer (the case of SOI), generally insulated form the surface layer by an insulation layer. In the case of the SOI, the mechanical substrate is usually constituted by a silicon substrate with a layer of silica on the surface, but it may also be constituted by a solid substrate of fused silica (silicon on quartz). Other thin layer semi-conductor structures are also known like the AsGa on silicon, the SiC on silicon or the GaN on sapphire etc. These structures are made either by technologies known as “Wafer Bonding”, or by heteroepitaxy.
STATE OF THE PRIOR ART
Thin layer semi-conductor structures like for example SOI structures are increasingly used to make electronic devices. SOI structures are used in particular to manufacture VLSI logic and analogue circuits or to manufacture power components. An SOI structure (or substrate) has several advantages relative to a solid silicon substrate. One of these advantages is that the insulant subjacent to the silicon layer makes it possible to reduce the stray capacitance of devices elaborated in the silicon layer, and all the more so the thicker this insulant is.
A now conventional process for making an SOI substrate is the SIMOX (Separation by IMplanted OXygen) process. According to this process, the insulant is a buried silicon oxide SiO2 layer obtained by uniform implantation of oxygen in a silicon substrate. This technology is now being challenged by other processes of the type known as “Wafer Bonding” in the English-speaking world, (and which will be denoted hereinafter by the term molecular adhesion), for example the BSOI process (described by J. HAISMA et al., in Jap. J. Appl. Phys., vol. 28, page L 725, 1989) or the UNIBOND process (described by M. BRUEL in Electron. Lett., vol. 31, page 1201, 1995).
SIMOX technology is still widely used. It is based on an implantation of a very high dose of oxygen. It allows the manufacture of buried layers of silicon only for thicknesses of between 100 and 400 nm. The major drawback of this technology is its cost due to the high dose ion implantation, and the need to resort to non standard micro-electronic equipment. Technologies of the molecular adhesion type do not have this drawback and make it possible additionally, in principle, to modulate the thicknesses of layers and the nature of the material constituting the insulant. The UNIBOND process additionally makes possible a lower cost and a better homogeneity of the silicon layer.
All current SOI substrates use the amorphous silica SiO2 as the base material for the buried insulating layer. This material is a good insulant, is easy to manufacture and gives very good interfaces with the silicon since it has few fixed charges and interface states. It has moreover a low dielectric constant, which is a favourable factor for the rapidity of the components because of the reduction in stray capacitance
Silica has however one great drawback: its very low thermal conductivity which is of the order of 0.2 W.m−1.K−1. This causes a substantial transitory and localised temperature rise, altogether problematic for the proper operation of the components. One way of reducing this rise in temperature is to reduce the thickness of the buried silica layer. However, the drawbacks of this reduction in thickness are that on the one hand stray capacitance is increased (thereby reducing the rapidity of the components) and, on the other hand, electrical strength is reduced. Furthermore, the reduction in thickness of the insulating layer is not easy to obtain in the implementation of processes of the molecular adhesion type where a good quality of adhesion is obtained much more easily with layers of thickness exceeding 300 nm.
The idea has therefore been conceived of replacing the silica by another insulating material having better thermal conductivity. Reference may be made on this subject to the documents EP-A-0 707 338, EP-A-0 570 321, EP-A-0 317 445 and WO-A-91/11822. The materials proposed (for example diamond) do not have a good interface with silicon from the electrical point of view. For this reason, a thin layer of silica is added so as to achieve the interface with the surface silicon. These solutions are certainly effective from the thermal point of view, but they are not easily applicable in association with the technologies of bonding by molecular adhesion. It is indeed extremely difficult to bond materials of high thermal conductivity as conceived.
There are also structures of the SiC type on silicon or AsGa on silicon with generally an intermediate insulating layer. These structures are often used to make super high frequency power components. Because of this, heat dissipation in the component is substantial and the thermal conductivity of the silicon and/or of the dielectrics used is insufficient to provide a junction temperature which is not crippling.
DISCLOSURE OF THE INVENTION
To overcome this problem, there is proposed, according to the present invention, a thin layer semi-conductor structure having several layers between the semi-conductor surface layer, from which the electronic components will be elaborated, and the support substrate so as to decouple the functions of thermal conductivity and electrical insulation. This decoupling makes it possible to optimise, through a choice of appropriate materials these two functions, it being well understood that these materials must also allow a good interface quality (mechanical strength). The material in contact with the semi-conductor layer must additionally have a good quality electrical interface. Thus, the layer in contact with the semi-conductor surface layer may be made by means of an insulating layer offering good electrical insulation and a good electrical interface quality. A layer of a material having thermal conductivity is used to overcome the problem of temperature rise produced by the electronic components. Another layer may be used to provide the quality connection with the support substrate if the layer of good thermal conductivity does not allow it. It may be of low thermal conductivity. If this layer is insulating, its role may also be to maintain sufficient thickness of insulant of low permittivity under the semi-conductor surface layer in order to retain low stray capacitance for the electronic components and to allow ease of bonding when using molecular adhesion technology.
An object of the invention is therefore a thin layer semi-conductor structure including a semi-conductor surface layer separated from a support substrate by an intermediate zone, the intermediate zone being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate, having an electrical quality of interface considered as sufficiently good with the semi-conductor surface layer and including at least one first layer, of satisfactory thermal conductivity to provide an operation considered as correct of the electronic device or devices which are to be elaborated from the semi-conductor surface layer, characterised in that the intermediate zone additionally includes a second insulating layer of low dielectric constant, located between the first layer and the support substrate.
Advantageously, the thickness of the first layer is selected as a function of the dimension of the zones of heat dissipation of the electronic devices. By way of example, as thickness for the first layer will be chosen advantageously a thickness which is of the same order of magnitude or greater than the dimension of the largest zone of thermal dissipation. In the event of a third layer being used, it must be as thin as possible so as to optimise the role of the first layer.
The second layer must be able to provide adhesion considered as satisfactory between the intermediate zone and the support substrate. By good adhesion is understood a mechanical adhesion with as few macroscopic defects (i.e. localised adhesion failures) as possible.
The intermediate zone may include a third layer, insulating between the first layer and the semi-conductor surface layer, said third layer conferring on the intermediate zone said electrical quality of interface. If the semi-conductor structure is an SOI structure, the third layer is advantageously a layer of silicon oxide obtained for example by thermal oxidation.
If the semi-conductor structure is an SOI structure, the second layer may be a layer of silicon oxide.
The first layer is able not to be insulating. Its thickness is adjusted as a function of the heat generation zones in the semi-conductor layer. It may particularly be multi-layer.
More exactly, for the layer of good thermal conductivity to play its role effectively in diffusing the heat generated in the components, its thickness will have to be sufficient. Conversely, the thickness of possible intermediate layers of relatively low thermal conductivity between this layer and the semi-conductor layer will have to be minimised. In practice, the respective thicknesses of these layers necessary for good thermal operation will depend on the size of the components and on their operation (size of the thermal dissipation zones) and on the thermal conductivities of the different materials (semi-conductor layer, dissipating layer, sub-layers and substrate). The first layer may be constituted by a material chosen from among polycrystalline silicon, diamond, alumina, silicon nitride, aluminium nitride, boron nitride, silicon carbide.
The first layer may be in contact with- the semi-conductor surface layer and be able to confer said electrical interface quality. The semi-conductor structure being an SOI structure, the first layer may be a layer of cubic silicon carbide.
Advantageously, the second layer of the intermediate zone has sufficient thickness of insulant of low dielectric constant for the stray capacitance present between the semi-conductor surface layer and the support substrate to be sufficiently low to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer.
A further object of the invention is a process for manufacturing a semi-conductor structure as defined above, characterised in that it includes the following stages:
manufacture of the layers of the intermediate zone on one face of a first substrate intended to supply said semi-conductor surface layer and/or on one face of a second substrate intended to supply the support substrate of the structure,
bonding of the first substrate on the second substrate, said faces being placed opposite each other,
making of said semi-conductor surface layer.
Making said semi-conductor surface layer may include reducing the thickness of the first substrate.
Bonding the first substrate onto the second substrate may be achieved by molecular adhesion. In this case, the manufacturing stage of the layers of the intermediate zone may include the deposition of at least one bonding layer to allow bonding by molecular adhesion. Advantageously, said bonding layer is a silicon oxide layer.
The first layer may be a layer of a material chosen from among polycrystalline silicon deposited by LPCVD, diamond deposited by PECVD, alumina deposited by reactive cathode sputtering, silicon nitride deposited by CVD, aluminium nitride deposited by CVD, boron nitride deposited by CVD and silicon carbide deposited by CVD.
The reduction in the thickness of the first substrate may be obtained by using one or more technologies from among: rectification, chemical attack, polishing, separation following thermal treatment along a cleavage plane induced by ion implantation.