US20020089064A1 - Flexible lead surface-mount semiconductor package - Google Patents

Flexible lead surface-mount semiconductor package Download PDF

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Publication number
US20020089064A1
US20020089064A1 US09/756,007 US75600701A US2002089064A1 US 20020089064 A1 US20020089064 A1 US 20020089064A1 US 75600701 A US75600701 A US 75600701A US 2002089064 A1 US2002089064 A1 US 2002089064A1
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Prior art keywords
semiconductor device
cantilevers
zigzag
package
surface mount
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US09/756,007
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Jiahn-Chang Wu
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Cheng Kung Capital LLC
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Jiahn-Chang Wu
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Priority to US09/756,007 priority Critical patent/US20020089064A1/en
Publication of US20020089064A1 publication Critical patent/US20020089064A1/en
Priority to US10/404,793 priority patent/US7755199B2/en
Assigned to CHENG KUNG CAPITAL, LLC reassignment CHENG KUNG CAPITAL, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WU, JIAHN-CHANG
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49544—Deformation absorbing parts in the lead frame plane, e.g. meanderline shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This invention relates to semiconductor device package, particularly to surface mount optoelectric diode package, such as that for a light emitting diode (LED), a laser diode (LD), a photo diode (PD), etc.
  • the invention is also applicable to a light sensor diode, such as a image sensor.
  • the invention may also be applicable to packages for other non-optoelectric semiconductor devices.
  • FIG. 1 shows a prior art optoelectric diode package.
  • a semiconductor chip 10 is mounted on two metallic plates 11 , 12 serving as extension leads for a surface-mount diode package.
  • the chip 10 is sealed in glue 13 for protection.
  • FIG. 2 shows the side view of the package.
  • the outer portions of the metallic plates 11 and 12 are not covered with glue 13 .
  • the bottoms of the exposed portions L, R are contact surfaces for surface mounting to a motherboard. When the temperature changes, the motherboard may bend, causing the device chip 10 to break away from the metallic plates 11 , 12 . Then, the diode cannot function.
  • the keys of a computer key board are lit with a light emitting diodes for easy recognition in the dark. Due to constant pounding the keys, the light emitting devices may dislodge from the leads.
  • An object of the present invention is to prevent an optoelectric device from breaking away from the leads of a surface mount package due to temperature stress. Another object of this invention is to prevent a semiconductor device from breaking away from the leads of surfacemount package due to bending stress.
  • FIG. 1 shows the top view of a prior art package for surface mounting a diode chip to a motherboard.
  • FIG. 2 shows the side view of FIG. 1.
  • FIG. 3 shows the top view of diode package with two horizontal zigzag cantilevers based on the present invention.
  • FIG. 4 shows the side view of Fig. 3.
  • FIG. 5 shows the top view of a second embodiment of the package with two inverted V-shaped horizontal cantilevers.
  • FIG. 6 shows the side view of FIG. 5.
  • FIG. 7 shows the top view of a third embodiment of a package with two vertical cantilevers.
  • FIG. 8 shows the side view of FIG. 7.
  • FIG. 9 shows the top view of a fourth embodiment of a package with two horizontal zigzag cantilevers for packaging a diode with a top electrode and a bottom electrode.
  • FIG. 10 shows the side view of FIG. 9.
  • FIG. 3 shows the top view of the first embodiment of diode package based on the present invention.
  • a diode chip 20 is mounted on two metallic plates 21 , 22 .
  • the metallic plates 21 and 22 have a rectangular cut 25 in the middle portion to form two horizontal zigzag cantilevers.
  • the cantilevers serve as springs. When the package is subject to temperature variations, the spring action of the zigzag cantilevers can cushion the expansion and contraction stress.
  • the chip 20 is sealed in glue 23 up to a portion of the zigzag cantilevers as shown in side view FIG. 4.
  • the bottoms of the unsealed portions L 1 and R 1 of the metallic plates 21 , 22 serve as contacts for surface mounting the package to a motherboard.
  • FIG. 5 shows the top view of a second embodiment of this invention.
  • the diode chip 20 is mounted on two metallic plates 31 , 32 as in FIG. 3.
  • the cut 35 in the metallic plates 31 , 32 is of inverted V-shape (instead of being rectangular) to form the zigzag cantilevers. Otherwise the function of zigzag cantilevers are the same as in FIG. 3.
  • the chip 20 is sealed in glue 23 up to a portion of the zigzag cantilevers.
  • FIG. 6 shows the side view of FIG. 5, corresponding to FIG. 4.
  • the bottoms of the unsealed portions L 2 and R 2 of the metallic plates 31 , 32 serve as contacts for surface mounting the package to a motherboard.
  • FIG. 7 shows the top view of a third embodiment of the present invention.
  • the diode chip 20 is mounted on two metallic plates 41 , 42 .
  • the metallic plates are bent to form two two vertical zigzag cantilevers 45 .
  • the zigzag cantilevers serve as springs to cushion the stress due to temperature variations and bending.
  • FIG. 8 shows the side view of FIG. 7.
  • the chip 20 is sealed in glue 23 up to a portion of the zigzag cantilevers.
  • the bottoms of the unsealed portions L 3 and R 3 of the metallic plates 41 , 42 serve as contacts for surface mounting the package to a motherboard.
  • FIG. 9 shows the top view of a fourth embodiment of the present invention.
  • the diode chip 50 has a top electrode and a bottom electrode, unlike the chip 20 in previous embodiments with two bottom electrodes.
  • the diode chip 50 is mounted on a metallic plate 52 .
  • the top electrode of diode chip 50 is wire-bonded by wire 56 to the second metallic plate 51 , as shown in side view FIG. 10.
  • metallic plates 51 and 52 have cuts 55 to form horizontal zigzag cantilevers.
  • the zigzag cantilevers serve as springs to cushion the stress due to temperature variations and bending.
  • the chip 50 is sealed in glue 23 up to a portion a portion of the zigzag cantilevers.
  • the bottoms of the unsealed portions L 4 and R 4 of the metallic plates 51 and 52 respectively serve as contacts for surface mounting the package the package to a motherboard.

Abstract

A diode chip is mounted on two bottom metal leads of a surface-mount package through two flexible links. The links are zigzag cantilevers attached to the metallic plates. The cantilevers serve as springs to support the device and to cushion any temperature stress or bending stress so as not to damage the connection between the device and the metallic leads.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • This invention relates to semiconductor device package, particularly to surface mount optoelectric diode package, such as that for a light emitting diode (LED), a laser diode (LD), a photo diode (PD), etc. The invention is also applicable to a light sensor diode, such as a image sensor. The invention may also be applicable to packages for other non-optoelectric semiconductor devices. [0002]
  • 2. Brief Description of the Related Art [0003]
  • FIG. 1 shows a prior art optoelectric diode package. A [0004] semiconductor chip 10 is mounted on two metallic plates 11, 12 serving as extension leads for a surface-mount diode package. The chip 10 is sealed in glue 13 for protection. FIG.2 shows the side view of the package. The outer portions of the metallic plates 11 and 12 are not covered with glue 13. The bottoms of the exposed portions L, R are contact surfaces for surface mounting to a motherboard. When the temperature changes, the motherboard may bend, causing the device chip 10 to break away from the metallic plates 11, 12. Then, the diode cannot function.
  • Another occasion for the [0005] device chip 10 to break away the metallic plates 11,12 occurs when the diode package is mounted on a curvilinear motherboard such as a display panel. The curving of the surface can also cause bending stress on the device to damage the device. An example of such a situation occurs when a decorative light emitting ribbon is mounted at the corner of an automobile body.
  • Still another occasion occurs for the keys of a computer key board. Sometimes, the keys are lit with a light emitting diodes for easy recognition in the dark. Due to constant pounding the keys, the light emitting devices may dislodge from the leads. [0006]
    • SUMMARY OF THE INVENTION
  • An object of the present invention is to prevent an optoelectric device from breaking away from the leads of a surface mount package due to temperature stress. Another object of this invention is to prevent a semiconductor device from breaking away from the leads of surfacemount package due to bending stress. [0007]
  • These objects are achieved by mounting a semiconductor chip to its bottom metal leads for surface mounting through two flexible links. The links are zigzag cantilevers attached to the metallic plates. The cantilevers serve as springs to support the device and to cushion any temperature stress or bending stress so as not to damage the connection between the device and the metallic leads.[0008]
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • FIG. 1 shows the top view of a prior art package for surface mounting a diode chip to a motherboard. [0009]
  • FIG. 2 shows the side view of FIG. 1. [0010]
  • FIG. 3 shows the top view of diode package with two horizontal zigzag cantilevers based on the present invention. [0011]
  • Fig. 4 shows the side view of Fig. 3. [0012]
  • FIG. 5 shows the top view of a second embodiment of the package with two inverted V-shaped horizontal cantilevers. [0013]
  • FIG. 6 shows the side view of FIG. 5. [0014]
  • FIG. 7 shows the top view of a third embodiment of a package with two vertical cantilevers. [0015]
  • FIG. 8 shows the side view of FIG. 7. [0016]
  • FIG. 9 shows the top view of a fourth embodiment of a package with two horizontal zigzag cantilevers for packaging a diode with a top electrode and a bottom electrode. [0017]
  • FIG. 10 shows the side view of FIG. 9.[0018]
    • DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 3 shows the top view of the first embodiment of diode package based on the present invention. A [0019] diode chip 20 is mounted on two metallic plates 21, 22. The metallic plates 21 and 22 have a rectangular cut 25 in the middle portion to form two horizontal zigzag cantilevers. The cantilevers serve as springs. When the package is subject to temperature variations, the spring action of the zigzag cantilevers can cushion the expansion and contraction stress. The chip 20 is sealed in glue 23 up to a portion of the zigzag cantilevers as shown in side view FIG. 4. The bottoms of the unsealed portions L1 and R1 of the metallic plates 21, 22 serve as contacts for surface mounting the package to a motherboard.
  • FIG. 5 shows the top view of a second embodiment of this invention. The [0020] diode chip 20 is mounted on two metallic plates 31, 32 as in FIG. 3. However the cut 35 in the metallic plates 31, 32 is of inverted V-shape (instead of being rectangular) to form the zigzag cantilevers. Otherwise the function of zigzag cantilevers are the same as in FIG. 3. The chip 20 is sealed in glue 23 up to a portion of the zigzag cantilevers. FIG. 6 shows the side view of FIG. 5, corresponding to FIG. 4. The bottoms of the unsealed portions L2 and R2 of the metallic plates 31, 32 serve as contacts for surface mounting the package to a motherboard.
  • FIG. 7 shows the top view of a third embodiment of the present invention. The [0021] diode chip 20 is mounted on two metallic plates 41, 42. The metallic plates are bent to form two two vertical zigzag cantilevers 45. As in FIG. 3 and FIG. 5, the zigzag cantilevers serve as springs to cushion the stress due to temperature variations and bending. FIG. 8 shows the side view of FIG. 7. The chip 20 is sealed in glue 23 up to a portion of the zigzag cantilevers. The bottoms of the unsealed portions L3 and R3 of the metallic plates 41, 42 serve as contacts for surface mounting the package to a motherboard.
  • FIG. 9 shows the top view of a fourth embodiment of the present invention. The [0022] diode chip 50 has a top electrode and a bottom electrode, unlike the chip 20 in previous embodiments with two bottom electrodes. The diode chip 50 is mounted on a metallic plate 52. The top electrode of diode chip 50 is wire-bonded by wire 56 to the second metallic plate 51, as shown in side view FIG. 10. As in previous first and second embodiments, metallic plates 51 and 52 have cuts 55 to form horizontal zigzag cantilevers. The zigzag cantilevers serve as springs to cushion the stress due to temperature variations and bending. The chip 50 is sealed in glue 23 up to a portion a portion of the zigzag cantilevers. The bottoms of the unsealed portions L4 and R4 of the metallic plates 51 and 52 respectively serve as contacts for surface mounting the package the package to a motherboard.
  • While the preferred embodiments of the invention have been described, it will be apparent to those skilled in the art that various modifications may be made in the embodiments without departing from the spirit of the present invention. Such modifications are all within the scope of this invention. [0023]

Claims (10)

1. A surface mount semiconductor device package, comprising;
a semiconductor device; and
at least two metallic plates on which said semiconductor device is mounted,
said metallic plates having bottom contacts for surface mounting to a motherboard and zigzag cantilevers for making connections to said semiconductor device.
2. A surface mount semiconductor device package as described in claim 1, wherein said semiconductor device is a diode.
3. A surface mount semiconductor device package as described in claim 2, wherein said zigzag cantilevers are horizontal.
4. A surface mount semiconductor device package as described in claim 3, wherein said zigzag cantilevers are of inverted-U shape.
5. A surface mount semiconductor device package as described in claim 3, wherein said zigzag cantilevers are of inverted-V shape.
6. A surface mount semiconductor device package as described in claim 2, wherein said zigzag cantilevers are vertical.
7. A surface mount semiconductor device package as described in claim 1, further comprising a glue to seal said semiconductor device.
8. A surface mount semiconductor device package as described in claim 2, wherein said diode has two bottom electrodes.
9. A surface mount semiconductor device as described in claim 2, wherein said diode has a top electrode and a bottom electrode.
10. A surface mount semiconductor device as described in claim 9, wherein said bottom electrode rests on the first plate of said metallic plates and said top electrode is wire-bonded to the second plate of said metallic plates.
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Cited By (11)

* Cited by examiner, † Cited by third party
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