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Publication numberUS20020090824 A1
Publication typeApplication
Application numberUS 09/756,415
Publication dateJul 11, 2002
Filing dateJan 8, 2001
Priority dateJan 8, 2001
Also published asUS7015145
Publication number09756415, 756415, US 2002/0090824 A1, US 2002/090824 A1, US 20020090824 A1, US 20020090824A1, US 2002090824 A1, US 2002090824A1, US-A1-20020090824, US-A1-2002090824, US2002/0090824A1, US2002/090824A1, US20020090824 A1, US20020090824A1, US2002090824 A1, US2002090824A1
InventorsV.C. Jaiprakash, Norbert Arnold
Original AssigneeV.C. Jaiprakash, Norbert Arnold
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Self-aligned collar and strap formation for semiconductor devices
US 20020090824 A1
Abstract
A method for fabricating a buried strap forms a dielectric collar along sidewalls of a trench. The trench is formed in a substrate. The trench is filled with a conductive material and the conductive material is recessed in the trench to expose a portion of the collar. A masking layer is deposited in the trench over the exposed portion of the collar. A portion of the masking layer is removed over one side of the collar and a portion of the collar is etched on the one side. A buried strap is formed on the conductive material, which connects to the substrate on the one side.
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Claims(16)
What is claimed is:
1. A method for fabricating a buried strap, comprising the steps of:
forming a dielectric collar along sidewalls of a trench, the trench formed in a substrate;
filling the trench with a conductive material;
recessing the conductive material in the trench to expose a portion of the collar;
depositing a masking layer in the trench over the exposed portion of the collar;
removing a portion of the masking layer over one side of the collar;
etching a portion of the collar on the one side; and
forming a buried strap on the conductive material, which connects to the substrate on the one side.
2. The method as recited in claim 1, wherein the masking layer includes nitride.
3. The method as recited in claim 1, wherein the step of removing a portion of the masking layer includes patterning a cut mask for etching the masking layer.
4. The method as recited in claim 1, wherein the step of removing a portion of the masking layer includes the steps of:
forming a polysilicon layer over the trench;
doping and oxidizing the polysilicon layer in predetermined areas;
removing the polysilicon layer in other than the predetermined areas; and
etching the masking layer the in accordance with the predetermined areas.
5. The method as recited in claim 1, further comprising the step of forming isolation trenches in communication with the trench.
6. The method as recited in claim 5, further comprising the steps of:
oxidizing surfaces within the isolation trenches;
lining the isolation trenches with a nitride layer;
filling the isolation trenches with a dielectric material.
7. The method as recited in claim 6, further comprising the steps of:
protecting portions of the nitride layer in communication with the trench during the step of removing a portion of the masking layer by employing surfaces oxidized in the step of oxidizing surfaces.
8. The method as recited in claim 6, wherein the step of oxidizing surfaces includes forming an oxide between about 70 angstroms to about 90 angstroms in thickness.
9. The method as recited in claim 1, wherein the step of forming a buried strap includes the steps of:
depositing a buried strap conductor in the trench; and
etching back the buried strap conductor.
10. A method for fabricating a one-sided buried strap, comprising the steps of:
forming a dielectric collar along sidewalls of a trench, the trench formed in a substrate;
filling the trench with a conductive material;
etching isolation trenches in communication with the trench;
oxidizing surfaces within the isolation trenches;
lining the isolation trenches with a nitride layer;
filling the isolation trenches with a dielectric material;
recessing the conductive material in the trench to expose a portion of the collar;
depositing a masking layer in the trench over the exposed portion of the collar;
removing a portion of the masking layer over one side of the collar;
etching a portion of the collar on the one side; and
forming a buried strap on the one side.
11. The method as recited in claim 10, wherein the masking layer includes nitride.
12. The method as recited in claim 10, wherein the step of removing a portion of the masking layer includes patterning a cut mask for etching the masking layer.
13. The method as recited in claim 10, wherein the step of removing a portion of the masking layer includes the steps of:
forming a polysilicon layer over the trench;
doping and oxidizing the polysilicon layer in predetermined areas;
removing the polysilicon layer in other than the predetermined areas; and
etching the masking layer the in accordance with the predetermined areas.
14. The method as recited in claim 10, further comprising the steps of:
protecting portions of the nitride layer in communication with the trench during the step of removing a portion of the masking layer by employing surfaces oxidized in the step of oxidizing surfaces.
15. The method as recited in claim 10, wherein the step of oxidizing surfaces includes forming an oxide between about 70 angstroms to about 90 angstroms in thickness.
16. The method as recited in claim 10, wherein the step of forming a buried strap includes the steps of:
depositing a buried strap conductor in the trench; and
etching back the buried strap conductor.
Description
BACKGROUND

[0001] 1. Technical Field

[0002] This disclosure relates to semiconductor fabrication, and more particularly, to methods for forming a single sided buried strap on one side of the trench while protecting a collar dielectric on the other side of the trench.

[0003] 2. Description of the Related Art

[0004] To reduce memory cell size and increase the density of devices formed on a semiconductor chip, vertical transistors have been developed. Memory devices, such as dynamic random access memories (DRAM) may include vertical transistors. Vertical transistors are formed by providing a trench in a substrate and forming a dielectric collar on sidewalls of the trench. A storage node is formed in the trench and recessed to provide access to substrate walls. A buried strap is formed in the recess by depositing a highly doped material in the trench. For vertical transistors, a single side buried strap may be employed. This single-sided strap is formed by methods, which may cause damage to the collar on the opposite side of the trench. In these cases, the collar would not provide adequate protection from the adjacent device.

[0005] Therefore, a need exists for a fabrication method which removes a portion of a dielectric collar to form a single-sided buried strap without damage to portions of the collar, which are to remain in the trench.

SUMMARY OF THE INVENTION

[0006] A method for fabricating a buried strap forms a dielectric collar along sidewalls of a trench. The trench is formed in a substrate. The trench is filled with a conductive material and the conductive material is recessed in the trench to expose a portion of the collar. A masking layer is deposited in the trench over the exposed portion of the collar. A portion of the masking layer is removed over one side of the collar and a portion of the collar is etched on the one side. A buried strap is formed on the conductive material, which connects to the substrate on the one side.

[0007] In other methods, the masking layer preferably includes nitride. The step of removing a portion of the masking layer may include patterning a cut mask for etching the masking layer. The step of removing a portion of the masking layer may include the steps of forming a polysilicon layer over the trench, doping and oxidizing the polysilicon layer in predetermined areas, removing the polysilicon layer in other than the predetermined areas and etching the masking layer the in accordance with the predetermined areas. The may further includes the step of forming isolation trenches in communication with the trench. The method may include the steps of oxidizing surfaces within the isolation trenches, lining the isolation trenches with a nitride layer, filling the isolation trenches with a dielectric material. The method may further include the steps of protecting portions of the nitride layer in communication with the trench during the step of removing a portion of the masking layer by employing surfaces oxidized in the step of oxidizing surfaces. The step of oxidizing surfaces may include forming an oxide between about 70 angstroms to about 90 angstroms in thickness. The step of forming a buried strap may include the steps of depositing a buried strap conductor in the trench and etching back the buried strap conductor.

[0008] A method for fabricating a one-sided buried strap, includes the steps of forming a dielectric collar along sidewalls of a trench, the trench formed in a substrate, filling the trench with a conductive material, etching isolation trenches in communication with the trench, oxidizing surfaces within the isolation trenches, lining the isolation trenches with a nitride layer, filling the isolation trenches with a dielectric material, recessing the conductive material in the trench to expose a portion of the collar, depositing a masking layer in the trench over the exposed portion of the collar, removing a portion of the masking layer over one side of the collar, etching a portion of the collar on the one side and forming a buried strap on the one side.

[0009] In alternate embodiments, the masking layer may include nitride. The step of removing a portion of the masking layer may include patterning a cut mask for etching the masking layer. The step of removing a portion of the masking layer may include the steps of forming a polysilicon layer over the trench, doping and oxidizing the polysilicon layer in predetermined areas, removing the polysilicon layer in other than the predetermined areas and etching the masking layer the in accordance with the predetermined areas. The method may include the steps of protecting portions of the nitride layer in communication with the trench during the step of removing a portion of the masking layer by employing surfaces oxidized in the step of oxidizing surfaces. The step of oxidizing surfaces may include forming an oxide between about 70 angstroms to about 90 angstroms in thickness. The step of forming a buried strap may include the steps of depositing a buried strap conductor in the trench and etching back the buried strap conductor.

[0010] These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

[0011] This disclosure will present in detail the following description of preferred embodiments with reference to the following figures wherein:

[0012]FIG. 1 is a schematic diagram showing a cross-sectional view of a semiconductor device showing deep trenches and an isolation mask formed in accordance with the present invention;

[0013]FIG. 2 is a top view illustratively showing deep trenches with an isolation trench mask overlaid in accordance with the present invention;

[0014]FIG. 3 is a top view of the semiconductor device of FIG. 3 after isolation trenches have been etched and the isolation trench mask removed in accordance with the present invention;

[0015]FIG. 4 is a cross-sectional view of the semiconductor device of FIG. 3 taken at section line 4-4 of FIG. 3 in accordance with the present invention;

[0016]FIG. 5 is a cross-sectional view of the semiconductor device of FIG. 4 after isolation regions are formed in accordance with the present invention;

[0017]FIG. 6 is a top view of the semiconductor device of FIG. 5 in accordance with the present invention;

[0018]FIG. 7 is a cross-sectional view of the semiconductor taken at section line 7-7 of FIG. 6 showing a dielectric layer deposited in the deep trenches in accordance with the present invention;

[0019]FIG. 8 is a top view of the semiconductor device of FIG. 7 after patterning a cut mask in accordance with the present invention;

[0020]FIG. 9 is a cross-sectional view of the semiconductor taken at section line 9-9 of FIG. 8 showing the dielectric layer patterned in the deep trenches in accordance with the present invention;

[0021]FIG. 10 is a top view of the semiconductor device of FIG. 9 after the cut mask is removed in accordance with the present invention;

[0022]FIG. 11 is a cross-sectional view of the semiconductor device taken at section line 11-11 of FIG. 10 showing the dielectric layer removed where a layer 25 protects a layer 30 during the removal of the dielectric layer in accordance with the present invention;

[0023]FIG. 12 is a cross-sectional view of the semiconductor device of FIG. 10 showing a single side collar etch in accordance with the present invention;

[0024]FIG. 13 is a cross-sectional view of the semiconductor device of FIG. 12 showing a conductive layer deposited in accordance with the present invention;

[0025]FIG. 14 is a cross-sectional view of the semiconductor device of FIG. 13 showing the conductive layer forming a single-sided buried strap in accordance with the present invention;

[0026]FIG. 15 is a cross-sectional view of a semiconductor device with deep trenches filled, a dielectric layer formed in the deep trenches and an isolation trench mask formed in accordance with another embodiment of the present invention;

[0027]FIG. 16 is a top view of the semiconductor device of FIG. 15 after patterning isolation trench mask in accordance with the present invention;

[0028]FIG. 17 is a cross-sectional view of the semiconductor device of FIG. 16 taken at section line 17-17 of FIG. 16 showing isolation trenches formed in accordance with the present invention;

[0029]FIG. 18 is a cross-sectional view of the semiconductor device of FIG. 17 after isolation regions are formed in accordance with the present invention;

[0030]FIG. 19 is a cross-sectional view of the semiconductor device of FIG. 18 showing a dielectric layer and an amorphous polysilicon layer formed in accordance with the present invention;

[0031]FIG. 20 is a cross-sectional view of the semiconductor device of FIG. 19 showing the amorphous polysilicon layer converted to an etch mask in accordance with the present invention;

[0032]FIG. 21 is a cross-sectional view of the semiconductor device of FIG. 20 showing a filler material in the deep trench removed in accordance with the present invention;

[0033]FIG. 22 is a cross-sectional view of the semiconductor device of FIG. 21 showing a dielectric layer, formed in the deep trench, patterned in accordance with the present invention;

[0034]FIG. 23 is a cross-sectional view of the semiconductor device of FIG. 22 showing a single side collar etch in accordance with the present invention;

[0035]FIG. 24 is a top view of a semiconductor device having a collar recessed on opposite sides of a trench to form two self-aligned buried straps in accordance with the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0036] The present invention provides methods for fabricating memory cells with vertical transistors. The present invention relates, in particular to the removal of a portion of a dielectric collar without damaging other portions of the dielectric collar in a deep trench structure. The methods of the present invention provide at least the following features: protects the collar while forming a buried strap, ensures that the collar width is equal to an active area width, reduces/eliminates dependence of isolation regions on active area-to-deep trench overlay, eliminates the need for an additional active area pad nitride layer for patterning the active area and reduces process complexity.

[0037] The present invention confines the buried strap in a lateral dimension by a self-aligned strap formation process. In devices which need a strap on one side of the trench, the present invention permits for the formation of the buried strap on the one side while protecting a collar formed in the trench on the other side. These features will become apparent by the following description of the present invention. The structures and materials employed herein are for purposes of illustratively describing the present invention. These illustrative examples, may be modified or changed within the scope of the present invention.

[0038] Referring now in specific detail to the drawings in which like reference numerals identify similar or identical elements throughout the several views, and initially to FIG. 1, a cross-sectional view of a semiconductor device 10 is shown. Semiconductor device 10 preferably includes a dynamic random access memory (DRAM), although the present invention is applicable to any memory device having vertical transistors and a trench capacitor. Semiconductor device 10 includes a substrate 12, for example, a monocrystalline silicon substrate. A pad dielectric layer 13 (e.g., a pad nitride layer and a pad oxide layer) is formed on a surface of substrate 12. Trenches 14 (e.g., deep trenches (DT)) are formed in substrate 12 by patterning a hardmask layer (not shown) and etching pad dielectric layer 13 and substrate 12. A buried plate (not shown) is formed in a lower portion of trench 14 by doping substrate 12 at a lower portion of trenches 16, as is known in the art.

[0039] A dielectric collar 18 is formed in trench 14. Collar 18 preferably includes a silicon oxide formed by, for example, a TEOS deposition or a LOCOS process, and node formation prior to or after the collar, as is known in the art. Trench 16 is filled with a conductive material 20, such as, doped polysilicon, to form a storage node 22. Material 20 is removed from a top surface of pad dielectric layer 14 by a planarization process (e.g., chemicalmechanical polishing (CMP).

[0040] An isolation trench hardmask 24 is deposited and lithographically patterned to provide an etch mask for the formation of isolation trenches. As shown in FIG. 2, a top view of device 10 shows the lithographically patterned hardmask 24 relative to trenches 14. Trenches 14 include collar 18 and material 20 therein. Isolation trenches 26 (FIG. 4) are formed by performing a trench etch process, such as, a reactive ion etch (RIE). Hardmask 24 is then removed as shown in FIG. 3.

[0041] Referring to FIG. 4, a cross-section taken at section line 4-4 of FIG. 3 is shown, after etching isolation trenches 26. FIG. 5 shows the same section as FIG. 4 after hardmask 24 is removed and an oxidation process is performed to form an oxide on exposed surfaces of substrate 12 and material 20, which forms an oxidation layer 25. This oxidation layer 25 will be employed in later steps to protect a thin dielectric layer 30 from being etched from inside of trench 14. Dielectric layer 30 is conformally deposited on the walls and bottom of trenches 26 over oxidation layer 25. Dielectric layer 30 preferably includes a nitride. Trenches 26 are filled with a dielectric material, such as a high density plasma (HDP) oxide or the like to form shallow or intermediate trench isolation regions 32 (STI or IT, respectively). A CMP or other planarizing process is employed to planarize the top surface of device 10.

[0042]FIG. 6 is top view of device 10 after isolation regions 32 are filled. FIG. 7 is a cross-section taken at section line 7-7 of FIG. 6. Referring to FIG. 7, material 20 is recessed into trenches 14 by an anisotropic etching process. A thin dielectric layer 34 having a thickness of, for example, between about 2-5 nm is deposited. Dielectric layer 34 preferably includes a nitride layer.

[0043] Referring to FIG. 8, a top view of device 10 is shown after a cut mask 36 is deposited and patterned. Cut mask 36 may include a silicate glass, such as borophosphosilicate glass (BPSG), other oxides, photoresists or any other material which can be used to fill trench 14, form an etch mask and permit dielectric layer 34 to be patterned by an etch process. Cut mask 36 is deposited, lithographically patterned (e.g., by employing a patterned resist layer, and reactive ion etching cut mask 36 to obtain the appropriate pattern).

[0044] Referring to FIG. 9, a cross-sectional view taken at section line 9-9 of FIG. 8 is shown. Cut mask 36 protects dielectric layer 34 on the side 38 where collar 18 is to be preserved, and cut mask 36 leaves dielectric layer 34 exposed on a side 40 where a single sided buried strap is to be formed. Dielectric layer 34 is stripped in areas where it is left exposed by cut mask 36, as shown in FIG. 9.

[0045] Referring to FIG. 10, a top view of device 10 is shown after removing cut mask 36. FIG. 11 shows a cross-sectional view taken at section line 11-11 of FIG. 10. Dielectric layer 34 (FIG. 9) is removed from a surface 42. Surface 42 includes oxidation layer 25, which was formed earlier. Oxidation layer 25, which may be about 70 to 90 angstroms thick, protects dielectric layer 30 from being stripped during the removal of layer 34.

[0046] Referring to FIG. 12, cut mask 36 is removed and collar 18 is etched. Collar 18 is removed on side 38 and not side 40. On side 40, collar 18 is protected by dielectric layer 34. Advantageously, no lateral etching of collar 18 occurs on side 40, and collar 18 is self-aligned to appropriate areas of trench 14. Isolation trench 32 is protected form the collar etch process by dielectric layer 30 (see FIG. 11). Layer 25 is removed by the collar etch process.

[0047] Referring to FIG. 13, a conductive layer 46 is deposited in trench 14. Conductive layer 46 preferably includes doped polysilicon. As shown in FIG. 14, a buried strap polysilicon etchback (BSPE) process is performed to form a single-sided buried strap 50 in accordance with the present invention. Buried strap 50 provide a connection point between storage node 22 and a channel region 52 which will be formed in substrate 12. Channel region 52 will be formed into a channel for a vertical transistor (not shown) which will be enabled by a gate formed in an upper portion of trench 14. Processing continues as is known in the art to form vertical transistors and complete device 10.

[0048] Another embodiment of the present invention will now be described. This embodiment preferably includes dopant implantation and oxidation instead of a cut mask. Referring to FIG. 15, a sacrificial material 60 fill is performed to fill trench 14. Material 60 preferably includes polysilicon. Material 60 is planarized to provide a surface 62. This may be performed by a CMP process. An isolation trench mask 64, for example an oxide hardmask, is deposited and lithographically patterned as shown in FIG. 16.

[0049] Referring to FIG. 17, a cross-sectional view taken along section line 17-17 of FIG. 16 is shown after isolation trenches 26 are etched. As shown in FIG. 18, mask 64 is removed and an oxidation process is performed to form an oxide on exposed surfaces of substrate 12 to form an oxidation layer 25. This oxidation layer 25 will be employed in later steps to protect a thin dielectric layer 30 from being etched from inside of trench 14. Dielectric layer 30 is conformally deposited on the walls and bottom of trenches 26 over oxidation layer 25. Dielectric layer 30 preferably includes a nitride. Trenches 26 are filled with a dielectric material, such as a high density plasma (HDP) oxide or the like to form shallow or intermediate trench isolation regions 32 (STI or IT, respectively). A CMP or other planarizing process is employed to planarize the top surface 11 of device 10.

[0050] Referring to FIG. 19, material 60 is recessed into trench 14 by an anisotropic etching process. A thin dielectric layer 66 having a thickness of, for example, between about 2-3 nm is deposited. Dielectric layer 66 preferably includes a nitride layer. An amorphous polysilicon layer 68 is deposited over the surface of device 10.

[0051] Referring to FIG. 20, layer 68 (FIG. 19) is implanted with p or n type dopants, such as, for example, B, BF2, P or As. The implantation is performed at an angle to provide adequate shadowing of material in layer 68 which is directly above a portion of the trench. Undoped portions of layer 68 are then removed by etching, and the remaining portions of layer 68 are oxidized to form a mask 70. This leaves a mask 70 for etching layers therebelow.

[0052] Referring to FIG. 21, dielectric layer 66 and fill material 60 are removed down to layer 34 by an anisotropic etching processes, such as RIE processes. Dielectric layer 30 (FIG. 16) is protected from being etched inside of trench 14 by oxidation layer 25. As shown in FIG. 22, layer 34 is removed from side 38. Collar 18 is etched from side 38, as shown in FIG. 23. Mask 70 and material 60 are removed from trench 14. Now, a single-sided buried strap is formed by a buried strap conductor deposition and etch back as described above, and processing continues as is known in the art.

[0053] In a non-self-aligned scheme, the width of the collar must exceed a width dimension of an active area region to ensure lateral isolation. In other words, a sufficient amount of collar insulation must be present to ensure the sides of the trench are isolated from the regions outside the trench. The width of the collar in the non-self-aligned case must be large enough to account for misalignment tolerances between the active area (AA) region and the trench. Advantageously, in the self-aligned methods of the present invention, the collar width may be made exactly equal to the AA width and still provide good isolation. Since self-alignment is provided, the size of the collar and trench do not need to include larger dimensions to account for misalignment tolerances between the active area (AA) region and the trench.

[0054] Taking advantage of the alignment between active areas and deep trenches, permits additional advantages for the embodiments described above and for other memory cell designs. Referring to FIG. 24, a top view of a semiconductor device 200 is shown in accordance with another embodiment of the present invention. For device 200, buried straps are needed on both sides of trench 14. Collar 18 is recessed in regions 19 to permit access to material 20 in each trench 14 from active areas 15. Advantageously, collar 18 shares a same width dimension (e.g., regions 19) as active areas 15 and provides good isolation in remaining areas (regions of collar outside regions 19 and below STI region 32). These advantages are also applicable to the embodiments described above.

[0055] Having described preferred embodiments for self-aligned collar and strap formation for semiconductor devices (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments of the invention disclosed which are within the scope and spirit of the invention as outlined by the appended claims. Having thus described the invention with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7250336Jun 17, 2005Jul 31, 2007Infineon Technologies AgMethod for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure
US8354345 *May 11, 2010Jan 15, 2013Hynix Semiconductor Inc.Method for forming side contact in semiconductor device through self-aligned damascene process
US8569131 *Nov 19, 2010Oct 29, 2013International Business Machines CorporationSource/drain-to-source/drain recessed strap and methods of manufacture of same
US20110130004 *May 11, 2010Jun 2, 2011Sang-Oh LeeMethod for forming side contact in semiconductor device through self-aligned damascene process
US20120126337 *Nov 19, 2010May 24, 2012International Business Machines CorporationSource/drain-to-source/drain recessed strap and methods of manufacture of same
DE10310811A1 *Mar 12, 2003Sep 30, 2004Infineon Technologies AgProduction of a trench capacitor used in integrated circuits comprises forming a trench in a substrate using a hard mask, forming a capacitor dielectric in the lower and middle trench region, and further processing
DE10310811B4 *Mar 12, 2003Jul 27, 2006Infineon Technologies AgHerstellungsverfahren für einen Grabenkondensator mit einem Isolationskragen, der über einen vergrabenen Kontakt einseitig mit einem Substrat elektrisch verbunden ist
DE102004029516B3 *Jun 18, 2004Dec 29, 2005Infineon Technologies AgHerstellungsverfahren für eine Schattenmaske in einem Graben einer mikroelektronischen oder mikromechanischen Struktur sowie Verwendung derselben
Classifications
U.S. Classification438/700, 257/E21.653, 257/E21.652
International ClassificationH01L21/8242
Cooperative ClassificationH01L27/10864, H01L27/10867
European ClassificationH01L27/108M4B6C
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JAIPRAKASH, V.C.;ARNOLD, NORBERT;REEL/FRAME:011447/0904;SIGNING DATES FROM 20001228 TO 20010103