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Publication numberUS20020096555 A1
Publication typeApplication
Application numberUS 09/767,645
Publication dateJul 25, 2002
Filing dateJan 23, 2001
Priority dateJan 23, 2001
Also published asUS6419148
Publication number09767645, 767645, US 2002/0096555 A1, US 2002/096555 A1, US 20020096555 A1, US 20020096555A1, US 2002096555 A1, US 2002096555A1, US-A1-20020096555, US-A1-2002096555, US2002/0096555A1, US2002/096555A1, US20020096555 A1, US20020096555A1, US2002096555 A1, US2002096555A1
InventorsScott Waxler, Dan Zemer
Original AssigneeOrbotech Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
System for forming bumps on wafers
US 20020096555 A1
Abstract
A system and method for forming bumps on an integrated circuit including a scanning direct laser imager employed to selectably expose a photosensitive layer deposited on an integrated circuit substrate, thereby to define regions overlying selected portions of the substrate, a developer developing said photosensitive layer to form apertures in the photosensitive layer at the defined regions, and a solder applicator applying a solder composition to the apertures to define solder bumps on the integrated circuit at selected portions thereof.
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Claims(25)
What is claimed is:
1. A method for forming bumps on an integrated circuit, comprising:
employing a scanning direct laser imager to selectably expose a photosensitive layer deposited on an integrated circuit substrate thereby to define regions overlying selected portions of said integrated circuit substrate;
developing said photosensitive layer thereby to selectively remove the photosensitive layer at said regions; and
applying a solder composition to said predetermined regions, thereby to define solder bumps overlying said selected portions of said integrated circuit substrate.
2. A method for forming bumps on an integrated circuit substrate according to claim 1 and wherein said photosensitive layer is a solder mask.
3. A method for forming bumps on an integrated circuit substrate according to claim 1 and wherein employing said direct laser imager defines exposed regions having a spatial density which exceeds a spatial density which is realizable using an exposure mask.
4. A method for forming bumps on an integrated circuit substrate according to claim 1 and wherein employing said direct laser imager defines exposed regions of photoresist to produce apertures having walls whose perpendicularity to a surface of the integrated circuit substrate exceeds the perpendicularity which is realizable using an exposure mask.
5. A method for forming bumps on an integrated circuit substrate according to claim 1 and wherein said employing, developing and applying take place waferwise prior to dicing of said integrated circuit substrate into individual dies.
6. A method for forming bumps on an integrated circuit substrate according to claim 2 and wherein said employing, developing and applying take place waferwise prior to dicing of said integrated circuit substrate into individual dies.
7. A method for forming bumps on an integrated circuit substrate according to claim 1 and wherein said electrical circuit comprises an integrated circuit and said substrate comprises a semiconductor substrate.
8. A method for forming bumps on an integrated circuit substrate according to claim 1 and further comprising:
selectively forming metal bases overlying selected portions of said integrated circuit substrate and wherein said regions exposed in said photosensitive layer overly said bases.
9. A method for forming bumps on an integrated circuit substrate according to claim 8 and forming said metal bases comprises:
depositing a metal layer on said substrate;
coating said metal layer with a photoresist;
selectively exposing said photoresist to define a multiplicity of locations thereon;
developing said exposed photoresist and removing said photoresist other than at said locations, thereby to expose said metal layer other than at said locations; and
etching said metal layer to remove said metal layer other than at said locations to define a multiplicity of metal bases formed on said substrate.
10. A method for forming bumps on an integrated circuit substrate according to claim 9 and further comprising:
coating said substrate and said metal bases thereon with a layer of photosensitive solder mask.
11. A system for forming bumps on an integrated circuit, comprising:
a scanning laser direct imager selectably exposing a photosensitive layer deposited on an integrated circuit substrate thereby to define regions in said photosensitive layer overlying selected portions of said integrated circuit substrate;
a developer developing said photosensitive layer thereby to selectively remove the photosensitive layer at said regions; and
a solder applicator applying a solder composition to said predetermined regions, thereby to define bumps overlying said selected portions of said integrated circuit substrate.
12. A system for forming bumps on an integrated circuit substrate according to claim 11 wherein said photosensitive layer is a solder mask.
13. A system for forming bumps on an integrated circuit substrate according to claim 11 and wherein said direct laser imager defines exposed regions having a spatial density which exceeds a spatial density which is realizable using an exposure mask.
14. A system for forming bumps on an integrated circuit substrate according to claim 11 and wherein said direct laser imager defines exposed regions of said photosensitive layer to produce apertures having walls whose perpendicularity to a surface of the integrated circuit substrate exceeds the perpendicularity which realizable using an exposure mask.
15. A system for forming bumps on an integrated circuit substrate according to claim 11 and wherein said direct imager, said developer and said solder applicator operate waferwise prior to dicing of said integrated circuit substrate into individual dies.
16. A system for forming bumps on an integrated circuit substrate according to claim 12 and wherein said direct imager, said developer and said solder applicator operate waferwise prior to dicing of said integrated circuit substrate into individual dies.
17. A system for forming bumps on an integrated circuit substrate according to claim 11 and wherein said electrical circuit comprises an integrated circuit and said substrate comprises a semiconductor substrate.
18. A system for forming bumps on an integrated circuit substrate according to claim 11 and wherein said scanning laser direct imager comprises:
a laser emitting laser light;
a modulator receiving said laser light and modulating said laser light in accordance with control data received from a controller; and
a polygonal mirror receiving said modulated laser and scanning said modulated laser light to expose said photoresist in a predetermined pattern.
19. A system for forming bumps on an integrated circuit substrate according to claim 11 and further comprising:
a metal base applier applying metal bases overlying selected portions of said integrated circuit substrate and wherein said regions overly said bases.
20. A system for forming bumps on an integrated circuit substrate according to claim 19 and wherein said metal base applier comprises:
a metal layer depositer depositing a metal layer on said substrate;
a photoresist coater coating said metal layer with a photoresist;
a laser direct imaging system selectively exposing said photoresist to define a multiplicity of locations;
a developer developing said exposed photoresist and removing said photoresist other than at said locations, thereby to expose said metal layer other than at said locations;
an etcher removing said metal layer other than at said locations to define a multiplicity of metal bases formed on said substrate.
21. A system for forming bumps on an integrated circuit substrate according to claim 19 and further comprising:
a photosensitive layer coater coating said substrate and said metal bases thereon with a layer of photosensitive solder mask.
22. A system for forming bumps on an integrated circuit substrate according to claim 20 and wherein said scanning laser direct imaging system comprises:
a laser emitting laser light;
a modulator receiving said laser light and modulating said laser light in accordance with control data received from a controller; and
a polygonal mirror receiving said modulated laser and scanning said modulated laser light to expose said photoresist in a predetermined pattern.
23. A method for forming bumps on an integrated circuit, comprising:
exposing a first photosensitive layer deposited on an integrated circuit substrate thereby to define regions in said photosensitive layer overlying selected portions of said integrated circuit substrate;
applying a second photosensitive coating to the integrated circuit substrate;
employing a scanning laser direct imaging system to expose said second photosensitive coating to define apertures in said second photosensitive coating generally overlying said regions;
processing said second photosensitive coating to form apertures therein; and
applying a solder composition to said apertures to form bumps.
24. A method for forming a portion of an electrical circuit on an integrated circuit substrate comprising:
loading a first integrated circuit substrate and at least a second integrated circuit substrate onto a laser pattern exposure system; and
exposing a selected portion of a photosensitive layer deposited on said second integrated circuit substrate prior to completing an exposure sequence exposing part of an electrical circuit pattern to be formed on a photosensitive layer deposited on said first integrated circuit substrate.
25. A method for forming a portion of an electrical circuit on an integrated circuit substrate comprising:
loading an integrated circuit substrate onto a laser pattern exposure system, said substrate having formed on a surface thereof at least part of an integrated circuit pattern and a fiducial pattern having a known geometry with reference to said integrated circuit pattern, said substrate being at least partially coated with a photosensitive coating;
ascertaining the location of said fiducial pattern;
adjusting digital data representing a portion of an electrical circuit to be formed on said integrated circuit substrate according the location of said fiducial pattern; and
exposing a selected portion of said photosensitive layer with a laser beam according to a pattern supplied by said adjusted digital data.
Description
FIELD OF THE INVENTION

[0001] The present invention relates generally to methods and systems employed in the manufacture of electrical circuits and more particularly to the use of direct laser imaging for forming solder bumps on integrated circuit substrates.

BACKGROUND OF THE INVENTION

[0002] A known method for connecting integrated circuits to printed circuit board employs so-called “flip-chip” technology. An electrical circuit is formed on one side of an integrated circuit substrate, and solder bump contacts are formed on a layer overlaying the electrical circuit. The integrated circuit substrate is placed face down onto an interconnect, such as a multi-chip module or BGA substrate, so that the solder bump contacts are in registered contact with an array of contacts, such as surface mount pads, formed on the interconnect. The substrate and printed circuit board are heated to melt the solder and establish electrical connect between the integrated circuit and the interconnect.

[0003] The following U.S. patents are considered relevant to the art of solder bump preparation: U.S. Pat. No. 5,024,372 to Altman et al; U.S. Pat. No. 5,118,027 to Braun et al.; U.S. Pat. No. 5,161,257 to Yung; U.S. Pat. No. 5,293,006 to Yung; U.S. Pat. No. 5,323,947 to Juskey et al.; U.S. Pat. No. 5,447,264 to Koopman et al.; U.S. Pat. No. 5,539,153 to Schwiebert; U.S. Pat. No. 5,672,542 to Schwiebert; U.S. Pat. No. 5,738,269 to Masterton; U.S. Pat. No. 5,829,668 to George et al.; U.S. Pat. No. 5,938,106 to Pierson; U.S. Pat. No. 6,053,397 to Kaminski; U.S. Pat. No. 6,053,398 to Iizuka et cl.; U.S. Pat. No. 6,056,191 to Brouillette et al.; U.S. Pat. No. 6,085,968 to Swindlehurst et al.; U.S. Pat. No. 6,109,507 to Yagi et al.

SUMMARY OF THE INVENTION

[0004] The present invention seeks to provide improved apparatus and methods for forming high density solder bumps on semiconductor substrates.

[0005] There is thus provided in accordance with a preferred embodiment of the present invention a method for forming bumps on an integrated circuit comprising employing a scanning direct laser imager to selectably expose a photosensitive layer deposited on an integrated circuit substrate thereby to define regions overlying selected portions of the integrated circuit substrate; developing the photosensitive layer thereby to selectively remove the photosensitive layer at the regions; and applying a solder composition to the predetermined regions, thereby to define solder bumps overlying the selected portions of the integrated circuit substrate.

[0006] Preferably the photosensitive layer is a solder mask.

[0007] Preferably the exposed regions have a spatial density which exceeds a spatial density which is realizable using an exposure mask.

[0008] Alternatively and additionally the exposed regions of photoresist preferably produce apertures having walls whose perpendicularity to a surface of the integrated circuit substrate exceeds the perpendicularity which is realizable using an exposure mask.

[0009] Moreover, in accordance with a preferred embodiment of the invention the employing a scanning laser direct imager, developing the photosensitive layer, and applying a solder composition take place waferwise prior to dicing of the integrated circuit substrate into individual dies.

[0010] Preferably, the electrical circuit is an integrated circuit and the substrate comprises a semiconductor substrate.

[0011] Additionally, in accordance with a preferred embodiment of the invention metal bases, providing an underbump metalization, are formed to overlay selected portions of the integrated circuit substrate, and the regions exposed in the photosensitive layer overly the bases.

[0012] Preferably the metal bases are formed by depositing a metal layer on the substrate; coating the metal layer with a photoresist; selectively exposing the photoresist to define a multiplicity of locations on the photoresist; developing the exposed photoresist and removing the photoresist other than at predetermined locations, thereby to expose the metal layer other than at the predetermined locations; and etching the metal layer to remove the metal layer other than at the predetermined locations to define a multiplicity of metal bases formed on the substrate.

[0013] Preferably, the substrate and the metal bases thereon are both coated with a layer of photosensitive solder mask used in the formation of solder bumps.

[0014] There is thus provided in accordance with a preferred embodiment of the present invention a system for forming bumps on an integrated circuit comprising a scanning laser direct imager selectably exposing a photosensitive layer deposited on an integrated circuit substrate thereby to define regions in the photosensitive layer overlying selected portions of the integrated circuit substrate; a developer developing the photosensitive layer to selectively remove the photosensitive layer at the defined regions; and a solder applicator applying a solder composition to the defined regions, thereby to define bumps overlying the selected portions of the integrated circuit substrate.

[0015] Preferably the photosensitive layer is a solder mask.

[0016] Preferably the direct laser imager defines exposed regions having a spatial density which exceeds a spatial density which is realizable using an exposure mask.

[0017] Alternatively and additionally the direct laser imager preferably defines exposed regions of the photosensitive layer to produce apertures having walls whose perpendicularity to a surface of the integrated circuit substrate exceeds the perpendicularity which is realizable using an exposure mask.

[0018] Preferably the developer and the solder applicator operate waferwise prior to dicing of the integrated circuit substrate into individual dies.

[0019] Preferably the electrical circuit comprises an integrated circuit and the substrate comprises a semiconductor substrate.

[0020] In accordance with a preferred embodiment of the invention, the system for forming bumps on an integrated circuit substrate includes: a laser emitting laser light; a modulator receiving the laser light and modulating the laser light in accordance with control data received from a controller; and a polygonal mirror receiving the modulated laser and scanning the modulated laser light to expose the photoresist in a predetermined pattern.

[0021] Preferably the system further includes a metal base applier applying metal bases overlying selected portions of the integrated circuit substrate and wherein the regions overly the bases.

[0022] Preferably the metal base applier includes: a metal layer depositer depositing a metal layer on the substrate; a photoresist coater coating the metal layer with a photoresist; a laser direct imaging system selectively exposing the photoresist to define a multiplicity of locations; a developer developing the exposed photoresist and removing the photoresist other than at the locations, thereby to expose the metal layer other than at the locations; and an etcher removing the metal layer other than at the locations to define a multiplicity of metal bases formed on the substrate.

[0023] Preferably the system further includes a photosensitive layer coater coating the substrate and the metal bases thereon with a layer of photosensitive solder mask.

[0024] In accordance with a preferred embodiment of the invention, the system includes a laser emitting laser light; a modulator receiving the laser light and modulating the laser light in accordance with control data received from a controller; and a polygonal mirror receiving the modulated laser and scanning the modulated laser light to expose the photoresist in a predetermined pattern.

[0025] There is thus provided in accordance with a preferred embodiment of the invention a method for forming bumps on an integrated circuit, comprising: exposing a first photosensitive layer deposited on an integrated circuit substrate thereby to define regions in the photosensitive layer overlying selected portions of the integrated circuit substrate; applying a second photosensitive coating to the integrated circuit substrate; employing a scanning laser direct imaging system to expose the second photosensitive coating to define apertures in the second photosensitive coating generally overlying the portions; processing the second photosensitive coating to form apertures therein; and applying a solder composition to the apertures to form bumps. Preferably the bumps overly the selected portions of the integrated circuit.

[0026] There is thus provided in accordance with another preferred embodiment of the present invention a method for forming a portion of an electrical circuit on an integrated circuit substrate comprising: loading a first integrated circuit substrate and at least a second integrated circuit substrate onto a laser pattern exposure system; and exposing a selected portion of a photosensitive layer deposited on the second integrated circuit substrate prior to completing an exposure sequence exposing part of an electrical circuit pattern to be formed on a photosensitive layer deposited on the first integrated circuit substrate.

[0027] There is thus provided in accordance with still another preferred embodiment of the present invention a method for forming a portion of an electrical circuit on an integrated circuit substrate comprising: loading an integrated circuit substrate onto a laser pattern exposure system, wherein the substrate has formed on a surface thereof at least part of an integrated circuit pattern and a fiducial pattern having a known geometry with reference to the integrated circuit pattern, and the substrate is at least partially coated with a photosensitive coating; ascertaining the location of the fiducial pattern; adjusting digital data representing a portion of an electrical circuit to be formed on the integrated circuit substrate according the location of the fiducial pattern; and exposing a selected portion of the photosensitive layer with a laser beam according to a pattern supplied by the adjusted digital data.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The present invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:

[0029]FIGS. 1A, 1B, 1C, 1D, 1E, 1F, 1G & 1H are simplified pictorial illustrations illustrating various stages in a methodology for waferwise formation of solder bumps on an integrated circuit in accordance with a preferred embodiment of the present invention; and

[0030]FIGS. 2A and 2B are together a simplified pictorial illustration of various process steps employed in the methodology of FIGS. 1A-1H.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

[0031] Reference is now made to FIGS. 1A, 1B, 1C, 1D, 1E, 1F, 1G & 1H which are simplified pictorial illustrations illustrating various stages in a methodology for waferwise formation of solder bumps on an integrated circuit in accordance with a preferred embodiment of the present invention and to FIGS. 2A and 2B, which are together a simplified pictorial illustration of various process steps employed in the methodology of FIGS. 1A-1G.

[0032] As seen in FIG. 2A, a conventional silicon wafer 100, coated with a metallic base layer 102, as by sputtering or any other suitable technique, and formed of copper and/or chromium and/or nickel and/or other suitable material, shown at reference numeral 104 in FIG. 2A, is further coated with a layer 106 of suitable photoresist, as shown at reference numeral 108 in FIG. 2A. The photoresist layer 106 is exposed, preferably by laser direct imaging thereon to define an array 110 of solder bump locations 112, as shown at reference numeral 114. Solder bump locations 112 are positioned at predetermined selected portions of wafer 100 so that solder bumps formed at solder bumb locations 112 are in communication with an electrical circuit formed on wafer 100. It is appreciated that other conventional systems, for example steppers in combination with stencil masks or reticules, may be employed to expose photoresist layer 106 and define array 110.

[0033] As seen particularly in FIG. 1A, the exposure of the photoresist layer 106 on wafer 100 preferably is carried out using a scanning laser direct imaging system 115, preferably employing a polygonal mirror 116, which receives suitably modulated laser light via suitable optics 118, typically including a substantially telecentric scan lens 119, from a modulator 120. Modulator 120 is operative to data modulate light received from a laser 122 in accordance with control data received from a controller 121. The control data preferably is digital data representing a pattern of bump locations 112 to be imaged onto photoresist layer 106.

[0034] It is also seen at reference numeral 114 in FIG. 2A that patterns may be exposed on two wafers simultaneously, such that exposure of a selected portion of the photosensitive layer 106 deposited on one of the wafers may be commenced prior to completing an exposure sequence to expose an electrical circuit pattern to be formed on the photosensitive layer deposited the other wafer. Depending on the relative size of wafers 100 and the capacity of scanning laser direct imaging system 115, more than two wafers may be exposed simultaneously.

[0035] It is to be noted that the arrays 110 of solder bump locations 112, as well as the relative sizes of wafer 100 and laser direct imaging system 115, are not shown to scale in FIGS. 1A-2B out of considerations of clarity. Arrays 110 typically are in fact substantially smaller than shown, and may be distributed evenly, or not evenly, over substrate 100 in correlation to the location of integrated circuits formed on wafer 100.

[0036] Referring now to FIG. 1B, it is seen that following the exposure step of FIG. 1A, the photoresist layer 106 is developed to remove layer 106 other than at the solder bump locations 112. This developing stage is shown in FIG. 2A at reference numeral 124.

[0037] Following stage 124 shown in FIG. 2A, and also seen at FIG. 1B, the exposed base layer 102, not covered by the photoresist layer 106, which is only present at the bump locations 112, is etched away, as shown in FIG. 2A at reference numeral 126 and thereafter, the remaining photoresist layer 106 is stripped, to leave an array 128 of disks 130. Each disk 130 preferably forms an underbump metalization for a subsequently deposited solder bump, and each disk 130 overlays a bump location 112, as shown in FIG. 1C, corresponding to an appropriate location in an electrical circuit formed on wafer 100. It is appreciated that a preferred method for generating array 128 of disks 130, which typically are required to facilitate bonding of bumps to silicon wafer 100, includes a photolithography process employing a scanning laser direct imaging system as described hereinabove. Nevertheless, disks 130 may be formed using any other suitable process, for example direct deposit through stencils or a photolithography process employing a stepper and a suitable stencil mask or reticule.

[0038] As seen in FIG. 1D and at reference numeral 132 in FIG. 2B, a further photosensitive layer 134, such as a layer of photosensitive solder mask, is evenly deposited over the exposed wafer 100 and over the array 128 of disks 130, which corresponds to array 110 of bump locations 112.

[0039] It is a feature of the present invention that the photosensitive solder mask layer 134 is then exposed, preferably by laser direct imaging thereon, preferably employing system 115, to define an array 136 of aperture locations 138 in the photosensitive layer 134, each in registration with a corresponding solder bump location 112. It is appreciated that registration of aperture locations 138 needs to be very accurate.

[0040] A suitable technique for providing mutual registration of aperture locations 138, bump locations 112, and locations in an electrical circuit deposited on wafer 100 includes acquiring an image of a pattern formed of one or more fiducial markings (not shown) on wafer 100, for example with a CCD sensor (not shown) and ascertaining the location of the fiducial patterns. Digital data representing a pattern to be exposed on the surface of wafer 100 is dynamically aligned, and as necessary scaled and stretched, with reference to the pattern of fiducial markings, in order to pattern fit the locations to be recorded by system 115 to actual locations on wafer 100. It is appreciated that in such a system the pattern of fiducial markings has a known geometry with reference to an electrical circuit pattern.

[0041] A preferred method for precisely calibrating sensors employed to image fiducials and ascertain their location, used in registration and alignment in a scanning laser direct imaging system, is described in Applicant's copending U.S. patent application Ser. No. 09/798,160. A preferred method for dynamically scaling data in a scanning laser direct imaging system is described in Applicant's published PCT patent application WO/0002424. The disclosures of these references are incorporated herein by reference.

[0042] As seen particularly in FIG. 1D and at reference numeral 140 in FIG. 2B, the exposure of the photoresist layer 134 on wafer 100 is preferably carried out using a scanning laser direct imaging system 115, which may be identical to the system employed for exposing photoresist layer 106 (FIG. 1A), preferably employing a polygonal mirror 116, which receives suitably data modulated laser light via suitable optics 118, typically including a telecentric scan lens 119, from a modulator 120. Modulator 120 is operative to modulate light received from a laser 122 in accordance with control data received from a controller 121.

[0043] It is also seen in FIG. 2B that patterns may be exposed on two wafers simultaneously, such that exposure of a selected portion of the photosensitive layer deposited on one of the wafers may be exposed prior to completing an exposure sequence to expose an electrical circuit pattern to be formed on the photosensitive layer deposited the other wafer. Depending on the relative size of wafers 100 and the capacity of scanning laser direct imaging system 115, more than two wafers may be exposed simultaneously.

[0044] Referring now to FIG. 1E, it is seen that following the exposure step of FIG. 1D, the photosensitive layer 134 is developed to selectively remove photosensitive layer 134 at the aperture locations 138 which are in registration with the disks 130 providing an underbump metalization and located at the solder bump locations 112 (FIG. 1A), thereby providing apertures 142. This developing stage is shown in FIG. 2B at reference numeral 144.

[0045] It is appreciated that scanning laser direct imaging system 115 typically employs highly telecentric optics, such as scan lens 119, and a highly collimated focused laser beam to expose the photosensitive solder mask in a dense raster pattern. Consequently, the inventors believe that scanning laser direct imaging system 115 is capable of producing apertures 142 in the solder mask 134 whose walls have a perpendicularity to a surface of the integrated circuit substrate (wafer 100) that exceeds the perpendicularity that is realizable using exposure masks and reticules in a conventional solder mask exposure system, such as with a stepper.

[0046] Moreover, the inventors believe that a scanning laser direct imaging system 115 is able to produce arrays 136 of apertures 142 that have a spatial density that exceeds the spatial density realizable using exposure masks and reticules to expose solder mask 134 in a conventional solder mask exposure system, such as with a stepper

[0047] Following the stage shown in FIG. 1E, the apertures 142 are filled with a precise volume of a solder compound 146, for example in the form of a solder paste 147, as shown in FIG. 1F and at reference numeral 148 in FIG. 2B. Solder compound 146 may be a conventional composition of tin and/or lead solder, or may include gold or any other metal suitable for establishing a bonding electrical contact between an integrated circuit and a carrier substrate.

[0048] Thereafter, the remaining photosensitive layer 134 is stripped, for example by washing away the solder mask, to leave an array 150 of solder deposits 152, each overlying a corresponding disk 128 at a bump location 112, as shown in FIG. 1G.

[0049] As a final stage, the array 150 of solder deposits 152 may be subjected to reflow, for example by any suitable processes such as sonic vibration or heating, as shown at reference numeral 154 in FIG. 2B, thereby to define an array 156 of solder bumps 158, each having a generally predeteremined uniform shape and precise volume, in registration with disks 128 at respective bump locations 112 (FIG. 1A).

[0050] It is a particular feature of the present invention that the exposure functionality of exposing photosensitive solder mask layer 134, and preferably additionally photoresist layer 106, employed in the present invention may be carried out by a laser direct imaging raster scanning system. Such systems, employed in the generation of conductor patterns on printed circuit boards, are commercially available from the present assignee, Orbotech Ltd. of Yavne, Israel under the model designation DP-100, and may be suitably adapted to accommodate the exposure of silicon wafers 100.

[0051] The inventors believe that the use of such laser direct imaging raster scanning systems offer several advantages including: the option of using the large bed of a laser direct imaging raster scanning system (typically at least 24″ wide) to simultaneously expose several wafers; on-the-fly scaling of exposure patterns to be recorded, preferably provided by digital exposure data, on any of the photosensitive surfaces deposited on wafer 100, recordation of different exposure patterns, forming different structures of arrays 156, at different regions along the surface of wafer 100; recordation of exposure patterns on wafer 100 without the use of masks; recordation of exposure patterns on wafer 100 directly from digital data representing a pattern of bump locations or aperture locations to be exposed.

[0052] It is appreciated that the waferwise formation of solder bumps described hereinabove may take place prior to, subsequent to or any any suitable stage with respect to formation of integrated circuits on a given wafer. Preferably, the formation of bumps takes place prior to dicing a wafer into individual dies. Moreover solder bumps may be formed on the same side and same layer of a wafer as an integrated circuit formed thereon (the front end) or on the same side of the wafer but on a different layer than an integrated circuit formed thereon (the back end), or on an opposite side of the wafer altogether. It is also appreciated that aspects of the present invention may be applicable to non-waferwise formation of solder bumps.

[0053] It is appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described hereinabove. Rather the present invention includes modifications and variations thereof which would occur to a person of skill in the art upon reading the foregoing description and which are not in the prior art.

Classifications
U.S. Classification228/214, 228/33, 228/256, 228/259, 257/E21.508, 228/36
International ClassificationB23K1/005, H01L21/60
Cooperative ClassificationH01L2924/14, B23K2201/40, H01L24/11, H01L2224/13099, H01L2924/01079, H01L2924/01013, H01L2924/01082, H01L2924/01029, B23K1/0056, H01L2924/01033, H01L2924/01024, H01L2924/014
European ClassificationH01L24/11, B23K1/005R
Legal Events
DateCodeEventDescription
Sep 7, 2010FPExpired due to failure to pay maintenance fee
Effective date: 20100716
Jul 16, 2010LAPSLapse for failure to pay maintenance fees
Feb 22, 2010REMIMaintenance fee reminder mailed
Dec 27, 2005FPAYFee payment
Year of fee payment: 4
Jan 22, 2001ASAssignment
Owner name: ORBOTECH LTD., ISRAEL
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WAXLER, SCOTT STEVEN;ZEMER, DAN;REEL/FRAME:011480/0968
Effective date: 20010118
Owner name: ORBOTECH LTD. P.O. BOX 215 YAVNE 81102 ISRAEL
Owner name: ORBOTECH LTD. P.O. BOX 215YAVNE 81102, (1) /AE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WAXLER, SCOTT STEVEN /AR;REEL/FRAME:011480/0968
Owner name: ORBOTECH LTD. P.O. BOX 215 YAVNE 81102 ISRAEL
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WAXLER, SCOTT STEVEN;ZEMER, DAN;REEL/FRAME:011480/0968
Effective date: 20010118
Owner name: ORBOTECH LTD. P.O. BOX 215YAVNE 81102, (1) /AE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WAXLER, SCOTT STEVEN /AR;REEL/FRAME:011480/0968
Effective date: 20010118