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Publication numberUS20020096704 A1
Publication typeApplication
Application numberUS 09/333,687
Publication dateJul 25, 2002
Filing dateJun 16, 1999
Priority dateJan 7, 1999
Also published asUS6441426
Publication number09333687, 333687, US 2002/0096704 A1, US 2002/096704 A1, US 20020096704 A1, US 20020096704A1, US 2002096704 A1, US 2002096704A1, US-A1-20020096704, US-A1-2002096704, US2002/0096704A1, US2002/096704A1, US20020096704 A1, US20020096704A1, US2002096704 A1, US2002096704A1
InventorsAtsushi Fukumoto, Natsuo Ajika
Original AssigneeAtsushi Fukumoto, Natsuo Ajika
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Nonvolatile semiconductor memory device and method of manufacturing the same
US 20020096704 A1
Abstract
In a semiconductor substrate surface, first and second trenches extending in parallel with each other in a bit line direction are provided. An insulation film for trench isolation is filled in the first and second trenches. A floating gate is provided between the first and second trenches on the semiconductor substrate. A sidewall spacer is provided on a sidewall surface, extending in the bit line direction, of the floating gate.
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Claims(14)
What is claimed is:
1. A nonvolatile semiconductor memory device, comprising:
a semiconductor substrate;
first and second trenches provided in a surface of said semiconductor substrate and extending in parallel with each other in a bit line direction;
an oxide film for trench isolation filled in said first and second trenches;
a floating gate provided between said first and second trenches on said semiconductor substrate; and
a sidewall spacer provided on a sidewall surface, extending in the bit line direction, of said floating gate.
2. The nonvolatile semiconductor memory device according to claim 1, wherein
said sidewall spacer is provided on sidewall surfaces, extending in the bit line direction, on both sides of said floating gate.
3. The nonvolatile semiconductor memory device according to claim 1, wherein
said sidewall spacer is formed of polysilicon.
4. The nonvolatile semiconductor memory device according to claim 3, wherein
an n type impurity is implanted in said polysilicon.
5. The nonvolatile semiconductor memory device according to claim 1, wherein
said sidewall spacer increases in thickness from top to bottom.
6. The nonvolatile semiconductor memory device according to claim 1, wherein
said sidewall surface, extending in the bit line direction, of said floating gate is coplanar with a sidewall surface of said trench.
7. The nonvolatile semiconductor memory device according to claim 1, wherein
said insulation film for trench isolation is formed of a CVD insulation film of which material is TEOS.
8. A method of manufacturing a nonvolatile semiconductor memory device, comprising the steps of:
successively forming a tunnel insulation film and a first conductive layer on a semiconductor substrate;
patterning said first conductive layer and said tunnel insulation film in a bit line direction to form an uncompleted floating gate extending in the bit line direction and to form a trench in a surface of said semiconductor substrate in a self-alignment manner with the uncompleted floating gate;
filling an insulation film for trench isolation in said trench;
forming a sidewall spacer on a sidewall of said floating gate;
successively forming an insulation film and a second conductive layer on said semiconductor substrate to cover said uncompleted floating gate; and
patterning said second conductive layer, said insulation film and said uncompleted floating gate in a word line direction to form a completed floating gate and a control gate.
9. The method of manufacturing a nonvolatile semiconductor memory device according to claim 8, wherein
said sidewall spacer is formed of polysilicon.
10. The method of manufacturing a nonvolatile semiconductor memory device according to claim 9, wherein
the step of forming said sidewall spacer includes
forming a polysilicon layer on said semiconductor substrate to cover said uncompleted floating gate, and
carrying out isotropic etching of said polysilicon layer.
11. The method of manufacturing a nonvolatile semiconductor memory device according to claim 8, wherein
said insulation film is formed of a thin laminate film of an oxide film, a nitride film and an oxide film.
12. The method of manufacturing a nonvolatile semiconductor memory device according to claim 8, wherein
said insulation film for trench isolation is formed of a CVD oxide film of which material is TEOS.
13. The method of manufacturing a nonvolatile semiconductor memory device according to claim 8, wherein
said first conductive layer is formed of a polysilicon layer or an amorphous silicon layer.
14. The method of manufacturing a nonvolatile semiconductor memory device according to claim 8, wherein
said second conductive layer is formed of polysilicon.
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    The present invention generally relates to nonvolatile semiconductor memory devices and more particularly to a nonvolatile semiconductor memory device using trench isolation. The present invention also relates to a method of manufacturing such a nonvolatile semiconductor memory device.
  • [0003]
    2. Description of the Background Art
  • [0004]
    [0004]FIG. 6 is a plan view of a conventional nonvolatile semiconductor memory device using trench isolation. FIG. 7 shows a cross section (A) along the line A-A of FIG. 6, and a cross section (B) along the line C-C of FIG. 6.
  • [0005]
    Referring to these figures, the conventional nonvolatile semiconductor memory device includes a semiconductor substrate 1. In a main surface of semiconductor substrate 1, a linear trench 2 for trench isolation is formed in the direction Y of bit lines. An insulation film 24 for trench isolation is filled in trench 2. Trench 2 and insulation film 24 filled therein constitute a trench isolation region. On both sides of trench 2, a floating gate 4 is provided on semiconductor substrate 1 with a tunnel oxide film 3 therebetween. On floating gate 4, a control gate 6 is provided with an inter poly-insulation film 5 therebetween.
  • [0006]
    Referring next to FIG. 8, the operation of the nonvolatile semiconductor memory device will be described.
  • [0007]
    Here, the Fowler-Nordheim tunnel current writing method at a memory drain edge and the Fowler-Nordheim tunnel current erasing method on the entire channel surface, which are common to DINOR type flash memories, will be described.
  • [0008]
    Whether information is stored or not is determined by the charged and discharged states of a floating gate. When a floating gate is injected with electrons and negatively charged, Vth becomes higher with respect to the potential of a control gate thereon (erased state). When the floating gate is not negatively charged, however, Vth is low (written state). By applying, to the control gate, an intermediate voltage between Vth in the erased state and Vth in the written state, stored contents can be read through a memory cell transistor.
  • [0009]
    Writing can be performed on a basis of a bit by selecting a sub bit line (drain interconnection) and a word line (gate interconnection). Since an erase voltage can be applied on a basis of a word line (gate interconnection), erasing can be performed on a basis of a sector.
  • [0010]
    Since a floating gate electrode is covered by a high quality insulation film, injected electrons remain in the electrode unless erased. Accordingly, stored contents are maintained even if the power supply is turned off.
  • [0011]
    A conventional method of manufacturing the nonvolatile semiconductor memory device using trench isolation will be described in the following with reference to the figures.
  • [0012]
    In the figures described hereinafter, cross sections on the left side correspond to the cross section along the line A-A of FIG. 6, and those on the right side correspond to the cross section along the line C-C.
  • [0013]
    Referring to FIG. 9, a surface of semiconductor substrate (silicon substrate) 1 is oxidized to form tunnel insulation film 3 which is approximately 100 nm in film thickness. On tunnel insulation film 3, a polysilicon film 7 or amorphous silicon film (approximately 200 nm) doped with an n type impurity such as phosphorus, and a CVD oxide film 8 (approximately 100 nm) are successively deposited.
  • [0014]
    Referring to FIG. 10, a resist pattern 9 is formed by photo lithography, which has openings in portions in which first and second trenches extending in parallel with each other in the bit line direction are to be formed. Referring to FIGS. 9 and 10, resist pattern 9 is used for patterning in the bit line direction, oxide film 8, polysilicon film 7 and tunnel oxide film 3 are etched in this order, and trench 2 which is approximately 500 nm in depth is formed in the surface of semiconductor substrate 1. Thus, trench 2 is formed in a self-alignment manner with an uncompleted floating gate 4. Then, resist pattern 9 and oxide film 8 are removed.
  • [0015]
    Referring to FIGS. 10 and 11, a CVD insulation film 24 such as tetraethoxysilane (TEOS) is filled in trench 2. CVD insulation film 24 is etched to the surface of semiconductor substrate 1 such as by chemical mechanical polishing (CMP) to form uncompleted floating gate 4 which extends in the bit line direction. Then, an ONO film (thin laminate film formed of a CVD oxide film of approximately 5 nm/a CVD nitride film of approximately 5 nm/a CVD oxide film of approximately 5 nm) 5 is formed to cover floating gate 4.
  • [0016]
    Referring to FIG. 12, polysilicon 13 (approximately 50 nm) doped with an n type impurity such as phosphorus, a refractory metal silicide 14 (approximately 50 nm) such as WSi, and a CVD oxide film 15 (approximately 100 nm) such as TEOS are successively deposited. On CVD oxide film 15, a resist pattern 16 for forming a control gate is formed.
  • [0017]
    Referring to FIGS. 12 and 13, CVD oxide film 15, refractory metal silicide 14, polysilicon 13, ONO film 5, and uncompleted floating gate 4 are etched in this order to complete floating gate 4 and control gate 6.
  • [0018]
    Referring to FIG. 14, a portion other than a region to be a drain region is masked by a resist pattern 17 and subjected to ion implantation to form a drain region 18.
  • [0019]
    Referring to FIGS. 15 and 16, a portion other than a region to be a source region is masked and subjected to ion implantation to form a source region 19.
  • [0020]
    Referring to FIG. 17, a bit line 20 is formed, first and second Al interconnections 21 and 22 are formed thereon with interlayer insulation films 28 and 29 therebetween, and a glass coating 23 is formed. Thus, a memory cell transistor is completed.
  • [0021]
    Since the conventional method of manufacturing the nonvolatile semiconductor memory device is as described above, problems occur as described below.
  • [0022]
    In FIG. 18, (A) and (B) are cross sections along the lines A-A and B-B of FIG. 6 in the step of FIG. 13 (a bit line contact is omitted herein).
  • [0023]
    Referring to FIGS. 18 and 13, when the trench formed in a self-alignment manner with floating gate 4 is used for isolation, problems occur in etching control gate (memory gate) 6 and also etching uncompleted floating gate 4. That is, in the cross section along the line B-B shown in (B) of FIG. 18, oxide film 24 for trench isolation in trench 2 may be etched, causing a side surface of semiconductor substrate 1, that is, a side surface of trench 2 (a portion 50 indicated by a circle in the figure) to be exposed. As described above, exposure of the side surface of semiconductor substrate 1 prevents isolation characteristics to be maintained sufficiently.
  • [0024]
    Referring to (A) of FIG. 18, there is also a problem of electric field concentration on inter poly-insulation film 5 between floating gate 4 and control gate 6 because an upper end of floating gate 4 (portion 51 indicated by a circle in the figure) is angular and sharp.
  • SUMMARY OF THE INVENTION
  • [0025]
    The present invention was made to solve the problems as described above, and its object is to provide an improved nonvolatile semiconductor memory device so as to be able to maintain isolation characteristics sufficiently.
  • [0026]
    Another object of the present invention is to provide an improved nonvolatile semiconductor memory device so as not to concentrate electric fields on an inter poly-insulation film between a floating gate and a control gate.
  • [0027]
    Further object of the present invention is to provide a method of manufacturing an improved nonvolatile semiconductor memory device so as to be able to maintain isolation characteristics.
  • [0028]
    Still another object of the present invention is to provide a method of manufacturing an improved nonvolatile semiconductor memory device so as not to concentrate electric fields on an inter poly-insulation film between a floating gate and a control gate.
  • [0029]
    A nonvolatile semiconductor memory device according to a first aspect of the present invention includes a semiconductor substrate. In a surface of the semiconductor substrate, first and second trenches, which extend in parallel with each other in a bit line direction, are provided. An oxide film for trench isolation is filled in the first and second trenches. Between the first and second trenches, a floating gate is provided on the semiconductor substrate. A sidewall spacer is provided on a sidewall surface, extending in the bit line direction, of the floating gate.
  • [0030]
    According to the present invention, the sidewall spacer is provided on the sidewall surface, extending in the bit line direction, of the floating gate, and therefore an angular portion of the floating gate is rounded, preventing concentration of electric fields on an inter poly-insulation film.
  • [0031]
    According to the nonvolatile semiconductor memory device in a second aspect of the present invention, the sidewall spacer is provided on sidewall surfaces, extending in the bit line direction, on both sides of the floating gate.
  • [0032]
    According to the nonvolatile semiconductor memory device in a third aspect of the present invention, the sidewall spacer is formed of polysilicon.
  • [0033]
    According to the nonvolatile semiconductor memory device in a fourth aspect of the present invention, an n type impurity is implanted in the polysilicon.
  • [0034]
    According to the nonvolatile semiconductor memory device in a fifth aspect of the present invention, the sidewall spacer increases in thickness from top to bottom.
  • [0035]
    According to the nonvolatile semiconductor memory device in a sixth aspect of the present invention, the sidewall surface, extending in the bit line direction, of the floating gate is coplanar with a sidewall surface of the trench.
  • [0036]
    According to the nonvolatile semiconductor memory device in a seventh aspect of the present invention, the oxide film for trench isolation is formed of a CVD insulation film of which material is TEOS.
  • [0037]
    In a method of manufacturing a nonvolatile semiconductor memory device according to an eighth aspect of the present invention, a tunnel insulation film and a first conductive layer are first successively formed on a semiconductor substrate. The first conductive layer and the tunnel insulation film are patterned in a bit line direction to form an uncompleted floating gate extending in the bit line direction and to form a trench in a surface of the semiconductor substrate in a self-alignment manner with the uncompleted floating gate. An insulation film for trench isolation is filled in the trench. A sidewall spacer is formed on a sidewall of the floating gate. On the semiconductor substrate, an insulation film and a second conductive layer are successively formed to cover the uncompleted floating gate. The second conductive layer, the insulation film and the uncompleted floating gate are patterned in a word line direction to form a completed floating gate and a control gate.
  • [0038]
    According to the present invention, the sidewall spacer is formed on the sidewall of the floating gate. Accordingly, a trench sidewall is not exposed even if the isolation insulation film in the trench is etched in etching the control gate (memory gate) and the uncompleted floating gate. As a result, a nonvolatile semiconductor memory device with isolation characteristics maintained is obtained.
  • [0039]
    According to the method of manufacturing a nonvolatile semiconductor memory device in a ninth aspect of the present invention, the sidewall spacer is formed of polysilicon.
  • [0040]
    In the method of manufacturing a nonvolatile semiconductor memory device in a tenth aspect of the present invention, the step of forming the sidewall spacer includes forming a polysilicon layer on the semiconductor substrate to cover the uncompleted floating gate, and carrying out isotropic etching of the polysilicon layer.
  • [0041]
    According to the method of manufacturing a nonvolatile semiconductor memory device in an eleventh aspect of the present invention, the insulation film is formed of a thin laminate film of an oxide film, a nitride film and an oxide film.
  • [0042]
    In the method of manufacturing a nonvolatile semiconductor memory device according to a twelfth aspect of the present invention, the insulation film for trench isolation is formed of a CVD oxide film of which material is TEOS.
  • [0043]
    In the method of manufacturing a nonvolatile semiconductor memory device according to a thirteenth aspect of the present invention, the first conductive layer is formed of a polysilicon layer or an amorphous silicon layer.
  • [0044]
    In the method of manufacturing a nonvolatile semiconductor memory device according to a fourteenth aspect of the present invention, the second conductive layer is formed of polysilicon.
  • [0045]
    The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0046]
    [0046]FIG. 1 shows a cross section (A) along the line A-A and a cross section (B) along the line C-C of FIG. 6 described below, of a nonvolatile semiconductor memory device according to an embodiment.
  • [0047]
    [0047]FIGS. 2 and 3 are cross sections of a semiconductor device in the first and second steps of a method of manufacturing a nonvolatile semiconductor memory device according to the embodiment.
  • [0048]
    [0048]FIG. 4 is a cross section for describing the effects of the nonvolatile semiconductor memory device according to the embodiment.
  • [0049]
    [0049]FIG. 5 is a cross section for describing the effects of the method of manufacturing a nonvolatile semiconductor memory device according to the embodiment.
  • [0050]
    [0050]FIG. 6 is a plan view of the nonvolatile semiconductor memory device according to the embodiment or a conventional nonvolatile semiconductor memory device.
  • [0051]
    [0051]FIG. 7 shows a cross section (A) along the line A-A and a cross section (B) along the line C-C of the conventional nonvolatile semiconductor memory device.
  • [0052]
    [0052]FIG. 8 is a diagram for describing the operation of the conventional nonvolatile semiconductor memory device.
  • [0053]
    FIGS. 9 to 17 are cross sections of a semiconductor device in the first to ninth steps of a conventional method of manufacturing a nonvolatile semiconductor memory device.
  • [0054]
    [0054]FIG. 18 shows a cross section (A) along the line A-A and a cross section (B) along the line B-B of FIG. 6, showing problems with the conventional method of manufacturing a nonvolatile semiconductor memory device.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0055]
    An embodiment of the present invention will be described in the following with reference to the figures.
  • [0056]
    [0056]FIG. 1 is a cross section of a main part of a nonvolatile semiconductor memory device according to an embodiment. The plan view of such a nonvolatile semiconductor memory device according to the embodiment is almost the same as the one shown in FIG. 6.
  • [0057]
    In FIG. 1, (A) is a cross section along the line A-A of FIG. 6, and (3) is a cross section along the line C-C of FIG. 6.
  • [0058]
    Referring to these figures, the nonvolatile semiconductor memory device according to the embodiment includes a semiconductor substrate 1. In a surface of semiconductor substrate 1, first and second trenches 2 a and 2 b are provided which extend in parallel with each other in the direction of bit lines. An oxide film 24 for trench isolation is filled in first and second trenches 2 a and 2 b. A floating gate 4 is provided on semiconductor substrate 1 and between first and second trenches 2 a and 2 b.
  • [0059]
    A sidewall spacer 25 is provided on a sidewall surface, extending in the bit line direction, of floating gate 4. Sidewall spacer 25 is provided on sidewall surfaces, extending in the bit line direction, on both sides of floating gate 4. Sidewall spacer 25 is formed of polysilicon implanted with an n type impurity. Sidewall spacer 25 increases in thickness from top to bottom. A sidewall surface, extending in the bit line direction, of floating gate 4, is coplanar with a sidewall surface of trenches 2 a and 2 b. Oxide film 24 for trench isolation is formed of a CVD insulation film of which material is TEOS.
  • [0060]
    To cover sidewall spacer 25 and floating gate 4, an ONO film 5 serving as an inter poly-insulation film is formed on semiconductor substrate 1. A control gate 6 covers floating gate 4 and sidewall spacer 25 with ONO film 5 therebetween. Since other formation is similar to that of the conventional device shown in FIG. 7, the same or corresponding parts are denoted by the same reference characters and their description will not be repeated.
  • [0061]
    According to the nonvolatile semiconductor memory device in the embodiment, conductive sidewall spacers 25 are provided on the sidewalls of floating gate 4, and angular portions at an upper surface of the conductor formed by sidewall spacer 25 and floating gate 4 are rounded. Accordingly electric field concentration is not caused on inter poly-insulation film 5 between floating gate 4 and control gate 6. Further, the area in which floating gate 4 and control gate 6 are in contact with each other with inter poly-insulation film 25 therebetween increases, improving the memory cell coupling ratio.
  • [0062]
    A method of manufacturing the nonvolatile semiconductor memory device according to the embodiment will be described in the following.
  • [0063]
    Steps similar to the conventional steps shown in FIGS. 9 and 10 are carried out first. A resist pattern 9 and a CVD oxide film 8 are removed.
  • [0064]
    Referring to FIG. 2, oxide film 24 for trench isolation is then filled in trench 2. Thereafter, polysilicon 26 doped with an n type impurity such as phosphorus is deposited on semiconductor substrate 1.
  • [0065]
    Referring to FIGS. 2 and 3, polysilicon 26 is subjected to isotropic etching. Thus, sidewall spacers 25 are formed on the sidewalls of floating gate 4. Then, steps similar to the ONO film formation step shown in FIG. 11 and the conventional steps shown in FIGS. 12 to 17 are carried out to complete a nonvolatile semiconductor memory device. The effects will be described in the following.
  • [0066]
    [0066]FIG. 4 is a cross section along the line A-A of FIG. 6, showing a main part of the obtained semiconductor device. FIG. 5 is a cross section along the line B-B of FIG. 6, showing a main part of the obtained semiconductor device.
  • [0067]
    According to the embodiment of the present invention, the sidewall surfaces of trench 2 are not exposed even if insulation film 24 for trench isolation is etched, and therefore isolation characteristics are maintained. Further, the planarity of the conductor formed of floating gate 4 and sidewall spacers 25 is improved during word film formation, with reference to FIG. 4. Accordingly, word lines can be patterned easily.
  • [0068]
    As described above, according to the nonvolatile semiconductor memory device of the present invention, the area in which a floating gate and a control gate are in contact with each other increases. Accordingly, a nonvolatile semiconductor memory device with an improved memory cell coupling ratio is obtained.
  • [0069]
    According to the nonvolatile semiconductor memory device of the present invention, the surface shape of the floating gate is smooth, and therefore electric field concentration on an inter poly-insulation film is suppressed.
  • [0070]
    According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, a trench inner wall surface is not exposed even if an insulation film for trench isolation is etched. Accordingly, isolation characteristics can be maintained.
  • [0071]
    According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, the planarity of a floating gate is improved during word line formation, and therefore word lines can be patterned easily.
  • [0072]
    Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
Referenced by
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US6552386 *Sep 30, 2002Apr 22, 2003Silicon-Based Technology Corp.Scalable split-gate flash memory cell structure and its contactless flash memory arrays
US6838725 *Nov 30, 2000Jan 4, 2005Taiwan Semiconductor Manufacturing CompanyStep-shaped floating poly-si gate to improve a gate coupling ratio for flash memory application
US7115940Jul 14, 2003Oct 3, 2006Renesas Technology Corp.Semiconductor device
US7221008 *Oct 6, 2003May 22, 2007Sandisk CorporationBitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory
US7355242Jun 26, 2006Apr 8, 2008Renesas Technology Corp.Semiconductor device
US7381615Nov 23, 2004Jun 3, 2008Sandisk CorporationMethods for self-aligned trench filling with grown dielectric for high coupling ratio in semiconductor devices
US7402886Oct 14, 2005Jul 22, 2008Sandisk CorporationMemory with self-aligned trenches for narrow gap isolation regions
US7416956Oct 14, 2005Aug 26, 2008Sandisk CorporationSelf-aligned trench filling for narrow gap isolation regions
US7439602 *Aug 11, 2004Oct 21, 2008Nec Electronics CorporationSemiconductor device and its manufacturing method
US7615820May 13, 2008Nov 10, 2009Sandisk CorporationSelf-aligned trenches with grown dielectric for high coupling ratio in semiconductor devices
US9082654May 29, 2014Jul 14, 2015Rohm Co., Ltd.Method of manufacturing non-volatile memory cell with simplified step of forming floating gate
US9425203Jun 10, 2015Aug 23, 2016Rohm Co., Ltd.Non-volatile memory cell in semiconductor device
US20010000112 *Nov 30, 2000Apr 5, 2001Taiwan Semiconductor Manufacturing CompanyStep-shaped floating poly-si gate to improve gate coupling ratio for flash memory application
US20050012172 *Aug 11, 2004Jan 20, 2005Kohji KanamoriSemiconductor device and its manufacturing method
US20050072999 *Oct 6, 2003Apr 7, 2005George MatamisBitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory
US20050139908 *Jan 31, 2005Jun 30, 2005Renesas Technology Corp.Semiconductor device
US20050275063 *Jul 14, 2003Dec 15, 2005Renesas Technology Corp.Semiconductor device
US20060108647 *Oct 14, 2005May 25, 2006Yuan Jack HSelf-aligned trench filling for narrow gap isolation regions
US20060108648 *Oct 14, 2005May 25, 2006Yuan Jack HMemory with self-aligned trenches for narrow gap isolation regions
US20070023819 *Jun 26, 2006Feb 1, 2007Renesas Technology Corp.Semiconductor device
US20080157169 *Dec 28, 2006Jul 3, 2008Yuan Jack HShield plates for reduced field coupling in nonvolatile memory
US20080160680 *Dec 28, 2006Jul 3, 2008Yuan Jack HMethods of fabricating shield plates for reduced field coupling in nonvolatile memory
Classifications
U.S. Classification257/315, 257/E27.103, 257/E21.682, 257/E29.304
International ClassificationH01L27/115, H01L21/8247, H01L29/792, H01L29/788
Cooperative ClassificationY10S257/90, H01L29/7883, H01L27/11521, H01L27/115
European ClassificationH01L29/788B4, H01L27/115, H01L27/115F4
Legal Events
DateCodeEventDescription
Jun 16, 1999ASAssignment
Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FUKUMOTO, ATSUSHI;AJIKA, NATSUO;REEL/FRAME:010039/0699
Effective date: 19990521
Feb 3, 2006FPAYFee payment
Year of fee payment: 4
Jan 29, 2010FPAYFee payment
Year of fee payment: 8
Mar 18, 2011ASAssignment
Effective date: 20110307
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MITSUBISHI DENKI KABUSHIKI KAISHA;REEL/FRAME:025980/0219
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN
Apr 4, 2014REMIMaintenance fee reminder mailed
Aug 27, 2014LAPSLapse for failure to pay maintenance fees
Oct 14, 2014FPExpired due to failure to pay maintenance fee
Effective date: 20140827