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Publication numberUS20020105452 A1
Publication typeApplication
Application numberUS 09/746,724
Publication dateAug 8, 2002
Filing dateDec 20, 2000
Priority dateDec 20, 2000
Also published asUS6433714
Publication number09746724, 746724, US 2002/0105452 A1, US 2002/105452 A1, US 20020105452 A1, US 20020105452A1, US 2002105452 A1, US 2002105452A1, US-A1-20020105452, US-A1-2002105452, US2002/0105452A1, US2002/105452A1, US20020105452 A1, US20020105452A1, US2002105452 A1, US2002105452A1
InventorsJohn Clapp, Glen Johnson, Douglas Lebo, Lawrence Swanson
Original AssigneeClapp John S., Johnson Glen A., Lebo Douglas Baird, Swanson Lawrence Peter
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Apparatus and method for precision trimming of a semiconductor device
US 20020105452 A1
Abstract
The present invention provides methods and apparatus for trimming semiconductor devices and circuits, such as pin electronics circuits used in automated test equipment (ATE) systems and the like, without requiring a laser trimming operation. In a preferred embodiment, the present invention addresses the need to precisely adjust a reference current and/or voltage by replacing a conventional current/voltage reference source with a digital-to-analog (D/A) converter. A select switch or mechanism is preferably coupled to the input of the D/A converter and operatively presents a digital input word to the D/A converter by selectively reading the digital word from at least one of a data register and a fuse register. The data register is preferably used during testing of the overall current or voltage reference by iteratively trying various digital input codes while concurrently measuring the analog output signal from the D/A converter until the output signal sufficiently matches a predetermined output value. The fuse register, which comprises a plurality of fusible links, is then preferably blown to permanently store the input code word that provides the desired reference output. During normal operation of the circuit, the select switch preferably reads the D/A converter input word from the fuse register. In this manner, a precise output reference signal is achieved without the need for laser trimming.
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Claims(18)
What is claimed is:
1. A method of precisely trimming a semiconductor circuit comprising the steps of:
providing the circuit with a programmable source including at least one input for receiving a digital input signal, the programmable source being responsive to the digital input signal and selectively generating a corresponding analog output signal;
in a first mode of operation of the circuit, iteratively changing the digital input signal while measuring the corresponding analog output signal until a desired output signal is achieved, the desired output signal substantially matching a predetermined value; and
storing a trimmed digital input signal corresponding to the desired output signal, whereby in a second mode of operation of the circuit, the trimmed digital input signal is operatively coupled to the programmable source for generating the corresponding desired output signal.
2. The method of claim 1, wherein the step of iteratively changing the digital input signal comprises the steps of:
at least temporarily storing the digital input signal in a data register, the programmable source being operatively coupled to the data register in the first mode of operation; and
waiting a predetermined amount of time after changing the digital input signal stored in the data register until measuring the corresponding output signal from the programmable source.
3. The method of claim 1, wherein the step of storing the trimmed digital input signal comprises the step of selectively open-circuiting one or more fusible links included in a fuse register such that the trimmed digital input signal is permanently stored in the fuse register, the input of the programmable source being operatively coupled to the fuse register in the second mode of operation.
4. The method of claim 1, wherein the step of iteratively changing the digital input signal comprises the steps of:
coarsely stepping a binary representation of the digital input signal and measuring the corresponding analog output signal until the output signal is within a predefined window of the predetermined value; and
finely stepping the binary representation of the digital input signal when the corresponding output signal is within the predefined window until the corresponding output signal substantially matches the predetermined value.
5. The method of claim 1, wherein the step of iteratively changing the digital input signal further comprises the steps of:
calculating a difference between the measured analog output signal and the predetermined value for each change in the digital input signal; and
adjusting a coarseness of the change in the digital input signal in response to the difference between the measured analog output signal and the predetermined value, whereby the relative coarseness of the change in the digital input signal for a subsequent iteration is reduced as the difference between the measured output signal and the predetermined value decreases.
6. The method of claim 1, wherein the programmable source is a digital-to-analog converter.
7. A trimmable semiconductor device comprising:
a programmable source including at least one input for receiving a digital input signal, the programmable source being responsive to the digital input signal and selectively generating a corresponding analog output signal; and
a control circuit operatively coupled to the programmable source, the control circuit generating the digital input signal and being operable in at least one of:
a first mode, wherein the control circuit iteratively changes the digital input signal while measuring the corresponding analog output signal from the programmable source until a desired output signal is achieved, the desired output signal substantially matching a predetermined value; and
a second mode, wherein the control circuit fixedly stores a trimmed digital input signal corresponding to the desired output signal generated by the programmable source.
8. The semiconductor device of claim 7, further comprising:
a data register operatively connected to the control circuit and including at least one input for loading the data register with a digital word, the data register at least temporarily storing the digital word; and
a fuse register operatively connected to the control circuit, the fuse register fixedly storing the digital word;
wherein the control circuit operatively connects the data register to the at least one input of the programmable source in the first mode of operation and operatively connects the fuse register to the at least one input of the programmable source in the second mode of operation.
9. The semiconductor device of claim 8, wherein the fuse register comprises a plurality of fusible links, the fusible links being selectively open-circuited to store the trimmed digital input signal.
10. The semiconductor device of claim 7, wherein the first mode is a test mode and the second mode is a normal mode.
11. The semiconductor device of claim 7, wherein the programmable source is a digital-to-analog converter.
12. The semiconductor device of claim 7, wherein the control circuit comprises:
a data register including at least one input for loading the data register with a digital word, the data register at least temporarily storing the digital word;
a fuse register including at least one input for loading the fuse register with a digital word, the fuse register fixedly storing the digital word; and
a select switch including a first input operatively coupled to the data register, a second input operatively coupled to the fuse register and an output operatively coupled to the at least one input of the programmable source, the select switch further including an enable input for receiving a select input signal and selectively connecting at least one of the data register and the fuse register to the programmable source in response to the select input signal.
13. The semiconductor device of claim 12, wherein the select switch operatively connects the data register to the at least one input of the programmable source in the first mode of operation and operatively connects the fuse register to the at least one input of the programmable source in the second mode of operation.
14. A trimmable semiconductor device comprising:
a programmable source including at least one input for receiving a digital input signal, the programmable source being responsive to the digital input signal and selectively generating a corresponding analog output signal;
a data register including at least one input for loading the data register with a digital word, the data register at least temporarily storing the digital word;
a fuse register including at least one input for loading the fuse register with a digital word, the fuse register fixedly storing the digital word; and
a select switch including a first input operatively coupled to the data register, a second input operatively coupled to the fuse register and an output operatively coupled to the at least one input of the programmable source, the select switch further including an enable input for receiving a select input signal and selectively connecting at least one of the data register and the fuse register to the programmable source in response to the select input signal.
15. The semiconductor device of claim 14, wherein the select switch operatively connects the data register to the at least one input of the programmable source in a first mode of operation and operatively connects the fuse register to the at least one input of the programmable source in a second mode of operation.
16. The semiconductor device of claim 15, wherein the first mode of operation is a test mode and the second mode of operation is a normal mode.
17. The semiconductor device of claim 14, wherein the programmable source is a digital-to-analog converter.
18. The semiconductor device of claim 14, wherein the select switch is a multiplexer.
Description
FIELD OF THE INVENTION

[0001] The present invention relates generally to precision trimming of semiconductor devices, and more specifically relates to semiconductor precision trimming methods and apparatus without requiring a laser for the trimming operation.

BACKGROUND OF THE INVENTION

[0002] Apparatus and methods for precision trimming of semiconductor or thin film devices and circuits are well known in the art. Trimming is often necessary since the absolute-value tolerances associated with such semiconductor or thin film devices are not acceptable, after fabrication, to meet a given design tolerance. Trimming techniques that are known by those skilled in the art include, for example, oxidation, where by heating certain resistor films in an oxidizing atmosphere, some of the material on the film surface is converted to a nonconductive oxide layer to increase the total resistance value, and annealing, which causes the grain structure of a device to reorient itself in a more dense fashion thereby reducing the sheet resistance of the device. Another common trimming method employs narrow fusible links between prearranged segments or taps of a component, such as a resistor. These links are typically formed of metal (e.g., aluminum) and initially short-circuit all taps together, but they can be selectively open-circuited by burning them out, either by external means (e.g., laser) or internal means, for example bypassing an excessive amount of current through the particular link(s) to be blown.

[0003] One application which highlights the importance of precision trimming is the present manufacture of pin electronics used in automated test equipment (ATE) systems and the like, which rely primarily on laser trimming methods and apparatus to meet necessarily precise design performance specifications. Driver circuits utilized in pin electronics, for example, are required to have well-defined output slew rates (i.e., the rate of change of a signal), and because process variations are too great to accurately predict the absolute value of a given reference signal, laser trimming is commonly used. Laser trimming, however, has several inherent disadvantages which make its use undesirable. For instance, laser trimming is relatively slow, due at least in part to the mechanical positioning of the laser during trimming operations. Furthermore, extra mask levels or process steps are typically required in order to fabricate a laser-trimmable component, such as a thin film resistor, thus adding to the fabrication costs and reducing yield. Additionally, since laser trimming is done prior to packaging, any variations due to the packaging process itself cannot be easily corrected.

[0004] By way of example, FIG. 1A illustrates a simple pin electronics driver circuit for use in an automated test system. As understood by those skilled in the art, if a current sink 102 and a current source 104, I1 and I2, respectively, are ideal, the rate of change of output voltage, or slew rate (dv/dt), may be easily calculated as v t = i C ,

[0005] where C is the value of an output ramp-generating capacitor 106 (in Farads) and i is the current value (either I1 or I2, in Amperes) flowing through capacitor 106. Therefore, assuming that the value, C, of capacitor 106 can be accurately defined, the output slew rate (dv/dt) can be accurately predicted.

[0006] The pin electronics circuit may also include a switch mechanism 110, or equivalent means, to selectively connect the capacitor 106 to either the current sink 102 (I1) or current source 104 (I2), thereby generating a negative or a positive slew of the output voltage, respectively. An output buffer 108 is also generally connected to the capacitor 106 to provide a low impedance output node, as well as to provide isolation for the high impedance capacitance node 107.

[0007] A conventional bipolar junction transistor (BJT) implementation of the current sink 102 is depicted in FIG. 1B. With reference to FIG. 1B, the conventional current sink 102 includes an operational amplifier (op amp) 116 operatively connected in a unity gain closed-loop feedback configuration, with the output 118 of the op amp 116 coupled to the base of a BJT device 112, configured as an emitter follower, and the inverting (−) input 120 of the op amp 116 coupled to the junction of the emitter of the BJT device 112 and a reference resistor 1 14, which is typically a thin film laser-trimmable resistor. It is well known that the op amp 116 will control the current i by attempting to hold the voltage at the non-inverting (+) input 122 essentially equal to the voltage at the inverting input 120 of the op amp 116. This, in turn, substantially fixes the input voltage +V across the resistor 114. The current i is then adjusted by trimming the resistance R of resistor 114 until a desired current value is obtained. As stated above, as long as the current source 104 and sink 102 are precisely defined, the output voltage slew rate can be accurately predicted and controlled. The adjustment of the resistor value R is conventionally performed by laser trimming.

[0008] Conventional means of trimming pin electronics systems do not address the above problems. Accordingly, there is a need in the field of precision semiconductor trimming for a technique that provides quick, easy and accurate adjustment of a semiconductor device or circuit in a cost effective manner, without the need for additional process steps in the fabrication thereof. Furthermore, it would be desirable if such precision trimming capability could be provided after the packaging of the device has been completed.

SUMMARY OF THE INVENTION

[0009] The present invention provides a method and apparatus for trimming semiconductor devices and circuits, such as pin electronics, which does not employ a laser for the adjustment process. By eliminating the laser trimming operation, the present invention is a cost-effective means of quickly, easily and accurately adjusting a semiconductor device. Moreover, the present invention does not require fabrication of a laser-trimmable component, such as a thin film resistor, that typically requires additional fabrication process steps which can result in a diminished yield. Furthermore, the trimming capability may be provided after completion of the packaging of the device.

[0010] In accordance with one embodiment, the present invention addresses the need to precisely adjust a reference voltage or current source by replacing the traditional voltage or current source with a programmable voltage or current source, respectively. In a preferred pin electronics circuit application formed in accordance with the present invention, the conventional current source and sink are preferably replaced by a pair of programmable digital-to-analog (D/A) converters. Each D/A converter is operatively coupled to a select switch or mechanism, such as a multiplexer or suitable equivalent thereof, for selectively connecting the input of the D/A converter to at least one of a data register and a fuse register. The data register is used to temporarily store a digital code word during a first mode of operation of the circuit, preferably a test mode. The fuse register is used to permanently store a desired digital code word when the circuit is in a second mode of operation, preferably a normal mode.

[0011] During the test mode of operation, the analog output from the D/A converter is preferably measured while concurrently changing the input digital word stored in the data register. Once the analog output signal is measured to be substantially equal to a predetermined value for the D/A converter output, the digital code word stored in the data register, which corresponds to the desired output, is transferred to the fuse register, which includes a plurality of fusible links, for permanently storing the digital input word to the D/A converter. The digital word is preferably stored in the fuse register by selectively blowing one or more of the fusible links in order to generate the desired digital input word. During normal operation of the circuit, the select switch preferably connects the fuse register to the input of the D/A converter for generating the desired analog output signal.

[0012] These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1A is an electrical schematic diagram illustrating a conventional pin electronics driver circuit employing two ideal current sources.

[0014]FIG. 1B is an electrical schematic diagram illustrating a conventional circuit implementation of the ideal current sources used by the pin electronics driver circuit of FIG. 1A.

[0015]FIG. 2 is an electrical block diagram illustrating a pin electronics driver circuit formed in accordance with a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The present invention will be described herein in the context of a preferred pin electronics driver circuit for providing precision trimming or adjustment of an output voltage slew rate. It should be appreciated, however, that the methods and apparatus of the present invention have wide applicability for the precision trimming of semiconductor devices and/or circuits in general, especially those circuits including a reference current and/or voltage source requiring a precisely defined output. This includes, for example, precision timer circuits, oscillators, analog-to-digital converters, digital-to-analog converters and the like, where laser trimming methods are typically utilized to accurately adjust the absolute value of a reference current or voltage.

[0017]FIG. 2 illustrates a block diagram of a pin electronics driver circuit 200 for supplying input signals to a device under test (DUT) (not shown), formed in accordance with a preferred embodiment of the present invention. With reference to FIG. 2, the rate of change of a voltage generated across an output ramp capacitor 202, or slew rate (dv/dt), is preferably determined by reference sink and source currents, I1 and I2, respectively (in amperes), flowing through the capacitor 202, and the capacitance value, C, (in Farads) of capacitor 202 according to the equation v t = i C ,

[0018] as previously stated above. In order to provide accurate measurement capability, the pin electronics incorporated in an automated test equipment (ATE) system must have a precisely defined output slew rate. Conventionally, the output voltage slew rate of pin electronics driver circuits has been set using laser trimming methods, as discussed above. The present invention entirely eliminates the need for laser trimming by replacing the conventional reference current sink and source with digitally-programmable reference current sinks/sources, preferably implemented as a pair of digital-to-analog (D/A) converters 208, 210 respectively.

[0019] Assuming the value, C, of the output capacitor 202 is within a predetermined window of tolerance (e.g., typically on the order of 20% for integrated MOS capacitors), the slew rate can be precisely defined by adjusting the current flowing through the capacitor 202. As appreciated by those skilled in the art, a D/A converter can be viewed as a decoding device that accepts, as input, digitally coded signals and provides a corresponding analog output signal in the form of a current and/or voltage. Thus, by utilizing a D/A converter for the ideal current source/sink (see e.g., I1 or I2 in FIG. 1A), the output reference current (or voltage) can be selectively adjusted over a relatively wide predetermined range by programming the input of the D/A converter with an appropriate digital input word corresponding to the desired output. A discussion of D/A converters may be found, for example, in Alan B. Grebene, Bipolar and MOS Analog Integrated Circuit Design, John Wiley & Sons (1984), and therefore a detailed analysis will not be presented herein. Although the preferred embodiment shown in FIG. 2 includes two D/A converters 208, 210, each one replacing a corresponding conventional current source or sink, the present invention also contemplates an architecture (not shown) in which a single D/A converter may be employed, along with associated circuitry for controlling the direction of current flow into and out of the output ramp capacitor. Such associated circuitry will be apparent to those skilled in the art. By using two separate D/A converters for the reference current sink and source, the preferred embodiment of the present invention is able to individually adjust the positive and negative output slew rates. This would be advantageous, for example, if the positive and negative slew rates were required to be different.

[0020] The resolution of a D/A converter, typically expressed in bits, is generally defined as the smallest distinct change that can be produced at the analog output in response to a change in the digital input code. A D/A converter having n-bit resolution (i.e., accepting an n-bit digital input word) is capable of generating a total of 2″ discrete analog levels at the output, the levels being preferably equally spaced with respect to one another. The present invention, however, similarly contemplates alternate circuit configurations that may employ, for example, a D/A converter with logarithmically-spaced discrete output levels. Since the resolution of the D/A converter will affect the overall accuracy of the output current adjustment, it is desirable to employ a D/A converter having as great a resolution as possible. There is a tradeoff, however, in that a higher resolution D/A converter is generally more costly than its lower resolution counterpart. The necessary minimum resolution may be dictated, for instance, by the tolerance requirements specified for the output slew rate.

[0021] With continued reference to FIG. 2, the present invention preferably includes a pair of select switches 212 and 214, operatively connected to the inputs of D/A converters 208 and 210, respectively. The select switches 212, 214 are preferably implemented by an n-bit multiplexer (MUX) or suitable equivalent thereof. The digital input words to the D/A converters 208, 210 are preferably programmed and stored in a pair of corresponding data registers 218 and 220, or equivalent storage means. Each data register may be implemented as an n-bit latch or shift register which can be loaded either serially or in parallel for storing the input digital word to the D/A converters. Each select switch 212,214 is preferably responsive to at least one input signal 216 for selectively controlling whether the n-bit digital input word to the D/A converter 208, 210 is to be read from a corresponding n-bit data register 218, 220, respectively, or from a corresponding n-bit fuse register 222, 224, respectively, operatively connected thereto. The fuse registers 222, 224 are preferably implemented as a set of fusible links that can be selectively blown to permanently store a desired input to the corresponding D/A converters 208, 210, respectively.

[0022] The data registers 218, 220 are preferably used only during testing of the pin electronics, in essence as test registers, to determine and temporarily store the correct inputs to the corresponding D/A converters 208, 210. For example, with the select switches 212, 214 configured to operatively couple the data registers 218, 220 to the D/A converters 208, 210, an automated test and measurement procedure (e.g., a software applications program running on a general purpose computer or equivalent system) may be used to concurrently program the data registers with a given digital word and then measure the resulting analog output from the D/A converters. An iterative program/measurement procedure is preferably performed until a desired output is obtained from each D/A converter 208, 210. Once the desired outputs are found, the fuse registers 222, 224 are preferably permanently programmed to provide the same digital input words to the D/A converters as are stored in the corresponding data registers 218, 220. During normal operation of the pin electronics circuit 200, the select registers 212, 214 preferably connect the fuse registers 222, 224 to their corresponding D/A converters 208, 210, respectively.

[0023] In another embodiment of the present invention, the spacing or coarseness by which the digital input signal is changed from one iterative step to the next is preferably adaptively adjusted depending on how far away the corresponding output signal is from the desired output signal. For example, for a given iterative step, the output signal is measured and a difference between the measured output value and the desired value is preferably calculated. For a subsequent iteration step, the amount by which the digital input signal is changed is preferably adjusted in response to this calculated difference. By adaptively adjusting the step size of the digital input word to the D/A converter, the amount of time, and consequently number of iterative steps, required to determine the appropriate input digital word can be reduced.

[0024] The fuse registers each preferably comprise n fusible links, with each link connected to either an internal pull-up resistor or pull-down resistor such that the digital code word output from the fuse register is at least initially either all zeros (0) or all ones (1), respectively, with all fuse links short-circuited (i.e., not blown). The fuse registers 222, 224 are preferably permanently programmed by passing an excessive current through each fusible link that is required to be open-circuited or blown, much like the way a conventional circuit protection fuse is blown. Assuming pull-up resistors are used, when a fuse link has been blown, the particular bit position associated with that link preferably changes from a logic zero to a logic one (or vice versa), thus changing the input digital code to the D/A converter and causing the D/A converter associated therewith to generate a new analog output signal corresponding to the new digital input word. It is to be appreciated that the present invention additionally contemplates that the fuse registers may be implemented by a non-destructive storage device, such as an electrically-erasable programmable read only memory (EEPROM) which is programmed in a conventional manner.

[0025] In order to program the fuse registers, the pin electronics circuit 200 preferably includes one or more on-chip current sources (not shown) for supplying the current necessary to blow the fusible links. It is similarly contemplated that the current required to blow the fuse links may be supplied externally (i.e., off chip), either via an integrated circuit (IC) probe or a physical connection to an external IC pad. Additionally, control circuitry (not shown) is preferably included for directing the current through the desired link(s) to be blown, as appreciated by those skilled in the art. The control circuitry, which may be implemented as a MUX or similar device(s), preferably reads the digital word from the data registers 218, 220, once the desired input word has been found, and determines which links in the corresponding fuse registers 222, 224 should be blown in order to provide the same digital input word to the appropriate D/A converters 208, 210, respectively. In this manner, the present invention uniquely enables the reference current sink/source to be preliminarily adjusted during a test and measurement operation by successively trying various digital input words and measuring the analog output until a sufficiently accurate result is achieved, without permanently fixing the D/A converter inputs. Preferably, only after a sufficiently accurate reference output result is obtained are the fuse registers 222, 224 blown, thereby permanently storing the desired input to the D/A converters 208, 210.

[0026] It is to be appreciated that the present invention provides the ability to precisely adjust the absolute value of an output reference current and/or voltage after the semiconductor circuit has been packaged, rather than only at the wafer level. Since the output reference signal may be subjected to certain variations inherent during the packaging process itself, these errors may be effectively eliminated or at least significantly reduced by performing the precision trimming after the device has been packaged. Conventional laser trimming approaches do not allow for such post-packaging adjustment. As an additional feature of the present invention, if the select input 216 is bonded out externally to an IC pin, the fuse registers 222, 224, which permanently store a preset digital code word relating to a desired reference output current (or voltage), may be overridden such that the digital inputs to the D/A converters 208, 210 are instead read from the data registers 218, 220 associated therewith, as they are during test mode.

[0027] The present invention, as illustrated and described herein by way of an example pin electronics driver circuit, provides methods and apparatus for trimming semiconductor devices and circuits, such as pin electronics circuits used in ATE systems and the like, which do not employ a laser trimming operation. In a preferred embodiment, the present invention addresses the need to precisely adjust a reference current and/or voltage by replacing the conventional current/voltage reference source with a digitally-programmable current/voltage reference source preferably implemented by a D/A converter. A select switch having an output bit width corresponding to the D/A converter input bit width is preferably operatively coupled to the input of the D/A converter and operatively presents a digital input word to the D/A converter by selectively reading the digital word from at least one of a data register and a fuse register. The data register is preferably used only during testing of the overall current or voltage reference circuit by iteratively stepping through various digital input codes until a sufficiently accurate output signal is achieved. The fuse register is then preferably blown to permanently store the input code word that provides the desired reference output signal. During normal operation of the system, the select switch preferably reads the D/A converter input word from the fuse register. In this manner, a precise output reference output signal is achieved without the need for a laser trimming operation.

[0028] Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications maybe affected therein by one skilled in the art without departing from the scope or spirit of the invention.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6985100Dec 9, 2003Jan 10, 2006Analog Devices, Inc.Integrated circuit comprising a DAC with provision for setting the DAC to a clear condition, and a method for setting a DAC to a clear condition
US7031218 *Nov 17, 2003Apr 18, 2006Infineon Technologies AgExternally clocked electrical fuse programming with asynchronous fuse selection
US7456426Oct 8, 2004Nov 25, 2008International Business Machines CorporationFin-type antifuse
US7691684Jul 31, 2008Apr 6, 2010International Business Machines CorporationFin-type antifuse
US8280672Dec 31, 2008Oct 2, 2012SK Hynix Inc.Trimming circuit of semiconductor memory apparatus and trimming method thereof
US8350617Dec 16, 2010Jan 8, 2013SK Hynix Inc.Semiconductor apparatus
WO2004054113A1 *Dec 9, 2003Jun 24, 2004Analog Devices IncAn integraded circuit comprising a dac with provision for setting the dac to a clear condition, and a method for setting a dac to a clear condition
Classifications
U.S. Classification341/144
International ClassificationG01R31/319, G01R31/28, H01L21/82, H01L21/822, H03K19/00, H01L27/04, H03M1/10
Cooperative ClassificationG01R31/31924, H03M1/1061, H03M1/108
European ClassificationH03M1/10C3T2, H03M1/10T2, G01R31/319S3
Legal Events
DateCodeEventDescription
May 8, 2014ASAssignment
Free format text: PATENT SECURITY AGREEMENT;ASSIGNORS:LSI CORPORATION;AGERE SYSTEMS LLC;REEL/FRAME:032856/0031
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG
Effective date: 20140506
Jan 15, 2014FPAYFee payment
Year of fee payment: 12
Feb 8, 2010FPAYFee payment
Year of fee payment: 8
Feb 9, 2006FPAYFee payment
Year of fee payment: 4
Oct 22, 2002CCCertificate of correction
Mar 28, 2001ASAssignment
Owner name: AGERE SYSTEMS GUARDIAN CORP, FLORIDA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CLAPP, JOHN S.;JOHNSON, GLEN A.;LEBO, DOUGLAS BAIRD;AND OTHERS;REEL/FRAME:011642/0819;SIGNING DATES FROM 20010319 TO 20010322
Owner name: AGERE SYSTEMS GUARDIAN CORP SUITE 105 14645 N.W. 7
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CLAPP, JOHN S. /AR;REEL/FRAME:011642/0819;SIGNING DATES FROM 20010319 TO 20010322
Owner name: AGERE SYSTEMS GUARDIAN CORP SUITE 105 14645 N.W. 7