|Publication number||US20020108930 A1|
|Application number||US 10/115,666|
|Publication date||Aug 15, 2002|
|Filing date||Apr 4, 2002|
|Priority date||May 26, 1998|
|Also published as||US6395192|
|Publication number||10115666, 115666, US 2002/0108930 A1, US 2002/108930 A1, US 20020108930 A1, US 20020108930A1, US 2002108930 A1, US 2002108930A1, US-A1-20020108930, US-A1-2002108930, US2002/0108930A1, US2002/108930A1, US20020108930 A1, US20020108930A1, US2002108930 A1, US2002108930A1|
|Inventors||Yael Nemirovsky, Sara Stolyarova, Benjamin Brosilow|
|Original Assignee||Steag Cvd Systems Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (2), Classifications (14)|
|External Links: USPTO, USPTO Assignment, Espacenet|
 This application is related to Provisional Application No. 60/086,635, filed May 20, 1998 and claims its priority date.
 The present invention relates to a method and apparatus for selectively removing native oxide layers from silicon wafers without significantly affecting the underlying silicon, or without significantly removing other materials, such as polysilicon or thermal oxide depositions, that may be thereon. Such a process is of substantial importance to the semiconductor industry since the selective removal of native oxide from silicon wafers is among the most frequently performed processes in fabricating silicon semiconductor devices.
 Whenever a silicon wafer is exposed to an oxidizing environment, a native oxide layer tends to form on the silicon wafer. Such native oxide layers would deleteriously affect the subsequent processing steps performed on the silicon wafer, and therefore must be cleanly and quickly removed without disturbing other depositions, such as, polysilicon or thermal oxide depositions, on the silicon wafer. Generally speaking, a dry cleaning process is more effective and less damaging to the silicon surface than a wet cleaning process.
 Narita U.S. Pat. No. 4,985,372 describes a dry cleaning process wherein the silicon wafer surface is exposed to an echant gas including NF3 and H2, or N2 in place of the H2. The process described in that patent requires the generation of a plasma in the chamber at the time the wafer is exposed to the etchant gas.
 Another cleaning technique is described in a PhD Thesis by Kevin J. Torek, University of Pennsylvania, May 1996. One described process involves exposing the silicon wafer to NF3 gas and to ultraviolet radiation while at room temperature (20° C.). According to the data set forth in that Thesis (FIG. 8. page 47), the native oxide was etched at a relatively low rate of between 0.7 A/min (at 80 Torr) to 4A/min (at 760 Torr) The native oxide removal was selective over depositions on the silicon wafer produced by sputtoring, chemical vapor deposition, steam-thermal deposition, and dry-thermal oxide deposition.
 This Thesis described another process (FIG. 10, page 50) which included heating the wafer while exposing it to NF3 in the presence of ultraviolet light and H2O. However, such a process involves completely different chemistry since the addition of H2O causes the formation of HF and completely changes the reaction rates and selectivities.
 An object of the present invention is to provide a method for selectively removing a native oxide layer from a silicon wafer having advantages over the above-described methods known in the prior art. Another object of the invention is to provide apparatus for removing native oxide layers in accordance with the novel method.
 According to one aspect of the present invention, there is provided a method of selectively removing a native oxide layer from a silicon wafer without significantly affecting the underlying silicon or other materials that may be there on, comprising exposing the silicon wafer to an etchant gas including NF3 while simultaneously exposing the wafer to ultraviolet radiation and heating the wafer to a temperature of 100-400° C.
 Preferably, the process should be performed at a temperature of 250-350° C., particularly good results having been obtained at a temperature of about 300° C. As will be described more particularly below, it has been found that elevating the process temperature as described above substantially increases the removal rate of the native oxide without losing the selectivity achieved at room temperature until the higher end of above-described temperature range is reached At higher temperatures, the native oxide removal rate may increase further, but it was found that selectivity is lost.
 According to further features in the preferred embodiment of the invention described below, the etchant gas also includes N2 The example described below includes N2 in approximately equal proportions by volume as the NF3.
 According to still further features in the described preferred embodiment, the partial pressure of the etchant gas is preferably within the moderate pressure range, of 10-300 Torr. The higher partial pressures would be expected to produce faster reaction rates, but would result in a number of disadvantages. Thus, higher pressures in the reactor increase the danger of leakage of NF3 from the reactor to the atmosphere, which can cause a serious health problem since NF3 is highly toxic. In addition, a high pressure in the reactor increases the danger of particles depositing on the silicon wafer being treated which will cause problems in subsequent processing of the wafer. Further, a higher pressure in the reactor increases the wafer processing time in single-wafer processing apparatus, since the NF3 must be completely removed from the chamber prior to transferring the wafer to the next process module. Thus, a low process pressure saves time by requiring less pump down time at the end of the process, and less time for pressure and flow stabilization at the beginning of the process.
 Preferably, therefore, the pressure should be below 100 Torr. optimally about 30-60 Torr. In the example described below, the partial pressure of the NF3 was 30 Torr and the partial pressure of the N2 was 30 Torr.
 According to another aspect of the present invention, there is provided apparatus for removing a native oxide layer from a silicon wafer without significantly affecting the underlying silicon or other materials that may be there on, comprising a heating chamber including a supporting member for supporting the wafer from which the native oxide layer is to be selectively removed; a heater for heating a wafer on the supportive member to a temperature of 100-400° C.; a gas supply for introducing into the chamber an etchant gas including NF3; and an ultraviolet source for irradiating the water with ultraviolet radiation while the wafer is exposed to the etchant gas and is heated to the temperature of 100-400° C.
 Further features and advantages of the invention will be apparent from the description below
 The invention is herein described, somewhat diagramatically and by way of example only, with reference to the accompanying drawings, wherein:
FIG. 1 is a side view illustrating one form of apparatus constructed in accordance with the present invention;
FIG. 2 is an axial view of the apparatus of FIG. 1; and
FIG. 3 sets forth the results a number of experiments in selectively removing native oxide layers from a silicon wafer in accordance with the present invention.
FIGS. 1 and 2 schematically illustrate one form of apparatus constructed in accordance with the present invention for cleaning silicon wafers by selectively removing a native oxide layer from the silicon wafer without significantly affecting the underlying silicon, or a polysilicon or thermal oxide deposition that may be thereon.
 The apparatus illustrated in FIGS. 1 and 2 includes a reactor, generally designated 2, consisting of a horizontal quartz tube defining an internal reactor chamber 3. The horizontal quartz tube may be about 85 mm in length, about 15 mm in diameter, and about 2 mm wall thickness. The lower half of reactor chamber 3 is occupied by a half-cylinder shaped graphite susceptor 4 which supports one of more silicon wafers SW to be processed within the reactor chamber. Externally of and below reactor chamber 3 is an infrared lamp 5 which heats the graphite susceptor 4 from below. The graphite susceptor has a thermo-couple 6 embedded within it for temperature measurement, which measurement is outputted via lead 6 a. Externally above reactor 2 is a low-pressure mercury lamp 7 which generates ultra-violet light for radiating the silicon wafers SW supported on the graphite susceptor 4. The upstream end of reactor 2 includes a gas supply manifold 8 for supplying the etchant gas; and the down-stream end of the reactor includes a gas discharge assembly 9 for removing the etchant gas Gas discharge assembly 9 may be a roughing pump connected to the downstream end of the reactor chamber by a series of steel pipes.
 The reactor 2 is only schematically shown in FIGS. 1 and 2. Preferably it would be of the structure described in U.S. Pat. No. 5,228,206, which description is hereby incorporated by reference.
 The silicon wafers SW to be cleaned are supported on the upper flat surface of the graphite susceptor 4, as shown in FIGS. 1 and 2. Preferably, this is done by supporting it on three supporting pins spacing the wafer from the susceptor to minimize the contact of the wafer with the susceptor. The infrared lamp heater 5 is energized to heat the graphite susceptor to a predetermined temperature as measured by thermo-couple 6 embedded within the graphite susceptor. The silicon wafers SW are also irradiated with ultraviolet light from the ultraviolet lamp 7 overlying the reactor 2. While the silicon wafers SW are thus heated by heater 5 and irradiated with ultraviolet light by ultraviolet lamp 7. They are exposed to a flow of etchant gas introduced via the inlet manifold 8 and exhausted via the gas discharge assembly 9.
 As one example, the etchant is NF3 mixed with N2. Each gas is supplied at a partial pressure of 30 Torr (total pressure 60 Torr) with a gas flow of 200 cm3/sec. in this example, the process time was three minutes.
 A number of silicon wafer samples were thus treated by the etchant while heated by infrared lamps 5 to a predetermined high temperature, ranging from room temperature 27° C. to 600° C., and while exposed to the ultraviolet light from the UV (ultra violet) lamp 7. After the process had been completed, the samples were removed from the reactor chamber and immediately analyzed with an ellipsometer to measure the thickness of the various layers. It was possible to calculate the amount of material removed during each process from each sample by comparing the ellipsometer measurements made with respect to each sample before being processed, with those made after the sample was processed.
FIG. 3 is a table setting forth the results obtained when three silicon wafer samples (a), (b) and (c) were processed as described above at 27° C. (room temperature), 300° C. without ultraviolet radiation, 300° C. with ultraviolet radiation, 450° C. without ultraviolet radiation, and 600° C. without ultraviolet radiation. Sample (a) was a silicon single crystal wafer with a native oxide layer; sample (b) was a silicon wafer having a 4000 A layer of polysilicon and a 1000 A layer of thermal oxide; and sample (c) was a silicon wafer having a 1000 A layer of thermal oxide. The treatment in all cases was carried out for three minutes, and included the etchant gas of NF3 and N2 as described above.
 As can be seen from the data set forth in the table of FIG. 3, no significant etching of any of the layers was noted when the process was performed at 27° C. with ultraviolet radiation, or at 300° C. without ultraviolet radiation.
 However, when the process was performed at 300° C. with ultraviolet radiation, the native oxide layer was completely removed from sample (a); but neither the polysilicon layer nor the thermal oxide layer was removed from sample (b), nor was the thermal oxide layer removed from sample (c).
 When the process was performed at 450° C., even without ultraviolet radiation, the native oxide from sample (a) was completely removed, but the polysilicon from sample (b) was also completely removed. Similarly, when the process was performed at 600° C., the native oxide was removed from sample (a), but the polysilicon and thermal oxide layers were also completely removed from sample (b), and the thermal oxide layer was removed from sample (c). The removal of the polysilicon and thermal oxide layers from samples (b) and (c) would of course destroy the selectivity of the etching process; moreover had the samples also been irradiated with ultraviolet light when heated to those very high temperatures 450° C. and 600° C., it would be expected that the undesired removal of the polysilicon and thermal oxide layers would even have been accelerated.
 Accordingly, among the temperatures and other conditions tested in the above-described experiments, it is clear that best results were obtained in rate of removal and selectivity when the process is performed at a temperature approximately 300° C. while accompanied with ultraviolet radiation.
 It is believed that the selectivity can be explained by the nature of the reaction involved of the etchant gas with silicon dioxide and silicon. Thus, without ultraviolet radiation, when the temperature is less than 600° C., the process is controlled by the thermally-activated reaction of NF3 with silicon.
4NF 3↑+3Si→3SiF 4↑2N 3 556 (1)
 With UV photon activation, a controlled quantity of F-radicals can be obtained, which interact with SiO2.
4F+SiO 2 →SiF 4 ↑+O 2↑(2)
 This reaction is less temperature dependent and occurs rather fast (native oxide removed for 3 min) at the temperature lower than those required for the reaction (2).
 When the temperature is above 600° C., a thermal decomposition of NF3 to F-radicals takes place. Both reactions therefore occur, and the selectivity is lost.
 An important advantage of the process of the present invention is that it achieves a significantly increased etch rate at the low pressure desirable for such process for reasons set forth earlier. For example, at PNF3=30 Torr (and Pn2b =30 Torr) the described process at 300° C. gives a native oxide etch rate of over 5 A/min., while the room temperature process reported by Torek (K Torek, PhD thesis, Penn State University. 1996) referred to above, gave an etch rate of only 0.7 A/min at this NF3 pressure and room temperature. It is to be noted that the higher etch rate given by the elevated temperature process does not harm the selectivity of native oxide etch over thermal oxide and silicon, which are not etched.
 While the invention has been described with respect to one preferred embodiment, it will be appreciated that this is set forth merely for purposes of example, and that many other variations, modifications and applications of the invention may be made.
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7789965||Sep 19, 2007||Sep 7, 2010||Asm Japan K.K.||Method of cleaning UV irradiation chamber|
|US7871937||Dec 9, 2008||Jan 18, 2011||Asm America, Inc.||Process and apparatus for treating wafers|
|U.S. Classification||216/66, 257/E21.252, 156/345.5, 257/E21.226|
|International Classification||C12N15/867, H01L21/311, B08B7/00, H01L21/306|
|Cooperative Classification||H01L21/31116, H01L21/02046, B08B7/0057|
|European Classification||B08B7/00S6, H01L21/311B2B, H01L21/02F2B|