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Publication numberUS20020109236 A1
Publication typeApplication
Application numberUS 10/059,932
Publication dateAug 15, 2002
Filing dateJan 28, 2002
Priority dateFeb 9, 2001
Also published asUS6448661
Publication number059932, 10059932, US 2002/0109236 A1, US 2002/109236 A1, US 20020109236 A1, US 20020109236A1, US 2002109236 A1, US 2002109236A1, US-A1-20020109236, US-A1-2002109236, US2002/0109236A1, US2002/109236A1, US20020109236 A1, US20020109236A1, US2002109236 A1, US2002109236A1
InventorsHyeong-Seob Kim, Sa-Yoon Kang, Myung-Kee Chung, In-Ku Kang, Kwan-Jai Lee
Original AssigneeSamsung Electronics Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof
US 20020109236 A1
Abstract
A three-dimensional, multi-chip package with chip selection pads formed at the chip-level and a manufacturing method thereof are provided. The three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, (N-1) chip selection pads, an insulation layer, (N-1) metal wirings, upper connection terminals, lower connection terminals, and trench wirings. The chip selection terminal of each chip is separated from the chip selection of the other chips by the chip selection pads formed at the chip-level.
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Claims(14)
What is claimed is:
1. A three-dimensional, multi-chip package formed by stacking a number (N) of semiconductor integrated circuit chips, each chip comprising:
an integrated circuit die having an upper surface and a lower surface;
a chip selection terminal formed on the upper surface of said die;
a number (N-1) of chip selection pads formed on the upper surface of said die proximate to said chip selection terminal;
an insulation layer formed on the upper surface;
a number (N-1) of first metal wirings formed within said insulation layer, each of said first metal wirings connected to a corresponding one of said chip selection pads;
upper connection terminals formed on said insulation layer and connected to said first metal wirings;
lower connection terminals formed on the lower surface of said die corresponding to said upper connection terminals; and
trench wirings formed through said die, said trench wirings connecting said chip selection terminal or said chip selection pads to said lower connection terminals,
wherein among said chip selection pads, a first chip selection pad next to said chip selection terminal is connected to the upper connection terminal formed above said chip selection terminal, and the (N-1)th chip selection pad is connected to the upper connection terminal formed above the (N-2)th chip selection pad, and
wherein said chips are stacked by attaching said upper connection terminals of a lower chip to said lower connection terminals of an upper chip, and said chip selection terminal of each chip is connected to a corresponding one of said lower connection terminals of a lowermost chip.
2. The multi-chip package of claim 1, wherein said die is one of a plurality of integrated circuit dies formed on a wafer.
3. The multi-chip package of claim 1, wherein said die is an integrated circuit die separated from a wafer.
4. The multi-chip package of claim 1, wherein said die is a memory chip.
5. The multi-chip package of claim 1, wherein each chip further comprises second metal wirings formed on said insulation layer, said second metal wirings for connecting said first metal wirings to said upper connection terminals.
6. The multi-chip package of claim 1, wherein said upper connection terminal formed above said (N-1)th chip selection pad is electrically isolated.
7. The multi-chip package of claim 1, further comprising adhesive layers, each adhesive layer being interposed between a lower chip and an upper chip.
8. The multi-chip package of claim 1, further comprising Anisotropic Conductive Film (ACF) or Anisotropic Conductive Adhesive (ACA), each ACF or each ACA being interposed between a lower chip and an upper chip.
9. A method for manufacturing a three-dimensional multi-chip package formed by stacking a number (N) of semiconductor integrated circuit chips, said method comprising:
(a) forming a chip selection terminal and a number (N-1) of chip selection pads proximate to said chip selection terminal on an upper surface of said chip;
(b) forming a plurality of trenches from said chip selection terminal and said chip selection pads within said chip;
(c) forming trench wirings by filling said trenches with a conductive material;
(d) forming a number (N-1) of first metal wirings along said upper surface of the chip, each of said first metal wirings being connected to a corresponding one of said chip selection pads;
(e) forming a first insulation layer on said upper surface of the chip and said first metal wirings;
(f) forming a plurality of upper connection terminals connected to said first metal wirings on said first insulation layer;
(h) forming a plurality of lower connection terminals on said lower surface of the chip, each of said lower connection terminals connected to a corresponding one of said trench wirings; and
(i) stacking said chips by attaching said upper connection terminals of a lower chip to said lower connection terminals of an upper chip.
10. The method of claim 9, wherein said step (f) comprises:
(f-1) forming a plurality of through holes by removing a portion of said first insulation layer, each of said through holes for exposing a portion of corresponding one of said first metal wirings;
(f-2) forming through wirings by filling said through holes with a conductive material; and
(f-3) forming upper connection terminals connected to a corresponding one of said through wirings on said first insulation layer.
11. The method of claim 9, wherein said step (f) comprises:
(f-4) after forming a plurality of through holes by removing a portion of said first insulation layer, forming first through wirings by filling said through holes with a conductive material, said through hole for exposing a portion of a corresponding one of said first metal wirings;
(f-5) forming second metal wirings connected to said first through wirings on said first insulation layer;
(f-6) forming a second insulation layer on said second metal wirings;
(f-7) after forming a plurality of through holes by removing a portion of said second insulation layer, forming second through wirings by filling said through holes with a conductive material, said through hole for exposing a portion of corresponding one of said second metal wirings; and
(f-8) forming upper connection terminals connected to a corresponding one of said second through wirings on said second insulation layer.
12. The method of claim 9, wherein the step (i) further comprises interposing adhesive layers between the chips.
13. The method of claim 9, wherein the step (i) further comprises interposing Anisotropic Conductive Film (ACF) or Anisotropic Conductive Adhesive (ACA) between the chips.
14. The method of claim 9, further comprising:
(g) grinding the lower surface of said chip so that said trench wirings are exposed through said lower surface of the chip.
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    1 . Field of the Invention
  • [0002]
    The present invention relates to semiconductor packaging technology and, more particularly, to a three-dimensional, multi-chip package with chip selection pads and a manufacturing method thereof.
  • [0003]
    2 . Description of the Related Art
  • [0004]
    In order to satisfy the pressing demands for increased integration and multi-functionality, various three-dimensional multi-chip packages have recently been developed. A conventional three-dimensional multi-chip package is manufactured as described below. After manufacturing a wafer and separating the wafer into a plurality of individual chips, the chip is attached and electrically connected to the substrate, and is encapsulated with a molding resin to produce a package. Then, a multi-chip package is obtained by stacking the packages.
  • [0005]
    These multi-chip packages employ a lead frame, or a substrate such as a tape circuit board or a printed circuit board. Various interconnection methods such as a wire-bonding method, tape automated bonding (TAB) method, or flip chip-bonding method, are employed to establish electrical connection between the chip and the substrate.
  • [0006]
    The multi-chip packages formed by stacking a plurality of packages are disclosed in U.S. Pat. Nos. 4,982,265, 4,996,583, 5,172,303, 5,198,888, 5,222,014, 5,247,423, 5,313,096, 5,783,870 and 6,072,233. However, these multi-chip packages are manufactured using complex processes. Moreover, these multi-chip packages have much bigger sizes than the standard chip, thereby reducing the mounting density on the external apparatus. Further, since the multi-chip packages employ substrates, they cause long signal transmission routes and thereby signal delay results.
  • [0007]
    While three-dimensional multi-chip packages on wafer-level or chip-level are disclosed in U.S. Pat. Nos. 4,394,712, 4,807,021, 4,897,708, 4,954,875, 5,202,754, 5,229,647 and 5,767,001. These multi-chip packages have the advantage of simple structures, smaller sizes, and simple manufacturing processes. Further, a multi-chip package at the wafer-level prevents signal delay. However, this technique is applied only to non-memory devices such as Application Specific Integrated Circuit (ASIC) or to multi-chip packages with multiple functions by stacking different types of chips.
  • [0008]
    Generally, multi-chip packages are classified into two types. One is a multi-chip package formed by stacking different types of chips, thereby achieving multi-functionality. The other is a multi-chip package formed by stacking the same types of chips, thereby improving memory capacity.
  • [0009]
    In order to improve memory capacity by stacking the same types of chips, there must be a chip selection mechanism to operate the desired chip. Therefore, each memory chip comprises a chip selection terminal. For example, in case of a DRAM chip, the Row Address Strobe (RAS), Column Address Strobe (CAS) or Chip Selection Pin (CSP) is used as the chip selection terminal. By selectively transmitting electronic signals to the specific chip selection terminal corresponding to the desired chip of the multi-chip package, the desired chip is selected for operation. Other non-selecting terminals of the memory chips in the multi-chip package are commonly connected together, but the chip selection terminal for each individual chip are isolated and connected to an external electronic component.
  • [0010]
    The conventional technique for separating the chip selection terminals of each chip from one another is disclosed in the above-described multi-chip package. That is, the chip selection terminal of each chip is connected to an external electronic component through connection wirings formed on a substrate of the package. Therefore, in order to separate the chip selection terminal of each chip from one another, each substrate should comprise a connection wiring configuration different from the other substrates, thereby increasing the production cost and reducing productivity.
  • [0011]
    The drawbacks are prevented by a conventional technique disclosed in U.S. Pat. No. 5,995,379. In this patent, the chip selection terminal of each chip is connected to external electronic components by a substrate with the same connection wiring configuration as the substrate of the other chips. However, since this technique is applied to a multi-chip package by stacking packages, it requires substrates on which connection wirings are formed. Therefore, this technique also has the previously described drawbacks of stacked, multi-chip packages such as large package size, reduced mounting density, complex manufacturing processes, and signal delay.
  • SUMMARY OF THE INVENTION
  • [0012]
    The present invention increases memory capacity by providing a multi-chip package formed by stacking at least two of the same types of chips.
  • [0013]
    The present invention provides a multi-chip package at the wafer-level, thereby reducing package size, increasing mounting density, and preventing signal delay.
  • [0014]
    The present invention separates the chip selection terminal of each chip from one another via chip selection pads formed at the chip-level. The present invention simplifies the manufacturing process of the multi-chip package.
  • [0015]
    According to one embodiment, a three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, a number (N-1) of chip selection pads, an insulation layer, a number (N-1) of metal wirings, upper connection terminals, lower connection terminals, and trench wirings.
  • [0016]
    The chip selection terminal and the chip selection pads are formed on an upper surface of the die, and the chip selection pads are proximate to the chip selection terminal. The insulation layer is formed on the upper surface of the die, and the metal wirings are formed within the insulation layer and connected to the chip selection pads. The upper connection terminals are formed on the insulation layer and connected to the metal wiring. The lower connection terminals are formed on the lower surface of the die, and each of the lower connection terminals is connected to a corresponding one of the chip selection terminal and the chip selection pads. The trench wirings extend through the die, and connect the chip selection terminal and the chip selection pads to the lower connection terminals.
  • [0017]
    Among the chip selection pads, a first chip selection pad next to the chip selection terminal is connected to the upper connection terminal formed above the chip selection terminal, and the (N-1)th chip selection pad is connected to the upper connection terminal formed above the (N-2)th chip selection pad.
  • [0018]
    The individual chips are stacked by attaching the upper connection terminals of a lower chip to the lower connection terminals of an upper chip. The chip selection terminal of each chip is connected to a corresponding one of the lower connection terminals of a lowermost chip.
  • [0019]
    Further, the present invention provides a method of manufacturing a chip-level, three-dimensional, multi-chip package by stacking a number (N) of semiconductor integrated circuit chips.
  • [0020]
    In accordance with the method of the present invention, a chip selection terminal and a number (N-1) of chip selection pads close to the chip selection terminal are formed on the upper active surface of the chip, and a plurality of trenches from the chip selection terminal and the chip selection pads are formed within the chip. Then, trench wirings are formed by filling the trenches with a conductive material, and a number (N-1) of first metal wirings formed along the upper surface of the chip, each of the first metal wirings are connected to a corresponding one of the chip selection pads. A first insulation layer is formed on the upper surface of the chip and the first metal wirings, and a plurality of upper connection terminals connected to the first metal wirings are formed on the first insulation layer. The lower surface of the chip is grinded so that the trench wirings are exposed through the lower surface of the chip. A plurality of lower connection terminals are formed on the lower surface of the chip, with each of the lower connection terminals being connected to a corresponding one of the trench wirings. The chips are stacked by attaching the upper connection terminals of a lower chip to the lower connection terminals of an upper chip.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0021]
    These and other objects, features, and advantages of the present invention will be readily understood with reference to the following detailed description provided in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and, in which:
  • [0022]
    [0022]FIG. 1 is a cross-sectional view of a three-dimensional, multi-chip package in accordance with an embodiment of the present invention;
  • [0023]
    [0023]FIG. 2 is a cross-sectional view of an individual semiconductor integrated circuit chip used in the three-dimensional, multi-chip package of FIG. 1;
  • [0024]
    [0024]FIGS. 3A to 3K are cross-sectional views showing a manufacturing method of the three-dimensional, multi-chip package of FIG. 1; and
  • [0025]
    [0025]FIG. 4 is a cross-sectional view of a three-dimensional, multi-chip package in accordance with another embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0026]
    Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
  • [0027]
    [0027]FIG. 1 is a cross-sectional view of a chip-level, three-dimensional, multi-chip package in accordance with one embodiment of the present invention, and FIG. 2 is a cross-sectional view of an individual semiconductor integrated circuit chip used in the chip-level, three-dimensional, multi-chip package. With reference to FIGS. 1 and 2, a first embodiment of the present invention is described below.
  • [0028]
    In order to improve memory capacity, a chip-level three-dimensional multi-chip package 100 of FIG. 1 is formed by stacking four (4) of the same types of semiconductor integrated circuit chips 10 in FIG. 2. Reference numerals 110, 120, 130 and 140 in FIG. 1 each represent individual integrated circuit chips.
  • [0029]
    The chips 10, 110, 120, 130 and 140 are memory chips such as DRAM chips or flash memory chips. It is well known that a memory chip comprises address input terminals for addressing memory cells, data input/output terminals for inputting/outputting data to/from the memory cells, and power supply terminals. The chip terminals 12 of the chips are interconnected to one another, while the chip selection terminal 12 a of one chip is separated from another chip selection terminal 12 a of another chip and connected to an external environment.
  • [0030]
    As shown in detail in FIG. 2, the chip 10 comprises a die 11. Herein, the die 11 is a die on wafer-level or a die individually separated (singulated) from a wafer. A plurality of chip terminals 12 and a chip selection terminal 12 a are formed on an upper active surface of the die 11. Integrated circuits (not shown) are formed within the die 11 and connected to the chip terminals 12 and the chip selection terminal 12 a.
  • [0031]
    The chip 10 comprises three (3) chip selection pads 12 b, 12 c, 12 d. The chip selection pads 12 b, 12 c, 12 d are formed on the upper surface of the die 11 close or adjacent to the chip selection terminal 12 a. Herein, the number of the chip selection pads is one less than the total number of stacked chips 10. For example, if the multi-chip package is formed by stacking a number (N) of chips, a number (N-1) of chip selection pads are required. The chip selection pads 12 b, 12 c, 12 d are not connected to the integrated circuits within the die 11.
  • [0032]
    First metal wirings 15 are formed on the upper surface of the die 11 and the chip selection pads 12 b, 12 c, and 12 d, with each chip selection pad connected to a corresponding one of the first metal wirings 15. A first insulation layer 16 is formed on the upper surface of die 11. Thus, the first metal wirings 15 are formed within the first insulation layer 16. The first metal wirings 15 extend toward the chip selection terminal 12 a and electrically separated from one another. Each of the chip selection pads 12 b, 12 c, and 12 d is connected to a corresponding one of the lower connection terminals 23 b, 23 c, and 23 d formed on the lower surface of die 11 by trench wirings 14 perforating or extending through the die 11. The chip selection terminal 12 a and the chip terminals 12 are electrically connected to the lower connection terminals 23 a and 23, respectively, through the trench wirings 14.
  • [0033]
    A second insulation layer 20 is formed on the upper surface of the first insulation layer 16. Second metal wirings 19, 19 a are formed within the second insulation layer 20. The second metal wirings 19, 19 a are electrically connected to the first metal wirings 15 through first through wirings 18 formed within the first insulation layer 16. The second metal wirings 19, 19 a extend toward the chip selection terminal 12 a and are electrically separated from one another. The second metal wiring 19 connected to the first chip selection pad 12 b next to the chip selection terminal 12 a is disposed above the chip selection terminal 12 a, and the second metal wiring 19 connected to the second chip selection pad 12 c is disposed above the first chip selection pad 12 b. The second metal wiring 19 connected to the third chip selection pad 12 d is disposed above the second chip selection pad 12 c. The isolated second metal wiring 19 a is disposed above the third chip selection pad 12 d.
  • [0034]
    Second through wirings 21 are formed within the second insulation layer 20 and connected to the second metal wirings 19, 19 a. Upper connection terminals 22 a, 22 b, 22 c, 22 d are formed on the second insulation layer 20 and connected to the second through wirings 21.
  • [0035]
    Upper connection terminals 22 are formed on the second insulation layer 20, and connected to the chip terminals 12. Herein, in order to electrically connect the chip terminal 12 to the corresponding upper connection terminal 22 and to the corresponding lower connection terminal 23, the trench wiring 14, the first through wiring 18, and the second through wiring 21 all are formed on the same position. Thus, the first selection pad 12 b is connected to the upper connection terminal 22 a, and the second selection pad 12 c is connected to the upper connection terminal 22 b. The third selection pad 12 d is connected to the upper connection terminal 22 c. The upper connection terminal 22 d is connected to the isolated second metal wiring 19 a, and is therefore not connected to any of the chip selection pads 12 b, 12 c, 12 d.
  • [0036]
    The multi-chip package 100 in FIG. 1 is obtained by stacking a plurality of the semiconductor integrated circuit chips 10, each chip having the above-described configuration. One chip 10 is connected to another chip by the attachment between the upper connection terminals 22, 22 a-22 d and the lower connection terminals 23, 23 a-23 d. That is, the upper connection terminals of a lower chip are attached to the lower connection terminals of an upper chip.
  • [0037]
    The lower connection terminals 23, 23 a-23 d of the lowermost chip 110 serve as external terminals of the multi-chip package 100 and are attached to an external device such as a mother board (not shown). In order to easily attach the lower connection terminals 23, 23 a-23 d to the mother board, metal bumps or solder balls may be formed on the lower connection terminals 23, 23 a-23 d. In the same manner, in order to effectively stack the chips 110, 120, 130, 140 to one another, metal bumps or solder balls may be formed on both/either the upper connection terminals 22, 22 a-22 d and/or the lower connection terminals 23, 23 a-23 d.
  • [0038]
    The chip selection terminal 12 a of each chip 110, 120, 130, 140 is connected to a corresponding one of the lower connection terminals 23 a-23 d of the lowermost chip 110. As shown in FIG. 1, the chip selection terminal 12 a of the first chip 110, i.e. the lowermost chip 110, is connected to the first lower connection terminals 23 a by the trench wiring 14. The chip selection terminal 12 a of the third chip 130 is connected to the third lower connection terminals 23 c by passing through the third, the second and the first chip 130, 120, 110.
  • [0039]
    In order to separate the chip selection terminal of one chip from the chip selection terminals of other chips, the multi-chip package in this embodiment of the present invention does not require that each chip have a different connection-wiring configuration. Although the three-dimensional multi-chip package of the present invention comprises a plurality of stacked chips, each chip with the same structure, the chip selection terminal of each chip is automatically separated from those of other chips. Also, the chip selection pads are formed at the chip-level. That is, the chip selection pads are formed directly on the integrated circuit chip. Since the multi-chip package of the present invention does not require any additional substrate for forming the chip selection pads, the present invention can achieve chip-level, multi-chip packages. The present invention minimizes package size and improves mounting density, thus preventing signal delay.
  • [0040]
    [0040]FIGS. 3A to 3K are cross-sectional views showing a manufacturing method of the chip-level, three-dimensional, multi-chip package of the present invention. With reference to FIGS. 3A to 3K, the manufacturing method of the chip-level, three-dimensional, multi-chip package of this embodiment is described below.
  • [0041]
    As shown in FIG. 3A, a semiconductor integrated circuit die 11 is first fabricated. The die 11 may be one of several dies fabricated on a wafer or an individual die separated from the wafer. As is identical to conventional chips, a plurality of the chip terminals 12 and a chip selection terminal 12 a are formed on the upper active surface of the die 11. Three (3) chip selection pads 12 b, 12 c, 12 d are formed on the upper surface of the die 11 close to or proximate to the chip selection terminal 12 a. The chip selection pads number one less than the number of stacked chips. The chip terminals 12 and the chip selection terminal 12 a are connected to the circuits formed within the die 11, while the chip selection pads 12 b, 12 c, 12 d are not connected to the circuits.
  • [0042]
    As shown in FIG. 3B, trenches 13, each having a predetermined depth, perforate the die 11 from the chip terminals 12, the chip selection terminal 12 a and the chip selection pads 12 b, 12 c, 12 d. The trenches 13 are formed by techniques such as a chemical etching method or a drilling method with a laser drill. The width of the trench 13 is smaller than the widths of the chip terminals 12, the chip selection terminal 12 a and the chip selection pads 12 b, 12 c, 12 d.
  • [0043]
    Then, as shown in FIG. 3C, the trenches 13 are filled with a conductive material, forming the trench wirings 14. Preferably, tungsten (W) is used as the conductive material, but other conductive materials may also be used. A conventional deposition technique such as Chemical Vaporization Deposition (CVD) is used in forming the trench wirings 14.
  • [0044]
    As shown in FIG. 3D, the first metal wirings 15 are formed on the upper surface of the die 11. The first metal wirings 15 are formed on the chip selection pads 12 b, 12 c, 12 d, but not formed on the chip selection terminal 12 a and the chip terminals 12. The first metal wirings 15 extend toward the chip selection terminal 12 a along the upper surface of the die 11, and are separated from each other. Various metals such as copper (Cu) or tungsten (W) can be used as the first metal wirings 15. A person skilled art will appreciate that other suitable conductive materials can be used in place. The first metal wirings 15 are formed by various methods. For example a metal layer is deposited on the whole upper surface of the die 11 and is etched using photoresist patterns to form the first metal wirings 15. Also, photoresist patterns are first coated on the upper surface of the die 11, and the metal layer is deposited thereon.
  • [0045]
    As shown in FIG. 3E, the first insulation layer 16 is formed on the upper surface of the die 11 including the first metal wirings 15. For the first insulation layer 16, an inorganic insulation layer such as a nitride layer or an organic layer such as a polyimide layer or an epoxy layer is used. The inorganic insulation layer is formed by a conventional deposition method, and the organic insulation layer is formed by a conventional spin coating method.
  • [0046]
    As shown in FIG. 3F, through holes 17 are formed by partially removing the first insulation layer 16. The through holes 17 are formed by a conventional photolithography method. The through holes 17 are disposed on the chip terminals 12 and the first metal wirings 15. The through holes 17 on the first metal wirings 15 are disposed between the neighboring trench wirings 14. One end of each first metal wiring 15 is connected to a corresponding one of the chip selection pads 12 b, 12 c, 12 d and the other end is connected to the through hole 17.
  • [0047]
    As shown in FIG. 3G, the through holes 17 are filled with a conductive material, thereby forming the first through wirings 18. The material and the forming method of the first through wirings 18 can be the same as those of the trench wirings 14.
  • [0048]
    As shown in FIG. 3H, the second metal wirings 19, 19 a are formed on the first insulation layer 16. The second metal wirings 19 are each connected to one of the chip selection pads 12 b, 12 c, 12 d through the first metal wirings 15 within the first insulation layer 16, and the isolated second metal wiring 19 a is disposed above the third chip selection pad 12 d. The second metal wirings 19 are not formed above the chip terminals 12 and are laterally offset from the chip selection terminal 12 a. The second metal wirings 19 extend toward the chip selection terminal 12 a along the upper surface of the first insulation layer 16. Therefore, one of the second metal wirings 19 extends partly above and partly offset from the chip selection terminal 12 a and the others extend above the chip selection pads 12 b, 12 c. The material and the forming method of the second metal wirings 19, 19 a can be the same as those of the first metal wirings 15.
  • [0049]
    Then, similar to the steps in FIGS. 3E to 3G, the second insulation layer 20 is formed on the first insulation layer 16. Through holes extend through the second insulation layer 20 and are filled with a conductive material, thereby forming the second through wirings 21. As shown in FIG. 31, the upper connection terminals 22, 22 a, 22 b, 22 c, 22 d are formed on the second insulation layer 20 and connected to the second through wirings 21. The upper connection terminals 22, 22 a, 22 b, 22 c, 22 d, each corresponds to one of the chip terminals 12, the chip selection terminal 12, and the chip selection pads 12 b, 12 c, 12 d. The upper connection terminal 22 above the chip terminal 12 is connected directly to the chip terminal 12. The upper connection terminal 22 a above the chip selection terminal 12 a is not connected to the chip selection terminal 12 a, but rather to the first chip selection pad 12 b. Likewise, each of the upper connection terminals 22 b, 22 c above the chip selection pads 12 b, 12 c, respectively, is not connected to the chip selection pads 12 b or 12 c, but connected to the neighboring chip selection pads 12 c, 12 d. The outermost upper connection terminal 22 d is connected to the isolated second metal wiring 19 a.
  • [0050]
    As shown in FIG. 3J, the lower surface of the die 11 is partially removed by a conventional etching method or a conventional grinding method such as wafer back lapping, so that the trench wirings 14 are exposed through the lower surface of the die 11.
  • [0051]
    As shown in FIG. 3K, lower connection terminals 23, 23 a, 23 b, 23 c, 23 d are formed on the lower surface of the die 11 so as to be electrically connected to the trench wirings 14. Therefore, each of the lower connection terminals 23, 23 a, 23 b, 23 c, 23 d is connected to a corresponding one of the chip terminals 12, the chip selection terminal 12 a, and the chip selection pads 12 b, 12 c, 12 d through the trench wirings 14.
  • [0052]
    The semiconductor integrated circuit chip 10 in FIG. 2 is manufactured by the above-described processing steps. A plurality of the chips are stacked, and the upper connection terminals of a lower chip are attached to the lower connection terminals of an upper chip, thus obtaining the multi-chip package 100 in FIG. 1. Since each chip of the multi-chip package has the same structure, plural chips at the wafer-level can be collectively manufactured and separated into individual chips.
  • [0053]
    The second metal wirings of the above-described first embodiment of the present invention may be used as the upper connection terminals. Further, in stacking the chips, an adhesive layer or an anisotropic conductive film may be interposed between the chips. FIG. 4 is a cross-sectional view of a chip-level, three-dimensional, multi-chip package 200 in accordance with another embodiment of the present invention.
  • [0054]
    In accordance with the second embodiment of the present invention, the multi-chip package 200 comprises three (3) integrated circuit chips 210, 220, 230. Therefore, each of the chip 210, 220, 230 comprises two (2) chip selection pads 12 b, 12 c. The insulation layer 16 is formed on the upper surface of the die 11, and the metal wirings 15 connected to the chip selection pads 12 b, 12 c are formed within the insulation layer 16. Then, through holes extend through the insulation layer 16 to expose a portion of the metal wirings 15 and are filled with a conductive material, thereby forming the through wirings 18.
  • [0055]
    The through wirings 18 are connected to the upper connection terminals 22 a, 22 b on the insulation layer 16. The upper connection terminal 22 is disposed above the chip terminal 12, and the isolated upper connection terminal 22 c is disposed above the outermost chip selection pad 12 c. The chip selection pad 12 a is not connected to any of the upper connection terminals 22, 22 a, 22 b, 22 c. The lower connection terminals 23, 23 a, 23 b, 23 c are formed on the lower surface of the die 11 correspondingly to the upper connection terminals 22, 22 a, 22 b, 22 c. Each of the chip terminal 12, the chip selection terminal 12 a, and the chip selection pads 12 b, 12 c is connected to a corresponding one of the lower connection terminals 23, 23 a, 23 b, 23 c through the trench wirings 14.
  • [0056]
    The chips 210, 220, 230 can be stacked using an Anisotropic Conductive Film (ACF) or an Anisotropic Conductive Adhesive (ACA). The ACF 25 or the ACA comprises an insulation film 24 a or an insulating adhesive, and conductive particles 24 b dispersed within the insulation film 24 a or the insulating adhesive. As the insulation film 24 a or the insulation adhesive is compressed by the upper connection terminals 22, 22 a-22 c of a lower chip and the lower connection terminals 23, 23 a-23 c of an upper chip, the upper connection terminals 22, 22 a-22 c and the lower connection terminals 23, 23 a-23 c are electrically interconnected by the conductive particles 24 b. Thereby, the insulation film 24 a or the insulation adhesive attaches the chip to another chip. Instead of the ACF 25 or the ACA, other various insulation adhesives may be used as an adhesion layer.
  • [0057]
    In the above-described multi-chip package 200 of the second embodiment, the chip selection terminal 12 a of each chip 210, 220, 230 is separated from the chip selection terminal 12 a of another chip and connected to a corresponding one of the lower connection terminals 23 a-23 c of the lowermost chip 210.
  • [0058]
    In the multi-chip package of the present invention, the chip selection terminal of each chip is separated from the chip selection terminal of another chip by the chip selection pads formed on the chip. Therefore, the multi-chip package of the present invention does not require differently structured chips or any additional substrate. Accordingly, the present invention achieves the chip-level multi-chip package, using a simple process.
  • [0059]
    The wafer-level multi-chip package of the present invention reduces package size and increases mounting density, thereby minimizing signal delay.
  • [0060]
    Although the preferred embodiments of the present invention have been described in detail hereinabove, it should be understood that many variations and/or modifications of the basic inventive concepts herein taught which may appear to those skilled in the art will still fall within the spirit and scope of the present invention as defined in the appended claims.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6984882 *Jan 22, 2003Jan 10, 2006Renesas Technology Corp.Semiconductor device with reduced wiring paths between an array of semiconductor chip parts
US7064055Sep 5, 2003Jun 20, 2006Massachusetts Institute Of TechnologyMethod of forming a multi-layer semiconductor structure having a seamless bonding interface
US7067909Dec 30, 2003Jun 27, 2006Massachusetts Institute Of TechnologyMulti-layer integrated semiconductor structure having an electrical shielding portion
US7307003Dec 30, 2003Dec 11, 2007Massachusetts Institute Of TechnologyMethod of forming a multi-layer semiconductor structure incorporating a processing handle member
US7626257Jan 18, 2006Dec 1, 2009Infineon Technologies AgSemiconductor devices and methods of manufacture thereof
US7683459Jun 2, 2008Mar 23, 2010Hong Kong Applied Science and Technology Research Institute Company, Ltd.Bonding method for through-silicon-via based 3D wafer stacking
US7698470Aug 6, 2007Apr 13, 2010Qimonda AgIntegrated circuit, chip stack and data processing system
US7785931Jun 12, 2009Aug 31, 2010John TrezzaChip-based thermo-stack
US7785987Jan 30, 2009Aug 31, 2010John TrezzaIsolating chip-to-chip contact
US7791199Nov 22, 2006Sep 7, 2010Tessera, Inc.Packaged semiconductor chips
US7808111Nov 6, 2006Oct 5, 2010John TrezzaProcessed wafer via
US7829438Apr 13, 2007Nov 9, 2010Tessera, Inc.Edge connect wafer level stacking
US7843068 *Jun 29, 2006Nov 30, 2010Shinko Electric Industries Co., Ltd.Semiconductor chip and method of manufacturing the same
US7847412Jun 6, 2006Dec 7, 2010John TrezzaIsolating chip-to-chip contact
US7851348Jan 10, 2006Dec 14, 2010Abhay MisraRoutingless chip architecture
US7884483Jan 10, 2006Feb 8, 2011Cufer Asset Ltd. L.L.C.Chip connector
US7901989Jun 20, 2008Mar 8, 2011Tessera, Inc.Reconstituted wafer level stacking
US7919870Nov 6, 2006Apr 5, 2011Cufer Asset Ltd. L.L.C.Coaxial through chip connection
US7932584Feb 16, 2007Apr 26, 2011Cufer Asset Ltd. L.L.C.Stacked chip-based system and method
US7942182Jan 10, 2006May 17, 2011Cufer Asset Ltd. L.L.C.Rigid-backed, membrane-based chip tooling
US7944058Nov 21, 2005May 17, 2011Oki Semiconductor Co., Ltd.Semiconductor device and process for fabricating the same
US7946331Jan 10, 2006May 24, 2011Cufer Asset Ltd. L.L.C.Pin-type chip tooling
US7952195Dec 28, 2006May 31, 2011Tessera, Inc.Stacked packages with bridging traces
US7969015Jan 10, 2006Jun 28, 2011Cufer Asset Ltd. L.L.C.Inverse chip connector
US7989958Jan 10, 2006Aug 2, 2011Cufer Assett Ltd. L.L.C.Patterned contact
US8021922Jun 25, 2010Sep 20, 2011Cufer Asset Ltd. L.L.C.Remote chip attachment
US8022527Oct 20, 2010Sep 20, 2011Tessera, Inc.Edge connect wafer level stacking
US8043895Aug 7, 2008Oct 25, 2011Tessera, Inc.Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US8053903Feb 24, 2010Nov 8, 2011Cufer Asset Ltd. L.L.C.Chip capacitive coupling
US8067312Apr 16, 2010Nov 29, 2011Cufer Asset Ltd. L.L.C.Coaxial through chip connection
US8076764 *Dec 6, 2006Dec 13, 2011Elpida Memory Inc.Stacked type semiconductor memory device and chip selection circuit
US8076788Nov 8, 2010Dec 13, 2011Tessera, Inc.Off-chip vias in stacked chips
US8084851Feb 23, 2010Dec 27, 2011Cufer Asset Ltd. L.L.C.Side stacking apparatus and method
US8093729Jul 16, 2007Jan 10, 2012Cufer Asset Ltd. L.L.C.Electrically conductive interconnect system and method
US8154131Jan 10, 2006Apr 10, 2012Cufer Asset Ltd. L.L.C.Profiled contact
US8193615Jul 31, 2008Jun 5, 2012DigitalOptics Corporation Europe LimitedSemiconductor packaging process using through silicon vias
US8197626Apr 14, 2011Jun 12, 2012Cufer Asset Ltd. L.L.C.Rigid-backed, membrane-based chip tooling
US8197627Apr 15, 2011Jun 12, 2012Cufer Asset Ltd. L.L.C.Pin-type chip tooling
US8232194Oct 14, 2011Jul 31, 2012Cufer Asset Ltd. L.L.C.Process for chip capacitive coupling
US8283778Feb 16, 2007Oct 9, 2012Cufer Asset Ltd. L.L.C.Thermally balanced via
US8288278 *Nov 13, 2008Oct 16, 2012Samsung Electronics Co., Ltd.Semiconductor device having through electrode and method of fabricating the same
US8304923 *Mar 29, 2007Nov 6, 2012ADL Engineering Inc.Chip packaging structure
US8310036May 21, 2010Nov 13, 2012DigitalOptics Corporation Europe LimitedChips having rear contacts connected by through vias to front contacts
US8338289Oct 8, 2010Dec 25, 2012Shinko Electric Industries Co., Ltd.Method of manufacturing a semiconductor chip including a semiconductor substrate and a through via provided in a through hole
US8349654May 25, 2011Jan 8, 2013Tessera, Inc.Method of fabricating stacked packages with bridging traces
US8395267Oct 21, 2009Mar 12, 2013Nxp B.V.Through-substrate via and redistribution layer with metal paste
US8405196Feb 26, 2008Mar 26, 2013DigitalOptics Corporation Europe LimitedChips having rear contacts connected by through vias to front contacts
US8426957Apr 14, 2011Apr 23, 2013Tessera, Inc.Edge connect wafer level stacking
US8431435Oct 20, 2010Apr 30, 2013Tessera, Inc.Edge connect wafer level stacking
US8432045Dec 9, 2010Apr 30, 2013Tessera, Inc.Conductive pads defined by embedded traces
US8456015Jan 6, 2010Jun 4, 2013Cufer Asset Ltd. L.L.C.Triaxial through-chip connection
US8461672Jul 25, 2008Jun 11, 2013Tessera, Inc.Reconstituted wafer stack packaging with after-applied pad extensions
US8461673Feb 9, 2012Jun 11, 2013Tessera, Inc.Edge connect wafer level stacking
US8466542Mar 12, 2010Jun 18, 2013Tessera, Inc.Stacked microelectronic assemblies having vias extending through bond pads
US8476774Dec 12, 2011Jul 2, 2013Tessera, Inc.Off-chip VIAS in stacked chips
US8487444 *Dec 4, 2009Jul 16, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Three-dimensional system-in-package architecture
US8513789Feb 9, 2007Aug 20, 2013Tessera, Inc.Edge connect wafer level stacking with leads extending along edges
US8513794Oct 17, 2011Aug 20, 2013Tessera, Inc.Stacked assembly including plurality of stacked microelectronic elements
US8551815Aug 1, 2008Oct 8, 2013Tessera, Inc.Stack packages using reconstituted wafers
US8569876Nov 22, 2006Oct 29, 2013Tessera, Inc.Packaged semiconductor chips with array
US8587126Mar 18, 2011Nov 19, 2013Tessera, Inc.Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8593891Sep 22, 2011Nov 26, 2013Elpida Memory, Inc.Semiconductor device and test method thereof
US8610259Sep 17, 2010Dec 17, 2013Tessera, Inc.Multi-function and shielded 3D interconnects
US8610264Dec 8, 2010Dec 17, 2013Tessera, Inc.Compliant interconnects in wafers
US8629059Dec 16, 2010Jan 14, 2014Samsung Electronics Co., Ltd.Methods of forming integrated circuit chips having vertically extended through-substrate vias therein
US8637968Dec 2, 2010Jan 28, 2014Tessera, Inc.Stacked microelectronic assembly having interposer connecting active chips
US8643186Jul 29, 2010Feb 4, 2014Cufer Asset Ltd. L.L.C.Processed wafer via
US8653644Feb 28, 2012Feb 18, 2014Tessera, Inc.Packaged semiconductor chips with array
US8659163Sep 17, 2012Feb 25, 2014Samsung Electronics Co., Ltd.Semiconductor device having through electrode and method of fabricating the same
US8664666Apr 25, 2011Mar 4, 2014Oki Semiconductor Co., Ltd.Semiconductor device and process for fabricating the same
US8680662Jun 15, 2009Mar 25, 2014Tessera, Inc.Wafer level edge stacking
US8704347Aug 16, 2010Apr 22, 2014Tessera, Inc.Packaged semiconductor chips
US8709871Nov 10, 2011Apr 29, 2014Junji YamadaStacked type semiconductor memory device and chip selection circuit
US8711573Feb 26, 2013Apr 29, 2014Mosaid Technologies IncorporatedUsing interrupted through-silicon-vias in integrated circuits adapted for stacking
US8717796Apr 10, 2013May 6, 2014Micron Technology, Inc.Memory dies, stacked memories, memory devices and methods
US8735205Nov 8, 2012May 27, 2014Invensas CorporationChips having rear contacts connected by through vias to front contacts
US8735287Jun 5, 2012May 27, 2014Invensas Corp.Semiconductor packaging process using through silicon vias
US8736066Mar 18, 2011May 27, 2014Tessera, Inc.Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8772908Aug 20, 2012Jul 8, 2014Tessera, Inc.Conductive pads defined by embedded traces
US8791575Jul 23, 2010Jul 29, 2014Tessera, Inc.Microelectronic elements having metallic pads overlying vias
US8796135Jul 23, 2010Aug 5, 2014Tessera, Inc.Microelectronic elements with rear contacts connected with via first or via middle structures
US8796828Dec 12, 2013Aug 5, 2014Tessera, Inc.Compliant interconnects in wafers
US8809190Dec 12, 2013Aug 19, 2014Tessera, Inc.Multi-function and shielded 3D interconnects
US8846445Jun 20, 2011Sep 30, 2014Cufer Asset Ltd. L.L.C.Inverse chip connector
US8847380Sep 17, 2010Sep 30, 2014Tessera, Inc.Staged via formation from both sides of chip
US8848473Nov 22, 2013Sep 30, 2014Ps4 Luxco S.A.R.L.Semiconductor device and test method thereof
US8883562Jun 6, 2013Nov 11, 2014Tessera, Inc.Reconstituted wafer stack packaging with after-applied pad extensions
US8912043Jul 18, 2013Dec 16, 2014Qualcomm IncorporatedDual-side interconnected CMOS for stacked integrated circuits
US8924903Nov 3, 2011Dec 30, 2014Ps4 Luxco S.A.R.L.Semiconductor device having plural memory chip
US8953355May 6, 2014Feb 10, 2015Micron Technology, Inc.Memory dies, stacked memories, memory devices and methods
US8999810Aug 19, 2013Apr 7, 2015Tessera, Inc.Method of making a stacked microelectronic package
US9035444Jun 11, 2012May 19, 2015Ps4 Luxco S.A.R.L.Semiconductor device having penetration electrodes penetrating through semiconductor chip
US9041218Feb 24, 2014May 26, 2015Samsung Electronics Co., Ltd.Semiconductor device having through electrode and method of fabricating the same
US9048234Jun 11, 2013Jun 2, 2015Tessera, Inc.Off-chip vias in stacked chips
US9070678Feb 11, 2014Jun 30, 2015Tessera, Inc.Packaged semiconductor chips with array
US9093431Jan 16, 2014Jul 28, 2015Lapis Semiconductor Co., Ltd.Semiconductor device and process for fabricating the same
US9099296Oct 23, 2013Aug 4, 2015Tessera, Inc.Stacked microelectronic assembly with TSVS formed in stages with plural active chips
US9099540 *Apr 16, 2013Aug 4, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Three-dimensional system-in-package architecture
US9147635Dec 13, 2010Sep 29, 2015Cufer Asset Ltd. L.L.C.Contact-based encapsulation
US9219035Jan 13, 2014Dec 22, 2015Samsung Electronics Co., Ltd.Integrated circuit chips having vertically extended through-substrate vias therein
US9224649Aug 4, 2014Dec 29, 2015Tessera, Inc.Compliant interconnects in wafers
US9252081Dec 4, 2014Feb 2, 2016Ps4 Luxco S.A.R.L.Semiconductor device having plural memory chip
US9269692Mar 25, 2014Feb 23, 2016Tessera, Inc.Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US9312031Aug 23, 2014Apr 12, 2016Ps4 Luxco S.A.R.L.Semiconductor device and test method thereof
US9324629Mar 30, 2007Apr 26, 2016Cufer Asset Ltd. L.L.C.Tooling for coupling multiple electronic chips
US9355948Jul 24, 2014May 31, 2016Tessera, Inc.Multi-function and shielded 3D interconnects
US9356000 *Mar 15, 2013May 31, 2016SK Hynix Inc.Semiconductor integrated circuit and semiconductor system with the same
US9362203Sep 27, 2014Jun 7, 2016Tessera, Inc.Staged via formation from both sides of chip
US9368476Jul 28, 2015Jun 14, 2016Tessera, Inc.Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US9378967Apr 6, 2015Jun 28, 2016Tessera, Inc.Method of making a stacked microelectronic package
US9548254Jun 29, 2015Jan 17, 2017Tessera, Inc.Packaged semiconductor chips with array
US9559041Jun 18, 2015Jan 31, 2017Lapis Semiconductor Co., Ltd.Semiconductor device and process for fabricating the same
US9620437Feb 18, 2016Apr 11, 2017Tessera, Inc.Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US9640437Jul 23, 2010May 2, 2017Tessera, Inc.Methods of forming semiconductor elements using micro-abrasive particle stream
US9754907Apr 20, 2016Sep 5, 2017Cufer Asset Ltd. L.L.C.Tooling for coupling multiple electronic chips
US20030234434 *Jan 22, 2003Dec 25, 2003Mitsubishi Denki Kabushiki KaishaSemiconductor device
US20040124538 *Sep 5, 2003Jul 1, 2004Rafael ReifMulti-layer integrated semiconductor structure
US20040126994 *Sep 5, 2003Jul 1, 2004Rafael ReifMethod of forming a multi-layer semiconductor structure having a seamless bonding interface
US20040219765 *Dec 30, 2003Nov 4, 2004Rafael ReifMethod of forming a multi-layer semiconductor structure incorporating a processing handle member
US20060087019 *Dec 30, 2003Apr 27, 2006Rafael ReifMulti-layer integrated semiconductor structure having an electrical shielding portion
US20060099796 *Dec 20, 2005May 11, 2006Rafael ReifMethod of forming a multi-layer semiconductor structure having a seam-less bonding interface
US20070001312 *Jun 29, 2006Jan 4, 2007Shinko Electric Industries Co., Ltd.Semiconductor chip and method of manufacturing the same
US20070126105 *Dec 6, 2006Jun 7, 2007Elpida Memory Inc.Stacked type semiconductor memory device and chip selection circuit
US20080064183 *Nov 8, 2007Mar 13, 2008Rafael ReifMethod of forming a multi-layer semiconductor structure incorporating a processing handle member
US20080083976 *Feb 9, 2007Apr 10, 2008Tessera, Inc.Edge connect wafer level stacking
US20080083977 *Apr 13, 2007Apr 10, 2008Tessera, Inc.Edge connect wafer level stacking
US20080116544 *Nov 22, 2006May 22, 2008Tessera, Inc.Packaged semiconductor chips with array
US20080116545 *Nov 22, 2006May 22, 2008Tessera, Inc.Packaged semiconductor chips
US20080157323 *Dec 28, 2006Jul 3, 2008Tessera, Inc.Stacked packages
US20080171413 *Jan 17, 2007Jul 17, 2008International Business Machines CorporationMethod of Reducing Detrimental STI-Induced Stress in MOSFET Channels
US20080237834 *Mar 29, 2007Oct 2, 2008Advanced Chip Engineering Technology Inc.Chip packaging structure and chip packaging process
US20080246136 *Feb 26, 2008Oct 9, 2008Tessera, Inc.Chips having rear contacts connected by through vias to front contacts
US20080265430 *Nov 21, 2005Oct 30, 2008Masamichi IshiharaSemiconductor Device an Process for Fabricating the Same
US20090039528 *Aug 7, 2008Feb 12, 2009Tessera, Inc.Wafer level stacked packages with individual chip selection
US20090039915 *Aug 6, 2007Feb 12, 2009Hermann RuckerbauerIntegrated Circuit, Chip Stack and Data Processing System
US20090043917 *Aug 6, 2007Feb 12, 2009Thilo WagnerElectronic Circuit and Method for Selecting an Electronic Circuit
US20090065907 *Jul 31, 2008Mar 12, 2009Tessera, Inc.Semiconductor packaging process using through silicon vias
US20090124072 *Nov 13, 2008May 14, 2009Samsung Electronics Co., Ltd.Semiconductor device having through electrode and method of fabricating the same
US20090160065 *Jun 20, 2008Jun 25, 2009Tessera, Inc.Reconstituted Wafer Level Stacking
US20090212381 *Feb 26, 2009Aug 27, 2009Tessera, Inc.Wafer level packages for rear-face illuminated solid state image sensors
US20090269888 *Jun 12, 2009Oct 29, 2009John TrezzaChip-based thermo-stack
US20090294916 *Jun 2, 2008Dec 3, 2009Hong Kong Applied Science and Technology Research Institute Company, Ltd.Bonding method for through-silicon-via based 3d wafer stacking
US20090316378 *Jun 15, 2009Dec 24, 2009Tessera Research LlcWafer level edge stacking
US20100053407 *Aug 26, 2009Mar 4, 2010Tessera, Inc.Wafer level compliant packages for rear-face illuminated solid state image sensors
US20100219503 *Feb 24, 2010Sep 2, 2010John TrezzaChip capacitive coupling
US20100225002 *Dec 4, 2009Sep 9, 2010Taiwan Semiconductor Manufacturing Company, Ltd.Three-Dimensional System-in-Package Architecture
US20100225006 *May 21, 2010Sep 9, 2010Tessera, Inc.Chips having rear contacts connected by through vias to front contacts
US20100230795 *Mar 12, 2010Sep 16, 2010Tessera Technologies Hungary Kft.Stacked microelectronic assemblies having vias extending through bond pads
US20110006432 *Jul 25, 2008Jan 13, 2011Tessera, Inc.Reconstituted wafer stack packaging with after-applied pad extensions
US20110012259 *Aug 16, 2010Jan 20, 2011Tessera, Inc.Packaged semiconductor chips
US20110027990 *Oct 8, 2010Feb 3, 2011Shinko Electric Industries Co., Ltd.Semiconductor chip and method of manufacturing the same
US20110031629 *Oct 20, 2010Feb 10, 2011Tessera, Inc.Edge connect wafer level stacking
US20110033979 *Oct 20, 2010Feb 10, 2011Tessera, Inc.Edge connect wafer level stacking
US20110049696 *Nov 8, 2010Mar 3, 2011Tessera, Inc.Off-chip vias in stacked chips
US20110086486 *Dec 16, 2010Apr 14, 2011Ho-Jin LeeMethods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein
US20110187007 *Apr 14, 2011Aug 4, 2011Tessera, Inc.Edge connect wafer level stacking
US20110201178 *Apr 25, 2011Aug 18, 2011Oki Semiconductor Co., Ltd.Semiconductor device and process for fabricating the same
US20110210452 *Oct 21, 2009Sep 1, 2011Nxp B.V.Through-substrate via and redistribution layer with metal paste
US20110230013 *May 25, 2011Sep 22, 2011Tessera, Inc.Stacked packages with bridging traces
US20130228920 *Apr 17, 2013Sep 5, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Protection layer for adhesive material at wafer edge
US20130230985 *Apr 16, 2013Sep 5, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Three-Dimensional System-in-Package Architecture
US20140175667 *Mar 15, 2013Jun 26, 2014SK Hynix Inc.Semiconductor integrated circuit and semiconductor system with the same
CN101840912A *Mar 5, 2010Sep 22, 2010台湾积体电路制造股份有限公司半导体装置及其制造方法
CN102844862A *Apr 6, 2011Dec 26, 2012高通股份有限公司Dual-side interconnected cmos for stacked integrated circuits
CN103887288A *Nov 13, 2013Jun 25, 2014爱思开海力士有限公司Semiconductor Integrated Circuit And Semiconductor System With The Same
CN104465567A *Sep 17, 2014Mar 25, 2015南亚科技股份有限公司Chip package and method for forming the same
CN104779218A *Aug 26, 2014Jul 15, 2015南亚科技股份有限公司Chip package
EP1587141A2Apr 4, 2005Oct 19, 2005Sun Microsystems, Inc.Method and apparatus involving capacitively coupled communication within a stack of laminated chips
EP1587141A3 *Apr 4, 2005Dec 5, 2007Sun Microsystems, Inc.Method and apparatus involving capacitively coupled communication within a stack of laminated chips
EP1686623A1 *Aug 10, 2004Aug 2, 2006Japan Science and Technology AgencySemiconductor device and process for fabricating the same
EP1686623A4 *Aug 10, 2004Jul 11, 2007Japan Science & Tech AgencySemiconductor device and process for fabricating the same
EP2474030A1 *Aug 27, 2010Jul 11, 2012MOSAID Technologies IncorporatedUsing interrupted through-silicon-vias in integrated circuits adapted for stacking
EP2474030A4 *Aug 27, 2010Dec 4, 2013Mosaid Technologies IncUsing interrupted through-silicon-vias in integrated circuits adapted for stacking
EP2534659A2 *Feb 10, 2011Dec 19, 2012Micron Technology, Inc.Memory dies, stacked memories, memory devices and methods
EP2534659A4 *Feb 10, 2011Aug 28, 2013Micron Technology IncMemory dies, stacked memories, memory devices and methods
EP2546873A3 *Jun 12, 2012May 29, 2013Elpida Memory, Inc.Semiconductor device
WO2004061962A2 *Dec 30, 2003Jul 22, 2004Massachusetts Institute Of TechnologyMulti-layer integrated semiconductor structure
WO2004061962A3 *Dec 30, 2003Nov 11, 2004Massachusetts Inst TechnologyMulti-layer integrated semiconductor structure
WO2007082854A1 *Jan 15, 2007Jul 26, 2007Infineon Technologies AgSemiconductor devices and methods of manufacture thereof
WO2010049852A1 *Oct 21, 2009May 6, 2010Nxp B.V.Through-substrate via and redistribution layer with metal paste
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