US20020113724A1 - Code independent charge transfer scheme for switched-capacitor digital-to-analog converter - Google Patents
Code independent charge transfer scheme for switched-capacitor digital-to-analog converter Download PDFInfo
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- US20020113724A1 US20020113724A1 US09/785,690 US78569001A US2002113724A1 US 20020113724 A1 US20020113724 A1 US 20020113724A1 US 78569001 A US78569001 A US 78569001A US 2002113724 A1 US2002113724 A1 US 2002113724A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
- H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
- H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
- H03M1/0663—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using clocked averaging
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/80—Simultaneous conversion using weighted impedances
- H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
- H03M1/804—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices with charge redistribution
Definitions
- the disclosure relates to switched-capacitor digital-to-analog (DAC) converter circuitry in which crossing switches for each capacitor are used thereby eliminating any cross interference between blocks sharing the same reference voltages.
- DAC digital-to-analog
- Switched-capacitor digital-to-analog (DAC) converters are popular blocks in mixed-signal chips. Differential structures are typically used in switched-capacitor DAC to suppress noise and odd order harmonic distortion.
- control signals ⁇ 1 and ⁇ 2 (timing signals) operate in two non-overlapping time intervals (or clock phases).
- DAC 10 samples a reference voltage and during clock phase ⁇ 2 transfers charge to integrator 20 together with negative reference v ref n 12 ( ⁇ v ref ) and positive reference v ref p 11 (+v ref ).
- Reference voltages v ref p 11 and v ref n 12 may be considered as input voltages to DAC 10 .
- Integrator 20 includes an operational amplifier (op amp) 21 , a first integrator capacitor 22 connected between non-inverting output lead 23 and inverting input lead 24 , and a second integrator capacitor 25 connected between inverting output lead 26 and non-inverting input lead 27 .
- op amp operational amplifier
- Switched-capacitor DAC 10 includes input lines 11 and 12 receiving the positive and negative terminals of a reference voltage v ref .
- a first set of input capacitors 13 are coupled to input lines 11 and 12 through a first switching circuit 14 and to the input leads 24 and 27 of op amp 21 through a second switching circuit 15 .
- a second set of input capacitors 16 as part of a fully differential structure are similarly coupled to input lines 11 and 12 through first switching circuit 14 and to input leads 24 and 27 of op amp 21 through second switching circuit 15 .
- Capacitors 13 and 16 sample (i.e., are charged by) the reference voltage v ref through switching circuit 14 and transfer charge to capacitors 22 and 25 through switching circuit 15 .
- the values of capacitors 13 and 16 are preferably equal as are the values of capacitors 22 and 25 .
- y i and y ib can be derived from a binary (or 2's complementary) code to thermometer code converter.
- Switching circuit 15 includes switches 19 and 30 , switches 19 being controlled by signal ⁇ 1 alone and switches 30 being controlled by signals ⁇ 2 alone see FIG. 1.
- Switching circuit 14 includes a first set of switches 17 connected between input lines 11 and the left plate of capacitors 13 .
- a second switch 18 is connected between input lines 12 and the left plate of capacitor 13 .
- a set of switches 17 are connected between input lines 12 and the left plate of capacitors 16 .
- a set of switches 18 are connected between input line 11 and the left plate of capacitors 16 .
- Switching circuit 15 includes a first switch 19 connected between the right plate of capacitors 13 and the inverting input lead 24 of op amp 21 and similarly a second switch 19 connected between the right plate of capacitors 16 and the non-inverting input lead 27 of op amp 21 .
- a switch 30 is connected between the right plate of capacitors 13 and the non-inverting input lead 24 of op amp 21 .
- a switch 30 is connected between the right plate of capacitor 16 and the non-inverting input lead 27 of op amp 21 .
- Switches 19 are controlled by a control signal ⁇ 1 while switches 30 are controlled by a control
- input capacitors 13 and 16 operate to sample reference voltages 11 and 12 through switching circuit 14 and transfer charge to integrating capacitors 22 and 25 through switching circuit 15 .
- the arrangement of input capacitors enables reference voltages to be sampled during both time intervals and charge to be transferred during both time intervals.
- the timing diagram of FIG. 1 assumes that the digital code signal y 1 remains stable during a single period of signals ⁇ 1 and ⁇ 2 .
- the DAC of FIG. 2 operates effectively to draw charge from references v ref p and v ref n and the charge depends on the previous digital code. Since references v ref p and v ref n always have certain output impedance, the derivative of the output signals 32 and 33 will ride on the references, thereby creating cross coupling and interference with other circuit blocks sharing the same references.
- An exemplary embodiment of the present invention relates to a switched-capacitor DAC system configured to receive a digital code signal.
- the DAC system includes a first switched-capacitor branch 80 and a second switched-capacitor branch which are dependent on the digital code signals. Further, the DAC system includes another switching circuit that includes a first and second sampling switch and a first and second discharge switch. The first and second sampling switches operate substantially in unison to sample signals from the first branch circuit and the second branch circuit and provide an output to an integrator.
- Another exemplary embodiment of the present invention relates to a switched-capacitor DAC system configured to receive a digital code signal.
- the DAC system includes at least one digital code dependent switching circuit, receiving the digital code signal.
- the DAC system also includes at least one reference input switching circuit. Then the at least one reference input switching circuit isolates from the digital code dependent switching circuit by at least one capacitor.
- Yet another exemplary embodiment of the present invention relates to a switched-capacitor DAC system configured to receive a digital code signal having an integrator circuit including an op amp having first and second input leads, first and second output leads, and first and second integrator capacitors respectively connected between the first and second input leads and the first and second output leads.
- the DAC system includes a first switching circuit coupled to a reference input. The first switching circuit output is dependent on the digital code signal.
- the DAC system also includes at least one first input capacitor to be charged through the reference inputs and the first switching circuit. Further, the DAC system includes a second switching circuit coupled to the reference input. The first switching circuit output is dependent on the digital code signal.
- the DAC system includes at least one second input capacitor to be charged by the output of the second switching circuit.
- the DAC system includes a third switching circuit that includes at least one switch responding according to the digital code signal and at least one switch responding to the complement of the digital code signal. The third switching circuit is coupled to the output of the first switching circuit through at least one capacitor.
- a fourth switching circuit includes at least one switch responsive to the digital code signal and at least one switch responsive to the complement of the digital code signal. The fourth switching circuit is coupled to the output of the second switching circuit through at least one capacitor.
- a fifth switching circuit includes a first switch coupled to the third switching circuit and receiving signals according to the digital code and the first switch coupled to the fourth switching circuit configured to receive signals according to the complement of the digital code.
- the fifth switching circuit also including a second switch coupled to the third switching circuit and receiving a signal according to the complement of the digital code and the second switch coupled to the fourth switching circuit and receiving a signal according to the digital code.
- the fifth switching circuit being coupled to the input of the integrator circuit.
- FIG. 2 is a circuit diagram of a switched-capacitor digital-to-analog converter of the prior art.
- FIG. 3 is an inverted switched-capacitor digital-to-analog converter which draws code-independent charge from references.
- a digital-to-analog converter 40 plus integrator 45 which has two crossing switches 74 and 78 for capacitors 77 and 80 respectively, are placed on the op amp side of converter 40 controlled by clock phase ⁇ 2 . Because, in each clock period, each reference will draw the same charge from the DAC switching operation, cross interference between blocks sharing the same references will be eliminated.
- a reference signal v ref p is supplied to inputs 51 and 52 which are coupled to switches 53 and 54 respectively and signal v ref n are applied to inputs 55 and 56 which are coupled to switches 57 and 58 respectively.
- Switches 53 and 58 are controlled by clock phase ⁇ 1 while switches 54 and 57 are controlled by clock phase ⁇ 2 (clock phases see FIG. 1).
- Switches 57 and 53 (making up a first input or a first reference switching circuit) are coupled to the left plate of capacitors 60 while switches 58 and 54 (making up a second input or a second reference switching circuit) are coupled to the left plate of capacitors 61 . Therefore, dependent on the states of switches 57 or 53 , capacitors 60 are charged accordingly. Similarly, depending on the states of switches 58 and 54 , capacitors 61 are charged according to input references v ref n and v ref p .
- a second switching circuit 70 includes a switch 71 having an input coupled to the right hand plate of capacitors 60 according to digital code y ib and an input coupled to the right hand plate of capacitor 61 according to digital code complement y 1 . Switch 71 is controlled by clock phase ⁇ 1 and is coupled to ground 72 .
- Switching circuit 70 also includes a switch 73 that is coupled on its input side to the right hand plate of capacitors 61 according to the digital code y ib and to the right hand plate of capacitors 60 according to digital code complement y i and is coupled to ground 72 on the output side. Switch 73 is controlled by clock phase ⁇ 1 and is coupled to ground 72 . Switching circuit 70 also includes a switch 74 , controlled by clock phase ⁇ 2 that is coupled, on the input side, to the right hand plate of capacitors 60 according to digital code y i and to the right handplate of capacitors 61 according to digital code complement y ib and coupled to inverting input lead 75 to op amp 76 and to integrating capacitor 77 .
- Switching circuit 70 further includes switch 78 , coupled to the right hand plate of capacitors 60 according to digital code complement y ib and the right handplate of capacitors 61 according to digital code y i on the input side and to non-inverting input 79 of op amp 76 and to integrating capacitor 80 on the output side.
- switch 74 receives a v ref n signal according to digital code according to switches 62 and 57 and v ref p according to digital code complement determined by switches 65 and 54 in complementary branch 81 .
- switch 78 receives a signal, when ⁇ 2 is high from v ref n based on complementary digital code switch 64 and switch 57 in branch 80 and v ref p according to digital code switch 63 and switch 54 in branch 80 .
- Switching circuits 70 , 80 and 81 are configured to provide a differential signal to integrator 45 of DAC 40 in such a manner as to allow isolation of reference inputs 51 , 52 , 55 , and 56 from the digital code inputs.
- switching circuit 70 is an effective structure for carrying out the functions required for isolation, other circuits may be applied without departing from the scope of the invention.
Abstract
Description
- The disclosure relates to switched-capacitor digital-to-analog (DAC) converter circuitry in which crossing switches for each capacitor are used thereby eliminating any cross interference between blocks sharing the same reference voltages.
- Switched-capacitor digital-to-analog (DAC) converters are popular blocks in mixed-signal chips. Differential structures are typically used in switched-capacitor DAC to suppress noise and odd order harmonic distortion.
- Referring now to FIG. 1, as is conventional for a switched-capacitor circuit, control signals Φ1 and Φ2 (timing signals) operate in two non-overlapping time intervals (or clock phases).
- With each input capacitor's equal size (a m bit DAC has2 m−1=n unit element capacitors) or multiple of unit size capacitor for better matching, a typical implementation of a fully differential switched-capacitor DAC is depicted in FIG. 2, in which a prior art switched-capacitor DAC system is shown including a
DAC 10 and anintegrator 20. During clock phase Φ1,DAC 10 samples a reference voltage and during clock phase Φ2 transfers charge tointegrator 20 together with negative reference vrefn 12 (−vref) and positive reference vrefp 11 (+vref).Reference voltages v refp 11 andv refn 12 may be considered as input voltages toDAC 10.Integrator 20 includes an operational amplifier (op amp) 21, afirst integrator capacitor 22 connected betweennon-inverting output lead 23 and invertinginput lead 24, and asecond integrator capacitor 25 connected between invertingoutput lead 26 and non-invertinginput lead 27. - Switched-
capacitor DAC 10 includesinput lines input capacitors 13 are coupled toinput lines first switching circuit 14 and to the input leads 24 and 27 ofop amp 21 through asecond switching circuit 15. A second set ofinput capacitors 16 as part of a fully differential structure are similarly coupled toinput lines first switching circuit 14 and to input leads 24 and 27 ofop amp 21 throughsecond switching circuit 15.Capacitors switching circuit 14 and transfer charge tocapacitors switching circuit 15. The values ofcapacitors capacitors - Depending on the individual digital code signal yi and yib, where yib is the complement of yi, i=1, 2, . . . n. If all yi equal to 1 represents maximum value of DAC and all yi equal to 0 represents minimum value of DAC. To an m bit DAC, yi and yib can be derived from a binary (or 2's complementary) code to thermometer code converter.
Switching circuit 14 includesswitches 17 which are controlled by combination logic Φ1 yi+Φ2 yib of (timing signal) Φ1, Φ2 and digital code yi and yib, where i=1,2, . . . , n and theswitches 18 which are controlled by a different way of Φ1 yi+Φ2 yib of Φ1, Φ2 and digital code yi and yib, where i=1,2, . . . , n. Switchingcircuit 15 includesswitches switches 19 being controlled by signal Φ1 alone andswitches 30 being controlled by signals Φ2 alone see FIG. 1. -
Switching circuit 14 includes a first set ofswitches 17 connected betweeninput lines 11 and the left plate ofcapacitors 13. Asecond switch 18 is connected betweeninput lines 12 and the left plate ofcapacitor 13. A set ofswitches 17 are connected betweeninput lines 12 and the left plate ofcapacitors 16. A set ofswitches 18 are connected betweeninput line 11 and the left plate ofcapacitors 16.Switching circuit 15 includes afirst switch 19 connected between the right plate ofcapacitors 13 and the invertinginput lead 24 ofop amp 21 and similarly asecond switch 19 connected between the right plate ofcapacitors 16 and thenon-inverting input lead 27 ofop amp 21. Aswitch 30 is connected between the right plate ofcapacitors 13 and thenon-inverting input lead 24 ofop amp 21. Similarly, aswitch 30 is connected between the right plate ofcapacitor 16 and thenon-inverting input lead 27 ofop amp 21.Switches 19 are controlled by a control signal Φ1 whileswitches 30 are controlled by a control signal Φ2. - As should be readily understood by those skilled in the art,
input capacitors reference voltages circuit 14 and transfer charge to integratingcapacitors switching circuit 15. The arrangement of input capacitors enables reference voltages to be sampled during both time intervals and charge to be transferred during both time intervals. The timing diagram of FIG. 1 assumes that the digital code signal y1 remains stable during a single period of signals Φ1 and Φ2. The DAC of FIG. 2 operates effectively to draw charge from references vrefp and vrefn and the charge depends on the previous digital code. Since references vrefp and vrefn always have certain output impedance, the derivative of theoutput signals - Accordingly, there is a need for a code-independent charge transfer scheme for switched-capacitor digital-to-analog converters which reduces complexity of the voltage references and achieves signal-independent charge drawn from the reference, without the use of multiple references or dummy circuitry or without using references with very low output impedance.
- An exemplary embodiment of the present invention relates to a switched-capacitor DAC system configured to receive a digital code signal. The DAC system includes a first switched-
capacitor branch 80 and a second switched-capacitor branch which are dependent on the digital code signals. Further, the DAC system includes another switching circuit that includes a first and second sampling switch and a first and second discharge switch. The first and second sampling switches operate substantially in unison to sample signals from the first branch circuit and the second branch circuit and provide an output to an integrator. - Another exemplary embodiment of the present invention relates to a switched-capacitor DAC system configured to receive a digital code signal. The DAC system includes at least one digital code dependent switching circuit, receiving the digital code signal. The DAC system also includes at least one reference input switching circuit. Then the at least one reference input switching circuit isolates from the digital code dependent switching circuit by at least one capacitor.
- Yet another exemplary embodiment of the present invention relates to a switched-capacitor DAC system configured to receive a digital code signal having an integrator circuit including an op amp having first and second input leads, first and second output leads, and first and second integrator capacitors respectively connected between the first and second input leads and the first and second output leads. The DAC system includes a first switching circuit coupled to a reference input. The first switching circuit output is dependent on the digital code signal. The DAC system also includes at least one first input capacitor to be charged through the reference inputs and the first switching circuit. Further, the DAC system includes a second switching circuit coupled to the reference input. The first switching circuit output is dependent on the digital code signal. Further still, the DAC system includes at least one second input capacitor to be charged by the output of the second switching circuit. Yet further still, the DAC system includes a third switching circuit that includes at least one switch responding according to the digital code signal and at least one switch responding to the complement of the digital code signal. The third switching circuit is coupled to the output of the first switching circuit through at least one capacitor. Yet further still, a fourth switching circuit includes at least one switch responsive to the digital code signal and at least one switch responsive to the complement of the digital code signal. The fourth switching circuit is coupled to the output of the second switching circuit through at least one capacitor. Yet further still, a fifth switching circuit includes a first switch coupled to the third switching circuit and receiving signals according to the digital code and the first switch coupled to the fourth switching circuit configured to receive signals according to the complement of the digital code. The fifth switching circuit also including a second switch coupled to the third switching circuit and receiving a signal according to the complement of the digital code and the second switch coupled to the fourth switching circuit and receiving a signal according to the digital code. The fifth switching circuit being coupled to the input of the integrator circuit.
- The invention will become more fully understood from the following detailed description, taken in conjunction with the accompanying drawings, wherein like reference numerals refer to like elements, in which:
- FIG. 1 is a timing diagram of clock phases Φ1, Φ2 and digital code y1, where i=1, . . . , n;
- FIG. 2 is a circuit diagram of a switched-capacitor digital-to-analog converter of the prior art; and
- FIG. 3 is an inverted switched-capacitor digital-to-analog converter which draws code-independent charge from references.
- Referring to FIG. 3, a digital-to-
analog converter 40plus integrator 45, which has twocrossing switches capacitors 77 and 80 respectively, are placed on the op amp side ofconverter 40 controlled by clock phase Φ2. Because, in each clock period, each reference will draw the same charge from the DAC switching operation, cross interference between blocks sharing the same references will be eliminated. - In operation, a reference signal vref
p is supplied to inputs 51 and 52 which are coupled toswitches 53 and 54 respectively and signal vrefn are applied toinputs 55 and 56 which are coupled toswitches Switches 53 and 58 are controlled by clock phase Φ1 whileswitches Switches 57 and 53 (making up a first input or a first reference switching circuit) are coupled to the left plate ofcapacitors 60 whileswitches 58 and 54 (making up a second input or a second reference switching circuit) are coupled to the left plate ofcapacitors 61. Therefore, dependent on the states ofswitches 57 or 53,capacitors 60 are charged accordingly. Similarly, depending on the states ofswitches capacitors 61 are charged according to input references vrefn and vrefp . - A digital code signal is applied to
switches second switching circuit 70 includes a switch 71 having an input coupled to the right hand plate ofcapacitors 60 according to digital code yib and an input coupled to the right hand plate ofcapacitor 61 according to digital code complement y1. Switch 71 is controlled by clock phase Φ1 and is coupled toground 72.Switching circuit 70 also includes aswitch 73 that is coupled on its input side to the right hand plate ofcapacitors 61 according to the digital code yib and to the right hand plate ofcapacitors 60 according to digital code complement yi and is coupled to ground 72 on the output side.Switch 73 is controlled by clock phase Φ1 and is coupled toground 72.Switching circuit 70 also includes aswitch 74, controlled by clock phase Φ2 that is coupled, on the input side, to the right hand plate ofcapacitors 60 according to digital code yi and to the right handplate ofcapacitors 61 according to digital code complement yib and coupled to invertinginput lead 75 toop amp 76 and to integrating capacitor 77.Switching circuit 70 further includesswitch 78, coupled to the right hand plate ofcapacitors 60 according to digital code complement yib and the right handplate ofcapacitors 61 according to digital code yi on the input side and tonon-inverting input 79 ofop amp 76 and to integratingcapacitor 80 on the output side. - Accordingly, switch74 receives a vref
n signal according to digital code according toswitches p according to digital code complement determined byswitches complementary branch 81. Conversely, switch 78 receives a signal, when Φ2 is high from vrefn based on complementarydigital code switch 64 and switch 57 inbranch 80 and vrefp according todigital code switch 63 and switch 54 inbranch 80. - According to scheme, charges drawing from
references 51, 52, 55, and 56 are same during each clock period. Therefore, charge drawing fromreferences 51, 52, 55, and 56 are completely independent of the digital code according toswitches -
Switching circuits integrator 45 ofDAC 40 in such a manner as to allow isolation ofreference inputs 51, 52, 55, and 56 from the digital code inputs. However, it should be noted that although switchingcircuit 70 is an effective structure for carrying out the functions required for isolation, other circuits may be applied without departing from the scope of the invention. - It is understood that, while the detailed drawings and specific examples given describe exemplary embodiments of the present invention, they are for the purposes of illustration only. The apparatus and method in the invention is not limited to the precise details, circuitry, and functioning disclosed. For example, although particular circuitry configurations are shown, other paths which may be functionally equivalent may be made as part of the scope of the invention. Accordingly, various changes may be made without departing from the scope of the present invention as defined in the following claims.
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JP3852721B2 (en) * | 1997-07-31 | 2006-12-06 | 旭化成マイクロシステム株式会社 | D / A converter and delta-sigma type D / A converter |
US6271784B1 (en) * | 1997-08-12 | 2001-08-07 | Analog Devices, Inc. | Capacitor-based digital-to-analog converter with continuous time output |
US6144331A (en) * | 1998-04-08 | 2000-11-07 | Texas Instruments Incorporated | Analog to digital converter with a differential output resistor-digital-to-analog-converter for improved noise reduction |
-
2001
- 2001-02-16 US US09/785,690 patent/US6437720B1/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040131131A1 (en) * | 2003-01-03 | 2004-07-08 | Peach Charles T. | Double-sampled, sample-and-hold circuit with downconversion |
US20070197184A1 (en) * | 2006-02-23 | 2007-08-23 | Yerazunis William S | Method and apparatus for minimizing harmonic interference in synchronous radio receivers by apodization |
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