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Publication numberUS20020119396 A1
Publication typeApplication
Application numberUS 09/956,605
Publication dateAug 29, 2002
Filing dateSep 18, 2001
Priority dateOct 28, 1999
Also published asUS6428942
Publication number09956605, 956605, US 2002/0119396 A1, US 2002/119396 A1, US 20020119396 A1, US 20020119396A1, US 2002119396 A1, US 2002119396A1, US-A1-20020119396, US-A1-2002119396, US2002/0119396A1, US2002/119396A1, US20020119396 A1, US20020119396A1, US2002119396 A1, US2002119396A1
InventorsHunt Jiang, Mark McCormack, Albert Chan, Kuo-Chuan Liu
Original AssigneeJiang Hunt Hang, Mccormack Mark, Chan Albert W., Kuo-Chuan Liu
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Structure and method for forming z-laminated multilayered packaging substrate
US 20020119396 A1
Abstract
A method for forming a plurality of solder bumps comprising providing a pair of metallic supports. An initial solder layer is respectively disposed on each of the metallic supports which may be a metal-filled blind via. One or two additional solder layers are disposed on one of the initial solder layers. A multilayered packaging assembly includes the solder layer(s) on a plurality of substrates which are coupled together.
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Claims(35)
What is claimed is:
1. A method for forming a solder bump on a metal comprising:
providing a metallic support;
depositing a first solder layer on the metallic support; and
depositing a second solder layer on the first solder layer.
2. The method of claim 1 additionally comprising depositing a third solder layer on the second solder layer.
3. The method of claim 1 wherein said first solder layer comprises a first solder composition and said second layer comprises a second solder composition which is generally different than said first solder composition.
4. The method of claim 2 wherein said third solder layer comprises a third solder composition.
5. The method of claim 4 wherein said third solder composition is generally different than said second solder composition.
6. The method of claim 4 wherein said third solder composition is generally equal to said first solder composition.
7. The method of claim 3 wherein said first solder composition comprises a major proportion of tin and a minor proportion of lead, and said second solder composition comprises a major proportion of lead and a minor proportion of tin.
8. The method of claim 4 wherein said first solder composition comprises a major proportion of tin and a minor proportion of lead, said second solder composition comprises a major proportion of lead and a minor proportion of tin, and said third solder composition comprises a major proportion of tin and a minor proportion of lead.
9. The method of claim 8 wherein said metallic support comprises a metal-filled via in a laminated substrate.
10. The method of claim 9 wherein said metal-filled via comprises a blind via having a generally frusto-conical shape in vertical cross section.
11. A method for forming a plurality of solder bumps comprising providing a first metallic support; providing a second metallic support; depositing a first solder layer on the first metallic support; depositing a second solder layer on the first solder layer; and depositing a third solder layer on the second metallic support.
12. The method of claim 11 additionally comprising depositing a fourth solder layer on the second solder layer.
13. The method of claim 11 wherein said first solder layer comprises a first solder composition and said second solder layer comprises a second solder composition which is generally different than said first solder composition.
14. The method of claim 12 wherein said fourth solder layer comprises a fourth solder composition.
15. The method of claim 14 wherein said fourth solder composition is generally different than said second solder composition.
16. The method of claim 14 wherein said fourth solder composition is generally equal to said first solder composition.
17. The method of claim 13 wherein said first solder composition comprises a major proportion of tin and a minor proportion of lead, and said second solder composition comprises a major proportion of lead and a minor proportion of tin.
18. The method of claim 14 wherein said first solder composition comprises a major proportion of tin and a minor proportion of lead, said second solder composition comprises a major proportion of lead and a minor proportion of tin, and said fourth solder composition comprises a major proportion tin and a minor proportion of lead.
19. The method of claim 18 wherein said first metallic support comprises a first metal-filled via in a first laminated substrate.
20. The method of claim 19 wherein said first metal-filled via comprises a first blind via having a generally frusto-conical shape in vertical cross section.
21. The method of claim 13 wherein said third solder layer comprises a third solder composition which is generally different than said second solder composition.
22. The method of claim 21 wherein said first solder composition comprises a major proportion of tin and a minor proportion of lead, and said second solder composition comprises a major proportion of lead and a minor proportion of tin.
23. The method of claim 21 wherein said first solder composition comprises a major proportion of tin and a minor proportion of lead, said second solder composition comprises a major proportion of lead and a minor proportion of tin, and said third solder composition comprises a major proportion of tin and a minor proportion of lead.
24. The method of claim 21 wherein said first solder composition consists of tin having a first thickness, said second solder composition consists of gold having a second thickness greater than the first thickness, and said third solder composition consists of tin having a third thickness less than said second thickness.
25. The method of claim 19 wherein said second metallic support comprises a second metal-filled via in a second laminated substrate which is coupled to said first laminated substrate.
26. A method for forming a multilayered packaging assembly comprising:
forming a first metallic support on a first substrate;
forming a second metallic support on a second substrate;
depositing a first solder layer on the first metallic support;
depositing a second solder layer on the first solder layer; and
coupling the second solder layer to the second metallic support.
27. The method of claim 26 additionally comprising rotating the second substrate 180 degrees prior to said coupling.
28. The method of claim 26 additionally comprising heating the first solder layer to a temperature higher than its melting point temperature but below a melting point temperature of the second solder layer.
29. The method of claim 26 additionally depositing a third solder layer on said second solder layer.
30. The method of claim 29 additionally comprising heating the first substrate to a temperature higher than a melting temperature of the first and third solder layers but below a melting point temperature of the second solder layer.
31. A substrate assembly comprising a substrate having a metallic member; a first solder layer disposed on the metallic member; and a second solder layer disposed on the first solder layer.
32. A multilayered packaging assembly comprising a first substrate having a first metallic support; a first solder layer disposed on the first metallic support; a second solder layer disposed on the first solder layer; a third solder layer disposed on the second solder layer; and a second substrate having a second metallic support and coupled to the first substrate.
33. The method of claim 30 additionally comprising heating the first substrate to a temperature greater than the melting point temperature of the second solder layer.
34. The method of claim 33 additionally comprising a bonding sheet supported by said first substrate.
35. The method of claim 34 additionally comprising cooling the first substrate to a temperature which approximates a curing temperature of the bonding sheet.
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    This is a continuation-in-part patent application of copending patent application Ser. No. 09/429,854, filed Oct. 28, 1999. Benefit of the earlier filing date is claimed for all common subject matter.
  • [0002]
    1. Field of the Invention
  • [0003]
    The present invention is related to multilayered packaging substrate. More specifically, the present invention provides a structure and method for producing or forming multilayered packaging circuit structures.
  • [0004]
    2. Description of the Prior Art
  • [0005]
    Multilayer circuit structures can be used to electrically communicate two or more electrical devices such as two or more computer chips. Multilayer circuit structures typically contain multiple conductive layers separated by one or more dielectric layers. Via structures disposed in apertures in the dielectric layers provide conductive paths so that electrical signals can pass from one conductive layer to another conductive layer. Multiple via structures in successive dielectric layers can be used to form a conductive path from an inner region to an outer region of a multilayer circuit structure.
  • [0006]
    The via structures in successive dielectric layers can be staggered in a multilayer circuit structure. For example, as shown in FIG. 37, a plurality of staggered via structures 110 are in electrical communication with each other. The staggered conductive path formed by the via structures 110 can provide communication between a core structure 120 and an outer surface of the multilayer circuit structure 100. Each of the via structures 110 shown in FIG. 37 is in the form of a conductive coating on an aperture wall in a dielectric layer. Unfortunately, staggering the via structures can consume valuable area in a multilayer circuit structure and can increase the signal run length. This can decrease the density of the circuitry in a multilayer circuit structure. Moreover, the metal coating of via structures of the type shown in FIG. 37 is thin. Open circuits can form if the coating is not thick enough or is not uniform.
  • [0007]
    It would be desirable to provide a method for efficiently producing a reliable high-density multilayer circuit structure in a cost effective manner.
  • SUMMARY OF THE INVENTION
  • [0008]
    Embodiments of the invention are directed to methods for forming multilayer circuit structures, particularly high density multilayer circuit structures, having stacked via structures. The via structures are preferably stacked conductive posts.
  • [0009]
    One embodiment of the invention can be directed to a method for forming a multilayer circuit structure. The method comprises: forming a first plurality of conductive posts on first and second sides of a circuitized core structure, each conductive post having an end proximate to the core structure and an end distal to the core structure; depositing a first dielectric layer on the first side of the core structure; depositing a second dielectric layer on the second side of the core structure; removing dielectric layer material from the distal ends of the first plurality of conductive posts; and forming a second plurality of conductive posts on the distal ends of the first plurality of conductive posts.
  • [0010]
    Another embodiment is directed a method comprising: forming a first plurality of conductive posts on a side of a circuitized core structure, each conductive post having an end proximate to the core structure and an end distal to the core structure; laminating a dielectric layer on the core structure; depositing a protective layer on the dielectric layer; removing dielectric layer material from the distal ends of the first plurality of conductive posts through the protective layer; and forming a second plurality of conductive posts on the distal ends of the first plurality of conductive posts.
  • [0011]
    The present invention also provides a method for forming a solder bump on a metal comprising providing a metallic support; depositing a first solder layer on the metallic support; and depositing a second solder layer on the first solder layer. A third solder layer may be disposed on the second solder layer. The first solder layer comprises a first solder composition and the second layer comprises a second solder composition which is generally different than the first solder composition. The third solder layer comprises a third solder composition, which may be generally different than the second solder composition. In one preferred embodiment of the invention, the third solder composition is generally equal to the first solder composition. In another preferred embodiment of the invention the first solder composition and the third solder composition each comprise a major proportion of tin and a minor proportion of lead, and the second solder composition comprises a major proportion of lead and a minor proportion of tin. The metallic support may be a metal-filled via in a laminated substrate. Preferably, the metal-filled via comprises a blind via having a generally frusto-conical shape in vertical cross section. In another embodiment of the invention, a bonding sheet may be disposed on the substrate and the solder layers may be disposed in an opening in the bonding sheet.
  • [0012]
    The present invention further provides a method for forming a multilayered packaging assembly comprising forming a first metallic support on a first substrate; forming a second metallic support on a second substrate; depositing a first solder layer on the first metallic support; depositing a second solder layer on the first solder layer; and coupling the second solder layer to the second metallic support on the second substrate. The method additionally comprises rotating the second substrate 180 degrees prior to the coupling of the second solder layer to the second metallic support on the second substrate. The method further additionally comprises heating the first solder layer to a temperature higher than its melting point temperature but below a melting point temperature of the second solder layer. A third solder layer may be deposited on the second solder layer. In an alternative preferred embodiment of the invention, the method additionally comprises heating the first substrate to a temperature higher than a melting temperature of the first and third solder layers but below a melting point temperature of the second solder layer. A bonding sheet is preferably supported by the first substrate. An opening may be formed in the bonding sheet and one or more of the solder layers may be positioned in the opening. In another embodiment of the invention, the first substrate is subsequently heated to a temperature greater than the melting point temperature of the second solder layer, and the first substrate is then preferably cooled to a temperature which approximates a curing temperature of the bonding sheet.
  • [0013]
    The present invention also provides a substrate assembly and a multilayered packaging assembly. The substrate assembly comprises a substrate having a metallic member, a first solder layer disposed on the metallic member, and a second solder layer disposed on the first solder layer. The multilayered packaging assembly comprises a first substrate having a first metallic support, a first solder layer disposed on the first metallic support, a second solder layer disposed on the first solder layer, a third solder layer disposed on the second solder layer, and a second substrate having a second metallic support and coupled to the first substrate.
  • [0014]
    These provisions together with the various ancillary provisions and features which will become apparent to those skilled in the art as the following description proceeds, are attained by the methods and multilayered circuit structures of the present invention, preferred embodiments thereof being shown with reference to the accompanying drawings, by way of example only, wherein:
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0015]
    [0015]FIG. 1 is a side elevational view of conformal polymer layer(s) disposed on a substrate assembly and over conductor pads;
  • [0016]
    [0016]FIG. 2 is a side elevational view of the substrate assembly of FIG. 1 after deposition of gap-filling polymer;
  • [0017]
    [0017]FIG. 3 is a side elevational view of an alternative substrate assembly with impedance control and ground planes deposited over polymeric CVD layers;
  • [0018]
    [0018]FIG. 4 is a side elevational view of the substrate assembly of FIG. 3 after deposition of gap-filling polymer;
  • [0019]
    [0019]FIG. 5 is a side elevational view of a substrate assembly with conformal polymer layer(s) on a substrate assembly and over conductor(s) and previously deposited layers;
  • [0020]
    [0020]FIG. 6 is a side elevational view of the substrate assembly of FIG. 1 after deposition of an organic or inorganic gap-filling layer;
  • [0021]
    [0021]FIG. 7 is a side elevational view of the substrate assembly of FIG. 6 after depositing a planarizing layer(s) to provide a compliant sealant layer, to facilitate chemical mechanical polishing and further build-up;
  • [0022]
    [0022]FIG. 8 is a side elevational view of the substrate assembly of FIG. 7 after subsequent build-up;
  • [0023]
    [0023]FIG. 9 is a side elevational view of part of the substrate assembly of FIG. 5;
  • [0024]
    [0024]FIG. 10 is a side elevational view another part of the substrate assembly of FIG. 5;
  • [0025]
    [0025]FIG. 11 is a side elevational view of the substrate assembly of FIG. 1 after low dielectric constant thermoplastic particulates were deposited;
  • [0026]
    [0026]FIG. 12 is a side elevational view of the substrate assembly of FIG. 11 after thermal treatment;
  • [0027]
    [0027]FIG. 13 is a side elevational view of the substrate assembly of FIG. 12 after build-up with another substrate assembly;
  • [0028]
    [0028]FIG. 14 is a side elevational view of part of the substrate assembly of FIG. 5;
  • [0029]
    [0029]FIG. 15 is a side elevational view of another part of the substrate assembly of FIG. 5;
  • [0030]
    [0030]FIG. 16 is a side elevational view of the substrate assembly of FIG. 14 after depositing a composite of low dielectric constant polymer particulates within another planarizing low dielectric constant polymer;
  • [0031]
    [0031]FIG. 17 is a side elevational view of the substrate assembly of FIG. 16 after build-up with another substrate assembly;
  • [0032]
    [0032]FIG. 18 is a side elevational view of part of the substrate assembly of FIG. 5;
  • [0033]
    [0033]FIG. 19 is a side elevational view of another part of the substrate assembly of FIG. 5;
  • [0034]
    [0034]FIG. 20 is a side elevational view of the substrate assembly of FIG. 18 after disposing a thermoplastic low dielectric constant polymer film on top thereof;
  • [0035]
    [0035]FIG. 21 is a side elevational view of the substrate assembly of FIG. 20 after thermal treatment;
  • [0036]
    [0036]FIG. 22 is a side elevational view of the substrate assembly of FIG. 20 after disposing an optional planarizing layer and subsequent build-up of successive layers;
  • [0037]
    [0037]FIG. 23 is a side elevational view of an LSI substrate assembly separated from a substrate supporting metal pads;
  • [0038]
    [0038]FIG. 24 is a side elevational view of the LSI substrate assembly after being coupled to the pad-supporting substrate;
  • [0039]
    [0039]FIG. 25 is a partial enlarged sectional view of one embodiment of a post in FIG. 24 coupled to a metal pad;
  • [0040]
    [0040]FIG. 26 is a partial enlarged sectional view of another embodiment of a post in FIG. 24 coupled to a metal pad;
  • [0041]
    [0041]FIG. 27 is a side elevational view of another embodiment of the two assemblies of FIG. 23;
  • [0042]
    [0042]FIG. 28 is a side elevational view of the two assemblies of FIG. 27 coupled together;
  • [0043]
    [0043]FIG. 29 is a partial enlarged elevational view of one embodiment of a post in FIG. 28 coupled to a metal pad;
  • [0044]
    [0044]FIG. 30 is a side elevational view of another embodiment of the two assemblies of FIG. 23;
  • [0045]
    [0045]FIG. 31 is a side elevational view of the two assemblies of FIG. 30 coupled together;
  • [0046]
    [0046]FIG. 32 is an enlarged elevational view of two posts in FIG. 31 coupled together;
  • [0047]
    [0047]FIG. 33 is a side elevational view of another embodiment of the two assemblies of FIG. 23;
  • [0048]
    [0048]FIG. 34 is a side elevational view of the two assemblies of FIG. 33 coupled together;
  • [0049]
    [0049]FIG. 35 is an enlarged elevational view of a post in FIG. 34 coupled to a cup member;
  • [0050]
    [0050]FIG. 36 is a partial perspective view of a wire interconnect structure (e.g., a WIT) spaced from a cup member;
  • [0051]
    [0051]FIG. 37 shows a cross section of a multilayer circuit structure with staggered via structures;
  • [0052]
    FIGS. 38 to 51 show cross sections of multilayer circuit structure precursors used to form a multilayer circuit structure with stacked conductive posts;
  • [0053]
    [0053]FIG. 52 shows a cross section of a multilayer circuit structure with stacked conductive posts;
  • [0054]
    [0054]FIG. 53 shows a cross section of another embodiment of a multilayer circuit structure assembly;
  • [0055]
    FIGS. 54 to 57A illustrates the fabrication process for forming a substrate having a plurality of metal-filled vias with each via supporting an embodiment of the solder bump(s) of the present invention;
  • [0056]
    [0056]FIG. 57B is an enlarged sectional view of one embodiment of the solder bump;
  • [0057]
    [0057]FIG. 57C is an enlarged sectional view of another embodiment of the solder bump;
  • [0058]
    [0058]FIGS. 58A to 63A illustrate one embodiment of process flow steps for forming the multilayer circuit structure assembly of FIG. 53; and
  • [0059]
    [0059]FIGS. 58B to 65B illustrate another embodiment of process flow steps for forming the multilayer circuit structure assembly of FIG. 53.
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION
  • [0060]
    Referring in detail now to the drawings, there is seen in FIGS. 1-22 various embodiments of a structure and method for making a low dielectric constant MCM. Structures and methods of the type illustrated in FIGS. 1-22 are of priority of future generation MCM's as they will enable gigahertz speed products without huge losses, noise, and delays. The advantages of a low dielectric constant MCM of the various embodiments of the present invention are: (1) higher performance MCMs may be made with lower dielectric constants; (2) reduces amount of chemical mechanical polishing (CMP) required by using only conformal dielectric coatings in the MCMs; (3) enables better dielectric-layer adhesion than possible with only one type of dielectric polymer because of using two or more dielectric polymers; and (4) enables controlled impedance structures. A dielectric constant is a value serving as an index of the ability of the dielectric material(s) (e.g., polymers) to resist the transmission of an electrostatic force from one charged body to another. The dielectric materials utilized in various embodiments of the present invention for producing low dielectric constant MCMs have a low dielectric constant, such as a dielectric constant less than about 3.8 at 20 C. In a preferred embodiment of the invention, the dielectric constant at 20 C. for the dielectric materials ranges from about 1.2 to about 3.4; preferably from about 1.4 to about 3.0; more preferably from about 1.6 to about 2.8; most preferably from about 1.8 to about 2.7; such as from about 2.0 to about 2.6 including from about 2.1 to about 2.5.
  • [0061]
    Suitable dielectric material(s) include B-stage polymeric compounds, such as polyimides, epoxy resins, polyurethanes or silicons, provided that these compounds are produced with a low dielectric constant at 20 C. Additional suitable materials could include thermosetting materials, such as high glass transition anhydride-cured epoxy composition possessing a low dielectric constant at 20 C. More particular suitable thermoset materials include, but are not limited to, one or more compounds produced with a low dielectric constant at 20 C. and selected from group consisting of epoxies and modified epoxies, melamine-formaldehydes, urea formaldehydes, phelonic resins, poly(bis-maleimides), acetylene-terminated BPA resins, IPN polymers, triazine resins, and mixtures thereof Further additional suitable materials include high temperature thermoplastic materials, such as liquid crystal polyesters (e.g., Xydar™ or Vectra™), poly-(ether ether ketones), or the poly(aryl ether ketones), provided that these thermoplastic materials are produced such as to possess the low dielectric constant at 20 C. Additional suitable thermoplastic materials include, by way of example only, ABS-containing resinous materials (ABS/PC, ABS/polysulfone, ABS/PVC), acetals acrylics, alkyds, allylic ethers, benzocyclobutenes, cellulosic esters, chlorinated polyalkylene ethers, cyanate, cyanamides, furans, parylene amorphous fluoropolymers, polyalkylene ethers, polyamides (Nylons), polyarylene ethers, perfluoroalkoxy polymeric resins, fluoroethylenepropylene polymers, polybutadienes, polycarbonates, polyesters, polyfluorocarbons, polyimides, polyphenylenes, polyphenylene sulfides, polypropylenes, polystyrenes, polysulfones, polyurethanes, polyvinyl acetates, polyvinyl chlorides, polyvinyl chloride/vinylidine chlorides, polyetherimides, and the like, and mixtures of any of the foregoing, provided that the materials are manufactured to have a low dielectric constant at 20 C.
  • [0062]
    In another preferred embodiment of the invention the low dielectric constant material comprises a polymer having the repeat structure (—CH2C6H4CH2—)n wherein n is an integer having a value ranging from about 2,000 to about 8,000; more preferably from about 3,000 to about 7,000; most preferably from about 4,000 to about 6,000, such as from about 4,500 to about 5,500 including from about 4,800 to about 5,200. In a further embodiment of the invention the low dielectric constant material comprises the repeat structure (—CF2—CF2—)n wherein n is an integer having a value ranging from about 3,000 to about 16,000; more preferably from about 4,000 to about 14,000; most preferably from about 8,000 to about 12,000.
  • [0063]
    Referring now to FIGS. 1-3, a thin conformal coating of one low dielectric constant layer of material 16 is first deposited over the conductor traces 14 (i.e., Cu) supported by substrate 10. A conformal coating is a coating which has sufficient viscosity to generally conform to an underneath supporting surface as shown in FIG. 1. A conformal coating is also a coating which deposits in a generally uniform thickness as shown in FIG. 1. A conformal coating is furthermore a coating which does not have to be polished (e.g., such as by CMP) after deposition. Conductor traces 14 (or pads or regions) may be plated and/or sputtered onto substrate 10. This layer of material 16 provides good adhesion to the conductor traces 14, and may be deposited by any suitable manner, such as chemical vapor deposition (CVD), sprayed on, or spun on. Optionally, a second low dielectric constant layer of material 18, preferably a conformal layer of material 18, may subsequently be deposited on and/or over layer of material 16. The layer of material 18 may be manufactured from a material having less adhesion to the conductor traces 14 but good adhesion to the layer of material 16. Thus, by way of example only, the material 16 may comprise the repeat structure (—CH2C6H4CH2—)n where n ranges from about 4,500 to about 5,500; and material 18 may comprise a fluorinated parylene, such as, by way of example only, one having the repeat structure (—CHFC6H2F2CHF—)n wherein n is an integer having a value ranging from about 2,000 to about 8,000; more preferably from about 3,000 to about 7,000; and most preferably from about 4,000 to about 6,000. The low dielectric constant for material 16 may have a value which is less than, or more than, the value of the low dielectric constant for the material 18. More specifically, the dielectric constant for material 16 may be less than about 2.3 (or less than about 1.8) whereas the dielectric constant for material 18 may be greater than about 2.3 (or greater than about 1.8), i.e., a value ranging from greater than about 1.8, or from about 2.3 to about 3.8, and vice versa, i.e., dielectric constant for material 18 is less than about 2.3, or less than about 1.8, and the dielectric constant for material 16 is greater than about 1.8, or greater than about 2.3 up to and including about 3.8.
  • [0064]
    A gap-filling material 20 is subsequently deposited (e.g., spun on) in voids 24 between spaced material 16 (see FIG. 2A and FIG. 4). In FIGS. 1 and 2B, the gap-filling material 20 is disposed (e.g., spun on) in voids 26 between spaced material 18 which is supported by material 16. Any excess gap-filling material 20 extending about material 16 and/or material 18 may be polished or planarized down until a planar surface 20 a registers with planar surfaces 16 a-16 a of material 16 or with planar surfaces 20 a-20 a of material 20 (see FIG. 2A). The material 20 is one or more of the previously mentioned low dielectric constant materials. The low dielectric constant for material 20 may be the same as, less than, or greater than the dielectric constant for material 16 and/or material 18.
  • [0065]
    Fluorinated parylene AF4 has a dielectric constant of approximately 2.3 with a very low dissipation constant (approaching that of Teflon). Future AF4 variants will have even lower values of dielectric constant and dissipation factor. It has been surprisingly discovered that heat treatments in a specific temperature range result in highly desirable improvements in the mechanical properties of parylene AF4 films. Without this inventive heat treatment, the thermal expansion coefficient of films are in excess of 100 ppm. Following the heat treatment, the films exhibit thermal expansion coefficients of ˜35 ppm. Even more importantly, the total elongation to plastic instability of the films is changed >100% from undesirable values of 5-10% to much more desirable excess of 15-20%. Without a property enhancement such as this, it is very unlikely that multilayer electrical circuits could be manufacturable or made reliable.
  • [0066]
    Free standing parylene AF4 films of 50-100 micron thickness were deposited by the Gorham process at platen temperatures of both −15 C. and −25 C. The lower temperature deposition temperature is believed to result in higher molecular weights of the polymer film. From these films dogbone specimens with gauge widths of 4 mm and gauge lengths of 1 cm were cut using a YAG laser specimens were then pulled to failure in an Instron at strain rates of 10−1/sec. The lower molecular weight film became plastically unstable and fractured at essentially the same lower strain values of ˜6-9%. The higher molecular weight films became plastically unstable at essentially the same strains as the higher molecular weight film. The toughness of these films is unacceptable for multilayer film build-up (strains in excess of 10% prior to plastic instability are required). The films exhibit young's moduli of approximately 1 Gpa and sustain stress of roughly 50 Mpa to the point of plastic instability. The following vacuum (<1 mbar) heat treatments of the films as set forth in the following Table 1 were performed prior to cutting the tensile specimens:
    TABLE I
    Heat Treatment (HT) Time @ HT Elongation prior to
    Temperature ( C.) Temperature plastic instability
    As-Received <5-8%
    280 1 hr ˜10%
    300 1 hr ˜10%
    300 4 hr ˜10%
    330 Ramp and cool ˜20%
    330 1 hr ˜20%
    330 16 hr  ˜20%
    400 1 hr ˜20%
    450 1 hr ˜10%
  • [0067]
    In another embodiment of the invention and as best shown in FIG. 3, a ground layer 30 may be disposed over material 20; or alternatively, over material 18 which is used to fill the voids 24 instead of material 20. Subsequently, a second material 16 s is deposited as indicated with second conductor traces 14 s disposed as shown in FIG. 3. The ground layer 30 may serve to both control impedance and provide mechanical stability to the structure.
  • [0068]
    Referring now to FIGS. 4-8 for another embodiment of the invention, masking may be used on the layer of material 16 to remove or discontinue material 16 from one conductor trace 14 to a contiguous conductor trace 14, as best shown in FIG. 5. Subsequently, a low dielectric constant material 34, such as xerogel, sesquisilones, etc., is deposited over the material 16. The layer of material 34 may be thermally cured and may contain or develop voids and cracks, especially as deposited layers exceed about one micron in thickness. Subsequently chemical mechanical polishing (CMP) and structural stability are facilitated with a deposit of a low dielectric constant layer 36 (see FIG. 7), such as Teflon AF, parylene, PAE, BCB or low molecular weight reactive oligimers with low dielectric constants. CMP may then be performed and a next layer may be constructed. An additional or alternative layer (not shown in the drawings) of parylene, PAE, BCB or low molecular weight reactive oligimers with low dielectric constants may be deposited after CMP of the layer of material 34 to better enable a subsequent layer (not shown) of conductor to adhere. As was seen for the embodiment of the invention in FIG. 3, the conformal coating of material 36 may be thicker than the layer of material 34, and subsequently the conducting ground layer 30 may be deposited on material 36 as shown in FIG. 8. This ground layer 30 may serve to both control impedance and provide mechanical stability to the structure. These “sidewalls” of the impedance controlling ground layer 30 may alternatively be deposited to a thickness for which adjoining sidewalls bridge one another.
  • [0069]
    Referring now to FIGS. 9-22 for additional embodiments of the present invention, there is seen in FIG. 11 a plurality of low dielectric constant particulate material 40. The particulate material 40 may comprise or consist of material 16 and/or material 18 and/or material 34, or any of the previously mentioned low dielectric constant material(s). The particulate material 40 may be applied to the surface of material 16 and/or material 18 by any suitable manner, such as by spreading, spray, transfer, etc. The particulate material 40 is then thermally processed to flow material 40 and enable it to substantially fill the gaps to produce material 40 a (see FIG. 12). The temperature (e.g., a temperature ranging from about 85 C. to about 200 C.) to cause particulate material 40 to flow would depend on the composition of low dielectric constant material 40. Voids may be retained in this layer if desired. Material 36 may be disposed on material 40a, and ground layer 30 may be deposited on material 36, followed by disposing on ground layer 30 another assembly of traces 14, material 16 and material 40 a.
  • [0070]
    Referring now to FIGS. 14-17, a thin, essentially conformal coating of one low dielectric constant material 16 (i.e., parylene, PAE, BCB or low molecular weight reactive oligimers with low dielectric constants) is first deposited over the conductor traces 14 (i.e., Cu). The conductor traces 14 may be plated and/or sputtered onto substrate 10. Layer of material 16 possesses good adhesion for the conductor traces 14. Material 16, as previously indicated, is preferably deposited from the vapor phase, but may be spun or sprayed on. An optional separate or phased-in (gradient composition or co-deposited) thin conformal layer 18 with less adhesion to the conductor traces 14 but good adhesion to the first layer 16 (e.g., inorganic containing dielectrics, fluorinated parylene, fluorinated PAE, fluorinated BCB or low molecular weight reactive oligimers with low dielectric constants) may then be deposited, as shown in FIG. 2B. This layer 18 should also have good adhesion to successive additions and layers. Masking can be used to make such polymer layers discontinuous from conductor to conductor. Such layers may serve as a diffusion or electromigration barriers as well as an adhesion promoter.
  • [0071]
    Next, and as shown in FIG. 16, a composite layer of polymer 42 (e.g., Teflon AF, liquid crystal polymer, etc.) and/or inorganic containing dielectrics is deposited together within another planarizing low dielectric constant material (e.g., inorganic containing dielectrics, fluorinated BCB or low molecular weight reactive oligimers with low dielectric constants). Particulates 44 may be pressed into fluid or fluid spun on lightly compressed (and/or partially sintered) particulates. Also, they can be co-deposited by spray or spin-on processes. Alternatively, the particulates 44 may be precipitated out of solution (chemically or via solvent removal). The structure may alter its spatial geometry during curing as the thermoplastics may flow somewhat at elevated temperatures. Voids may be retained in this layer. Subsequent CMP and structural stability may be facilitated with a planarizing deposit of inorganic dielectric, BCB or low molecular weight reactive oligimers with low dielectric constants deposition on top of the thermoplastic. CMP may then be performed and a next layer can be constructed. An additional layer of inorganic containing dielectric, parylene, PAE, BCB or low molecular weight reactive oligimers with low dielectric constants may be deposited after CMP to better enable the next layer of conductor to adhere.
  • [0072]
    As best shown in FIG. 17, another conformal polymer layer 42 and conductor traces 14 may be formed for further circuit buildup. The optional ground layer 30 may be deposited prior to this second layer buildup for dimensional stability and/or electrical performance.
  • [0073]
    Referring now to FIGS. 18-22, after the low dielectric constant assembly is formed (see FIGS. 18-19), as the same low dielectric assembly of FIGS. 4-5, 9-10 and 14-15 was formed, a thermoplastic film 50 (e.g., Teflon AF, PFTE, PFA, FEP, liquid crystal polymer, etc.) with low dielectric constant is placed over the appropriately coated circuitry. The film 50 may be thermally laminated or autoclaved onto the circuitry, as best shown in FIG. 21. Subsequent CMP and structural stability may be facilitated with a planarizing deposit of inorganic dielectric, BCB or low molecular weight reactive oligimers with low dielectric constants deposition on top of the thermoplastic. As previously indicated, CMP may then be performed and a next layer may be formed. An additional layer of inorganic containing dielectric material 54, such as parylene, PAE, BCB or low molecular weight reactive oligimers with low dielectric constants may be deposited on film 50, followed preferably by CMP to better enable the next layer of conductor to adhere. FIG. 22 discloses a second layer build-up, similar to the second layer build-ups of FIGS. 8, 13, 17 and 22.
  • [0074]
    Referring now to FIGS. 23-36 for describing a method and structure which utilizes the “Wire Interconnect Structure” (WIT) and “Transient Liquid Alloy Bonding” (TLAB) on ultra-fine-pitch flip chip technology. WIT structure provides an ultra-fine-pitch interconnection method between LSI and a substrate. TLAB provides a reliable lead-free bonding method. The depletion layer of the TLAB can be located at the bottom pad (substrate side), on the wire structure, or at the middle of the wire structure.
  • [0075]
    As respectively illustrated in FIGS. 23-26, FIGS. 27-29, FIGS. 30-32, and FIGS. 33-36, embodiments of the invention include four types of structures. The first structure of FIGS. 23-26 illustrates the WIT on an LSI side and a depletion phase (Sn, In or Sn/In alloy) on a substrate side. The second structure of FIGS. 27-29 illustrates the depletion phase on the WIT structure, which may be done by sequential electroplating. The third structure of FIGS. 30-32 illustrates the depletion phase located at the middle of the final WIT structure, which is accomplished by electroplating of depletion phase on one side of WIT or both sides (i.e., half-WIT is built on both sides first). The fourth structure of FIGS. 33-36 illustrates a cup structure combined with the WIT structure. The cup structure provides an anchoring function to hold the WIT tip. It supports the structure with a good laterally mechanical strength and can transfer the shearing stain/stress directly to the WIT structure but not the joint interface. In the fourth structure, the Sn can be within the cup structure or on the tip of WIT. Also, the cup height can be low, which will be functioned to compensate the stress concentration directly, or be high to avoid the high stress point.
  • [0076]
    Referring more specifically now to FIGS. 23-36, there is seen a substrate 56 supporting a plurality of metal pads 58 (i.e., pads 58 a, 58 b, 58 c, 58 d and 58 e) which in turn support depletion layers 60 (i.e., depletion layers 60 a, 60 b, 60 c, 60 d and 60 e such as Sn and/or In deposited by electroplating). There is also seen an LSI substrate 62 supporting a plurality of conductive pads 64 (i.e., conductive pads 64 a, 64 b, 64 c, 64 d and 64 e), having connected thereto wire interconnect structures (WISs) 66 (i.e., WTIs 66 a, 66 b, 66 c, 66 d and 66 e) which may be fabricated by electroplating with a thick photoresist and preferably may be copper and/or gold. The advantage of gold is that it can provide better elasticity when employed at a high CTE mismatch circumstance. In FIGS. 27, 30 and 33, the depletion layers 60 a, 60 b, 60 c, 60 d and 60 e are respectively deposited on the terminal ends of the WTIs 66 a, 66 b, 66 c, 66 d and 66 e. In FIG. 30, WTIs 66 are divided such that part of the respective WTIs 66 is coupled to and supported by LSI substrate 62 and part is coupled to and supported by substrate 56. Furthermore with respect to the embodiment of the invention in FIG. 30, depletion layers 60 are divided between the two sets of WTIs 66-66 and disposed on terminal ends of the respective WTIs 66-66. In FIG. 33 substrate 56 supports a plurality of conductive cups 68 (i.e., cups 68 a, 68 b, 68 c, 68 d and 68 e) for receiving terminal ends of WTIs 66 including the respective depletion layers 60 associated with the terminal ends of WTIs 66. The conductive (e.g., copper) cups 68 are preferably fabricated by electroplating. A donut shape ring is exposed for depositing the conductive cups 68. The depletion layers 60 may be deposited on the terminal ends of the WITs 66 or inside the respective conductive cups 68 either by electroplating, immersion or evaporation.
  • [0077]
    The LSI substrate 62 and substrate 56 are aligned by a suitable aligner, e.g., a flip-chip bonder by Karl Suess. The aligned pair is subsequently pressed and heated by a flip-chip bonder in air or nitrogen environment. The temperature needs to be higher than the melting point of the depletion layers 60 and held for a certain period of time. The melting temperature is around 232 C. for Sn, 157 C. for In and between 120 C. to 232 C. for Sn-In temperature alloy(depending on the alloy composition). The time should be long enough to convert the molten phase of depletion layers 60 completely into an alloy or intermetallic compounds 60 a′, 60 b′, 60 c′, 60 d′ and 60 e′ with the base metal (e.g., copper or gold). More desirably, the depletion layers 60 are to be converted completely into a strong and reliable metal phase which depends on the metallurgical system used. Lastly, the underfill is applied between the interconnects to form a reliable chip packaging. Another alternative way to put in underfill material is during the bonding process by using a liquid-type underfill that can be cured during the bonding process.
  • [0078]
    Referring in detail now to FIGS. 37-52, embodiments of the invention are directed to methods for forming multilayer circuit structures. In preferred embodiments, the methods comprise forming a first plurality of conductive posts on first and second sides of a circuitized core structure. Each conductive post has an end proximate to the core structure and an end distal to the core structure. After the conductive posts are formed, a first dielectric layer is deposited on the first side of the core structure and a second dielectric layer is deposited on the second side of the core structure. Dielectric layer material deposited on the distal ends of the first plurality of conductive posts is then removed. After removing the dielectric layer material from the ends of the posts, circuit patterns are formed on the dielectric layers. The formed circuit patterns can include conductive pads disposed over the cleaned distal ends of the posts. A second plurality of conductive posts can then be formed on the conductive pads on the distal ends. The second plurality of conductive posts can be stacked on the first plurality of conductive posts. Additional sets of subsequently formed conductive posts (e.g., third, fourth pluralities) and pads can be stacked on the second plurality of conductive posts to form a plurality of generally vertical conductive pathways (e.g., generally perpendicular to the orientation of the core structure) through the dielectric layers. The generally vertical conductive pathways can result in a multilayer circuit structure which occupies less space than a similar multilayer circuit structure having staggered via structures.
  • [0079]
    In embodiments of the invention, multilayer circuit structures can be formed quickly and efficiently. For example, in preferred embodiments, the dielectric layers, conductive posts, and conductive patterns including conductive pads can be simultaneously formed or deposited on opposite sides of multilayer circuit structure precursors (e.g., a core structure). For example, in embodiments of the invention, conductive posts can be simultaneously electroplated on conductive regions on opposite sides of a core structure. Furthermore, in preferred embodiments, the multilayer circuit structures having stacked conductive posts can be formed using less expensive processes such as photolithography and electroplating. More expensive techniques such as laser drilling are not needed in preferred embodiments of the invention. Consequently, high density multilayer circuit structures having high circuit densities can be formed efficiently and cost-effectively.
  • [0080]
    The conductive posts and conductive patterns in the multilayer circuit structures are preferably formed by additive processes. Additive processes have advantages over subtractive processes. For example, subtractive processes use etchants to remove metal from continuous metal layers to form conductive patterns. The uniformity of the lines in the etched patterns can be difficult to control, because etchants can undercut the lines. Consequently, it can be difficult to form fine line patterns using subtractive processes. In an additive process, however, the conductive pattern resolution is limited only by the resolution of the photoresist used to form the conductive patterns. Consequently, fine line and high density circuit patterns can be produced using additive processes. For instance, the circuit lines can have widths of 25 microns or less, and can be at a pitch of about 50 microns or less. In addition, in subtractive processes, metal layers are etched and then rinsed. The etching and rinsing processes consume large amounts of wet chemicals and water and can generate large amounts of waste (e.g., wasted metal). However, because of the reduced number of etching steps used in a typical additive process, the waste generated from a typical additive process is less than a typical subtractive process.
  • [0081]
    Embodiments of the invention can be described with reference to the Figures. FIG. 38 shows a circuitized core structure 122 upon which a plurality of conductive posts are formed. The core structure 122 includes a first side 122(a) and a second side 122(b), and can be flexible or rigid. The first and second sides 122(a), 122(b) can have, respectively, a first plurality of conductive regions 124(a) and a second plurality of conductive regions 124(b). The first and second conductive regions 124(a), 124(b) can include, e.g., lines, pads, or the ends of via structures. Moreover, the first and second conductive regions 124(a), 124(b) can be made of any suitable conductive material including copper, and can have any suitable thickness including a thickness of less than about 50 microns, and preferably between about 18 to about 36 microns. In addition to having conductive regions 124(a), 124(b) on the outer surfaces of the core structure 122, the core structure 122 may also include two or more dielectric layers and one or more conductive layers (not shown) embedded within the core structure 122. The core structure 122 can also include one or more via structures 123. The via structures can communicate the conductive regions 124(a), 124(b) on the first and second sides 122(a), 122(b) of the core structure 122. The via structures can be solid conductive posts, or can be plated through holes (PTH) which have been filled with a conductive or a non-conductive material. For example, the PTH can be filled with a polymeric material such as an epoxy-based polymer, with or without an embedded conductive material. In another example, the PTH can be filled with a conductive paste such as a silver filled conductive paste. Filling the PTH with a material displaces any air which might otherwise reside in the PTH. It is preferable to remove any air pockets which might reside in the resulting multilayer circuit structure, because trapped air may cause reliability problems in some instances.
  • [0082]
    In a typical PTH filling process, an aperture can be formed in a rigid insulating board. Metal can be electroplated onto the wall of the aperture to form a PTH. After forming the PTH, a conductive or non-conductive filler material can be deposited within the PTH by, e.g., stenciling. If the filler material is curable, the filler material can be cured within the PTH. Before or after curing, any excess filler material on the first and second sides of the core structure can be removed.
  • [0083]
    In preferred embodiments, after the core structure is formed, a first plurality of conductive posts are formed on both the first and second sides of the circuitized core structure. Each conductive post can have an end proximate to the core structure and an end distal to the core structure. The conductive posts are preferably solid and/or substantially homogeneous in composition (e.g., all metal). The posts may also include any suitable conductive material. Suitable conductive materials include metal or metal alloys including copper, silver, gold, nickel, palladium, and aluminum. The conductive material is preferably copper.
  • [0084]
    The conductive posts may include any suitable dimensions. For example, the conductive posts can have a height of at least about 10 microns, preferably between about 15 to about 75 microns, and more preferably between about 25 to about 50 microns. The conductive posts can have any suitable diameter including a diameter between about 10 to about 150 microns, preferably between about 25 to about 75 microns. In addition, each of the posts may have a generally round radial cross-section.
  • [0085]
    The conductive posts (e.g., the first plurality of conductive posts) can be formed using any suitable process. For example, plating processes such as electroless or electroplating processes can be used to form the conductive posts.
  • [0086]
    The conductive posts are preferably formed by electroplating. With reference to FIG. 39, seed layers 125(a), 125(b) can be deposited on the first and second sides 122(a), 122(b) of the core structure 122. The seed layers 125(a), 125(b) can be used to help initiate the plating of the subsequently formed conductive posts. Preferably, the seed layers 125(a), 125(b) are deposited simultaneously, but they can be deposited sequentially in some instances. Any suitable process including sputtering and electroless plating can be used to deposit the seed layers. Electroless plating is preferred as it is generally less expensive than sputtering. Regardless of how they are deposited, the seed layers 125(a), 125(b) may have a thickness of about 3 microns or less. Preferably, the thickness of each seed layer is between about 0.1 to about 1.0 micron, and is more preferably between about 0.3 to about 0.6 micron.
  • [0087]
    Prior to depositing the seed layers, the first and second sides of the core structure may be conditioned. For example, to increase the adhesion of seed layers to the sides of the core structure, the surfaces of the core structure can be roughened. Roughening can be performed using any suitable process including an etch process such as a permanganate etch process. By roughening the surfaces of the core structure prior to depositing the seed layers, the seed layers are more likely to adhere to the surfaces of the core structure.
  • [0088]
    After depositing the seed layers, photoresist layers can be deposited on the seed layers. The photoresist layers can be in the form of a film or a liquid prior to being deposited on the first and second sides of the core structure. An example of a suitable dry film photoresist is Riston□ 9000, commercially available from E. I. du Pont de Nemours, Inc. An example of a suitable liquid photoresist is AZ4620 liquid photoresist commercially available from Clariant, Inc. The photoresist layers may be positive or negative, and can be deposited on the first and second sides of the core structure simultaneously or sequentially.
  • [0089]
    The photoresist layers may be deposited by any suitable process including roller coating, spin coating, curtain coating, screen printing, slot coating, spray coating, and doctor blade coating. These processes are suitable for depositing liquid photoresist layers. Preformed photoresist layers may be deposited by laminating. Preferably, the photoresist layers are deposited by laminating. For example, in some embodiments, a double-sided hot roll laminator may be used to laminate preformed layers of photoresist on both sides of the core structure simultaneously.
  • [0090]
    After depositing the photoresist layers, photoresist patterns can be formed using conventional photolithographic techniques. For example, the deposited photoresist layers can be irradiated with a pattern of radiation. The irradiated photoresist layers can then be developed to form patterned photoresist layers. For example, with reference to FIG. 40, after the photoresist layers on both sides of the core structure 122 are developed, the developed photoresist layers 131(a), 131(b) can have a plurality of apertures 132(a), 132(b) disposed over one or more conductive regions 124(a), 124(b) on opposite sides of the core structure 122. The patterned photoresist layers can be used as masks to selectively deposit conductive material in predetermined areas. Deposition processes such as electroplating or electroless plating can be used to deposit the conductive material on regions not covered by the patterned photoresist layers.
  • [0091]
    With reference to FIGS. 40 and 41, a first plurality of conductive posts 134(a), 134(b) are formed within the apertures 132(a), 132(b) of the photoresist layers 131(a), 131(b), and on the conductive regions 124(a), 124(b) exposed through the photoresist layers 131(a), 131(b). In this example, the first plurality of conductive posts includes conductive posts 134(a) on the first side of the core structure 122 and conductive posts 134(b) on the second side of the core structure 122. The first plurality of conductive posts 134(a), 134(b) are preferably formed on both sides of the core structure simultaneously. For example, the structure shown in FIG. 40 can be placed in an electroplating bath. In the electroplating bath, conductive material can plate from the conductive regions 124(a), 124(b) to the open ends of the apertures 132(a), 132(b) to form a first plurality of conductive posts 134(a), 134(b).
  • [0092]
    Although the use of seed layers are described in detail with respect to the illustrated embodiments, seed layers need not be used in other embodiments. For example, the conductive regions 124(a), 124(b) exposed through the photoresist layers 131(a), 131(b) may be suitable to initiate the direct plating of posts within the apertures 132(a), 132(b) of the photoresist layers 131(a), 131(b), without the need to deposit seed layers.
  • [0093]
    After the first plurality of conductive posts 134(a), 134(b) are formed, the photoresist layers 131(a), 131(b) which were used to form the conductive posts 134(a), 134(b) can be removed (e.g., stripped) from the core structure 122. As shown in FIG. 42, after the photoresist layers 131(a), 131(b) are removed, the first plurality of conductive posts 134(a), 134(b) are disposed on the core structure 122 and protrude from the surfaces of the core structure 122.
  • [0094]
    After the photoresist layers 131(a), 131(b) are removed, the seed layers 125(a), 125(b), if present, can also be removed. Preferably, the seed layers are etched in a-flash etching process. In a typical flash etching process, the seed layers can be etched for a short period of time. After flash etching, the seed layers are completely removed from the dielectric layer surfaces, and an insubstantial portion of the formed conductive posts 134(a), 134(b) may also be removed.
  • [0095]
    After the first plurality of conductive posts are formed on the core structure, dielectric layers may be deposited on the first and second sides of the core structure. The dielectric layers may include any suitable material including any suitable polymeric material. Exemplary dielectric layer materials include polyimide, epoxy-functional materials, and BT resins. Moreover, the dielectric layers may optionally include a filler. Preferable fillers can include particles such as silica or alumina particles, but may include chopped, woven, or nonwoven fibers. Preferably, the dielectric layers are in the form of a preformed layer. Examples of preformed dielectric layers include ABF-SH9 film commercially available from Ajinomoto, Inc., and BT346 film commercially available from Mitsubishi Gas and Chemical, Inc. In addition, the dielectric layers are preferably non-photoimageable. Non-photoimageable dielectric materials typically have a higher glass transition temperature (Tg) and a lower moisture absorption rate than photoimageable dielectric layers. Consequently, multilayer circuit structures having non-photoimageable dielectric layers are generally more reliable than photoimageable dielectric layers.
  • [0096]
    The deposited dielectric layers may have any suitable thickness including a thickness of about 75 microns or less, preferably between about 25 to about 50 microns. The individual dielectric layers on the core structure may have the same or different thickness. Preferably, an individual dielectric layer can have a thickness which is less than or equal to the combined height of a post and pad upon which the post is disposed. For example, the thickness of a dielectric layer may be about 2 to about 8% less (e.g., 5% or less) than the combined height of a conductive post and a conductive pad upon which the conductive post is disposed.
  • [0097]
    The dielectric layers may be sequentially or simultaneously deposited onto opposite sides of the core structure. For example, a first dielectric layer can be deposited on a first side of a core structure by depositing a liquid dielectric material on the first side. The deposited liquid can then be softbaked to solidify the deposited layer, and can then be optionally cured. After the first dielectric layer is deposited, a second dielectric layer can be deposited on the second side of the core structure in the same or different manner as the first dielectric layer.
  • [0098]
    The dielectric layers may be deposited using any suitable process including spin coating, screen printing, slot coating, doctor blade coating, curtain coating, etc. These processes can be used to deposit liquid dielectric layers. Laminating can be used to deposit preformed dielectric layers. The dielectric layers may even be deposited by a gas-phase deposition process such as a chemical vapor deposition (CVD).
  • [0099]
    Preferably, the first and second dielectric layers are respectively laminated to the first and second sides of the core structure. In these embodiments, the dielectric layers may be preformed prior to being deposited on the core structure. By depositing a preformed dielectric layer onto the core structure, the thickness of the dielectric layer is substantially uniform when present on the core structure. In addition, by laminating preformed dielectric layers onto a core structure, dielectric layers on opposite sides of the core structure can be deposited simultaneously, thus providing for more efficient processing.
  • [0100]
    Preferably, a preformed dielectric layer is disposed on a carrier layer prior to being laminated to the core structure. The carrier layer may include any suitable polymeric material including polyethylene terephthalate. The preformed dielectric layer and the carrier layer may form a composite. Suitable composites are commercially available from Ajinomoto, Inc. (e.g., ABF-SH9). With reference to FIG. 43, composites 140(a), 140(b) including a carrier layer 142(a), 142(b) and a dielectric layer 141(a), 141(b) are laminated to the first and second sides of the core structure 122. The composites 140(a), 140(b) are laminated to the core structure 122 so that the carrier layers 142(a), 142(b) are disposed on the outer surfaces of the dielectric layers 141(a), 141(b). The composites 140(a), 140(b) are preferably flexible and can be laminated to the core structure 122 simultaneously or sequentially.
  • [0101]
    The composites can be laminated to the core structure using any suitable apparatus. Heat and pressure can be applied to the dielectric layers to soften them so that they can conform to the surfaces to which they are laminated. The heating temperature and/or pressure can chosen in accordance with the particular material used for the dielectric layer. For example, a hot roll laminator can be used to laminate composites of this type onto opposing sides of the core structure simultaneously or sequentially. In some embodiments, the rolls of the hot roll laminator can be between about 60 C. to about 120 C. (preferably 80 C. to about 90 C.), and the rollers can run at a speed of about 1 to about 2 meters per minute. A vacuum laminator can also be used to laminate the dielectric layers or composites to the core structure. For example, using heat, the vacuum laminator can operate near vacuum (e.g., less than 1 atm) for a few minutes (e.g., 5 minutes or more). Alternatively, composites can be laid on opposite sides of a core structure, placed in a lamination press (e.g., a hydraulic press), and then laminated together. The lamination press can operate at a temperature of about 80 C. to about 90 C., and at a pressure of about 1 to about 3 kg/cm2 for a few minutes, (e.g., about 5 minutes or more). Regardless of the specific lamination apparatus used, after lamination, the dielectric layers may be disposed on opposite sides of the core structure and can be sandwiched between carrier layers.
  • [0102]
    After depositing the dielectric layers 141(a), 141(b), the dielectric layers 141(a) may be optionally cured. The dielectric layers can be cured in any suitable manner. For example, an electron-beam, heat, and/or U-V radiation can be used to cure the dielectric layers. The dielectric layers are cured in a lamination press, or preferably an oven, using heat.
  • [0103]
    Release layers may be optionally disposed on the uncured dielectric layers prior to and/or during curing (e.g., in a lamination press). The release layers preferably include a heat resistant material. Exemplary release layer materials include Teddler™ paper (commercially available from du Pont), fluoropolymeric materials such as polytetrafluoroethylene (Teflon™), or metal (e.g., aluminum, copper). If the release layer is a copper foil, a shiny side of the foil is preferably in contact with the dielectric layer. In these embodiments, the previously described carrier layer (if used) may be optionally replaced with a release layer which has a higher melting temperature than the carrier layer. For example, the carrier layer can have a melting temperature less than 150 C. while the release layer can have a melting temperature greater than about 150 C.
  • [0104]
    With reference to FIGS. 43 to 45, carrier layers 142(a), 142(b) can be separated (e.g., peeled) from the first and second dielectric layers 141(a), 141(b) after they are laminated to the core structure 122. Then, release layers 151(a), 151(b) can be deposited on the uncured first and second dielectric layers 141(a), 141(b). Preferably, the release layers 151(a), 151(b) are laminated to the first and second dielectric layers 141(a), 141(b). Heat, and optionally pressure, are applied to the structure to cure the dielectric layers 141(a), 141(b). For example, the first and second dielectric layers 141(a), 141(b) can be heated to a temperature of about 170 C. or more and can be subjected to a pressure of about 3.5 to about 20 kg/cm2 for about 60 minutes or more.
  • [0105]
    The heat and pressure may be applied with a lamination press. After curing, the release layers 151(a), 151(b) can then be separated (e.g., by peeling) from the cured dielectric layers 141(a), 141(b).
  • [0106]
    In preferred embodiments, (with reference to FIGS. 43 and 44) an uncured dielectric layer on the core structure may be cured without the use of a release layer. For example, after laminating a carrier layer/dielectric layer composite to a core structure, the carrier layer can be removed from the dielectric layer. Then, the dielectric layer on the core structure can be cured.
  • [0107]
    In other embodiments, the dielectric layers can be partially cured and then conditioned (e.g., roughened) prior to complete curing. For instance, a precursor structure including a core structure and dielectric layers may be placed in an oven and baked for about 150 C. or more for about 30 minutes or less to partially cure the dielectric layers. Then, the outer surfaces of the dielectric layers may be roughened. For example, an etch process such as a permanganate etch process can be used to roughen the surfaces of a dielectric layer. After roughening, circuit patterns can be formed on the dielectric layer. The circuit patterns can include conductive pads disposed on the distal ends of the first plurality of conductive posts. The dielectric layers may then be baked again to fully cure them. For example, to fully cure the dielectric layers, the dielectric layers can be additionally heated at about 170 C. or more for about 60 to about 90 minutes, or more. Then, a second plurality of conductive posts can be formed on the conductive pads. Advantageously, by roughening the outer surfaces of the dielectric layers, any subsequently deposited seed layers or conductive layers can tightly adhere to the surfaces of the dielectric layers.
  • [0108]
    After the dielectric layers 141(a), 141(b) are deposited on the core structure 122, dielectric layer material present on the distal ends of the first plurality of conductive posts 134(a), 134(b) can be removed to clean the post ends. In some embodiments, residual dielectric layer material can be present on the distal ends of the conductive posts after one or more dielectric layers are deposited on the core structure. For example, after laminating and curing, a dielectric layer on the conductive posts on the core structure, residual dielectric layer material can remain on the post ends. The residual dielectric material is typically 10 microns or less, and is often is about 2 to about 5 microns thick. After the post ends are cleaned, additional conductive posts can be subsequently formed on the first plurality of conductive pads and posts 134(a), 134(b). The formed conductive posts can be stacked and are electrically coupled together to form a generally vertical electrical pathway through one or more dielectric layers.
  • [0109]
    Any suitable process can be used to remove dielectric material from the distal ends of the conductive posts. Exemplary removal processes include etching processes such as a permanganate etch process, plasma etch process, or an abrading process such as mechanical polishing. In preferred embodiments, mechanical polishing can be used to remove the dielectric layer material. Mechanical polishing can be performed by using a polishing apparatus such as an oscillation deburrer. Oscillation deburrers are commercially available from Ishii Hyoki. The polishing apparatus can include buffing elements such as SiC and Al2O3 buffing wheels. In a typical operation, the revolution speed of the wheels can be about 2000 revolutions per minute (rpm) or more, and the oscillation cycle of the wheels is about 470 (cycles per minute) or more, and the oscillation stroke of the wheels is about 5 mm or more. The wheel pressure can be controlled automatically by preset pressure at a range of 0.25 to about 20 kg/cm2. In other embodiments, the dielectric material on the distal ends of the conductive posts may be ablated. For example, a laser can be used to ablate the dielectric layer material from the ends of the conductive posts.
  • [0110]
    Optionally, protective layers may be used during the dielectric material removal process to protect the dielectric layer regions not disposed on the conductive posts. With reference to FIG. 46, protective layers 161(a), 161(b) can be disposed on the dielectric layers 141(a), 141(b). The apertures 162(a), 162(b) of the protective layers 161(a), 161(b) can be disposed over the distal ends of the conductive posts 134(a), 134(b). Dielectric layer material on the distal ends of the conductive posts are exposed through the protective layer apertures. By using a protective layer during the dielectric material removal process, the deposited dielectric layers are protected in the regions not disposed on the ends of the posts. Consequently, in these embodiments, unwanted dielectric layer material can be selectively removed. For example, a wide area laser can scan the outer surface of a protective layer disposed on a dielectric layer. The laser can ablate dielectric layer material exposed through apertures in the protective layer. Regardless of the particular removal process used, after removing the dielectric material from the ends of the conductive posts, the protective layers can be removed from the dielectric layers. For instance, the protective layers may be removed by etching or peeling.
  • [0111]
    The protective layers may deposited onto or formed on the previously deposited dielectric layers in any suitable manner. For example, in one embodiment, a layer of photoresist can be deposited, irradiated, and developed on a deposited dielectric layer to form a protective layer. In another embodiment, a protective layer with apertures is preformed, and is then laminated to a dielectric layer so that the distal ends of the posts (and any dielectric layer material thereon) are accessible through the apertures. The apertured protective layer may be the same as, derived from, or different from the previously described release or carrier layers.
  • [0112]
    In another example, apertures in the protective layers 161(a), 161(b) can be formed when the dielectric layer material is removed from the distal ends of the conductive posts. For example, a continuous protective layer can be laminated to a dielectric layer on a core structure. The dielectric layer material on the distal ends of the conductive posts may be ablated along with portions of the protective layer disposed on the distal ends. In this case, additional cleaning of the distal ends of the posts may not be needed after ablation and the formed apertured protective layer can simply be removed from the dielectric layers. Any residual material from the ablation process can remain on the outer surface of the formed protective layers and can be removed along with the protective layers. For example, any ash generated by the ablation process can be removed along with the protective layers when the protective layers are peeled off of the dielectric layers.
  • [0113]
    After the dielectric layers are deposited, conductive patterns can be formed on the dielectric layers. This can be done before the second plurality of conductive posts are formed. The conductive patterns are preferably formed by an additive process such as electroplating. For example, with reference to FIGS. 47 and 48, after any carrier layers, release layers, or protective layers are removed (if used), seed layers 155(a), 155(b) may be deposited on the outer surfaces of the first and second dielectric layers 131(a), 131(b) and over the distal ends of the first plurality of conductive posts 134(a), 134(b). Prior to depositing the seed layers, the dielectric layer surfaces can be conditioned (e.g., roughened) in the same or different manner as described above for the core structure 122. Then, photoresist layers may be deposited over the seed layers 155(a), 155(b), irradiated, and then developed to form patterned photoresist layers 161(a), 161(b). The photoresist layers 161(a), 161(b) may have the same or different characteristics as the previously described photoresist layers 131(a), 131(b). As shown in FIG. 49, the patterned photoresist layers 161(a), 161(b) can be disposed on the seed layers 155(a), 155(b).
  • [0114]
    With reference to FIG. 50, conductive patterns 156(a), 156(b) are then formed (e.g., by electroplating) on the portions of the seed layers not covered by the developed photoresist layers 161(a), 161(b). The conductive patterns are preferably made of the same material as the conductive posts. The thickness of the formed conductive patterns 156(a), 156(b) can be between about 5 to about 35 microns, preferably between about 10 and about 20 microns. After the conductive patterns 156(a), 156(b) are formed, the photoresist layers 161(a), 161(b) can be removed (e.g., by stripping) from the surfaces of the dielectric layers 131(a), 131(b).
  • [0115]
    The conductive patterns may include a number of pads 139(a), 139(b) which are disposed on the distal ends of the first plurality of conductive posts. The pads generally have a larger surface area than the diameter of the conductive posts upon which they are disposed. Typically, a pad is disposed between respectively stacked conductive posts and is in direct contact with the stacked conductive posts.
  • [0116]
    Then, a second plurality and any subsequent plurality of conductive posts, dielectric layers, and conductive patterns can be formed on the structure shown in FIG. 51, or any subsequent multilayer circuit structure precursor, by repeating one or more of the previously described steps. For example, the process used to form the second plurality of conductive posts can be the same or different process used to form the first plurality of conductive posts. Preferably, the first, second, and any subsequent plurality of posts are formed by electroplating. Once the conductive patterns 156(a), 156(b) and conductive posts are formed, any seed layers 155(a), 155(b) can be etched (e.g., by flash etching).
  • [0117]
    Any number of conductive patterns, conductive posts, and dielectric layers can be included in the formed multilayer circuit structure. For example, the multilayer circuit structure 170 shown in FIG. 52 includes a circuitized core structure 122, and three dielectric layers and three conductive layers on each side of the core structure 122. The multilayer circuit structure 170 also includes generally vertical conductive pathways, each pathway including stacked conductive posts, with a pad between each adjacent pair of stacked posts. The generally vertical conductive pathways permit the size of the formed multilayer circuit structure to be reduced in comparison with a similar multilayer circuit structure with staggered via structures. Consequently, embodiments of the invention can be used to produce reliable, high density multilayer circuit structures efficiently and in a cost efficient manner.
  • [0118]
    After the multilayer circuit structure is formed, surface finishes or solder masks can be applied to the outer surfaces of the multilayer circuit structure. For example, a Ni/Au pad finish and/or a solder mask can be formed on the outer surfaces of a formed multilayer circuit structure. Accordingly, the multilayer circuit structures can be used in, for example, single chip modules, multichip modules and/or as mother or daughter boards in an electrical assembly.
  • [0119]
    Referring in detail now to FIGS. 53-65B, there is seen in FIG. 53 a multilayer laminated substrate, generally illustrated as 200. The multilayer laminated substrate 200 includes conventional laminated substrates 202, 204, 206 and 208 which are electrically coupled together by aligned metal-filled interconnected vias, each generally illustrated as 210. Any two contiguous laminated substrates are separated by a bonding sheet 212, such as bonding sheets 212 a, 212 b and 212 c.
  • [0120]
    Referring now to FIGS. 54-57, there is seen in FIG. 54 a conventional laminated substrate 202 (e.g., fiberglass reinforced laminate) having a copper layer 214 disposed on an underside thereof. Subsequently, blind vias 216 a, 216 b and 216 c are laser drilled down to copper layer 214 by any conventional means, such as by CO2, UV-Yag or eximer laser. The CO2 laser is preferred since it is easy to drill through a fiber glass reinforced laminate and the drilling speed is much faster than others. Subsequently, and as shown in FIG. 56, the blind vias 216 a, 216 b and 216 c are respectively filled with copper 218 a, 218 b and 218 c, by any conventional manner. Due to plating non-uniformity (typically 10%), slightly over plating is necessary to make sure that every blind via 216 a, 216 b and 216 c is filled up or above the top surface of laminated substrate 202. After plating, buff polishing of surface is applied to remove excess plating and flatten copper-filled blind vias by a deburr machine, such as Ishii Hyoki's oscillation deburrer. After the blind vias 216 a, 216 b and 216 c have been copper-filled, and preferably subsequently buffed, a solder bump 220 is deposited on each of the copper-filled blind vias 216 a, 216 b and 216 c.
  • [0121]
    In one embodiment of the invention and as best shown in FIG. 57B, one or more solder bumps 220 may comprise three (3) separate superimposed solder layers 220 a, 220 b and 220 c. In another embodiment of the invention and as best shown in FIG. 57C, one or more solder bumps 220 may comprise two (2) separate superimposed solder layers (e.g., solder layers 220 a and 220 b) on one substrate and a single solder layer (e.g., solder layer 220 c) on a second substrate. Thus, two superimposed solder layers may be disposed on one substrate (e.g., substrate 220 a), while a single layer may be disposed on another substrate (e.g., substrate 220 b).
  • [0122]
    The material for the solder layer(s) 220 comprises a conductive composition which may include pure metals, metal alloys, metal alloy precursors, metallic compositions, metallic compounds, and combinations thereof For example, the conductive composition can include one or more materials selected from the group consisting of In, Sn, Bi, Sb, Pb, Ni, Zn, Cu, Cd, Pt, Pd, Au and Ag.
  • [0123]
    Preferably, the conductive composition includes soft solder materials which can readily deform when pressed, thus providing for good areal contact between conducting surfaces. For instance, deforming the conductive compositions against conductive surface can increase the contact area with the support area. Suitable examples of solder compositions can include metals, or single or multi-phase alloys. The alloys may be binary, ternary, or other higher order compositions. Examples include alloys comprising In-Sn, Bi-Sn, In-Ag, Sn-Sb, Au-Sn, and Pb-Sn. More specific examples of solder material combinations include 52In/48Sn, 58Bi/42Sn, 97In/3Ag, In, 37Pb/63Sn, 96.5Sn/3.5Ag, 95Sn/5Sb, 80Au/20Sn, and 90Pb/10Sn (described in terms of weight percentages). More specifically and in a preferred embodiment of the invention, when the solder layer(s) 220 comprises three (3) superimposed layers (e.g., solder layers 220 a, 220 b and 220 c), the conductive composition comprises the following elements of Table II (numbers representing weight percentages):
    TABLE II
    Approach I Approach II
    Solder Layer 220a 2-5 um of eutectic solder: 2-5 um of Sn
    37 Pb/63 Sn or
    40 Pb/60 Sn
    Solder Layer 220b 10-20 um of high lead solder: 10-20 um of Ag
    90-97 Pb/3-10 Sn
    Solder Layer 220c 2-5 um of eutectic solder: 2-5 um of Sn
    37 Pb/63 Sn or
    40 Pb/60 Sn
  • [0124]
    In the embodiment of the invention illustrated in FIG. 57C, solder layers 220 a and 220 b may respectively include the conductive composition set forth in Table II above for solder layers 220 a and 220 b. If a single solder layer, such as solder layer 220 c, is to be employed on a separate first substrate (e.g., substrate 202) while another or second substrate (e.g., substrate 204) supports two (2) superimposed solder layers (such as solder layers 220 a and 220 b), the single solder layer (i.e., solder layer 220 c) may comprise the conductive composition set forth in Table II above for solder layer 220 c.
  • [0125]
    Referring now to FIGS. 58A-63A, photoresist 224 is disposed on at least one side, more preferably photoresist 224 is disposed on two opposing sides and is patterned over copper layer 214 which is subsequently etched. Either dry film or liquid photoresist may be used. Photoresist 224 is stripped, and then a dielectric polymer bonding film (e.g., bonding sheet 212 a), and a release layer 226 coupled or attached thereto, is secured or tacked in any conventional manner to the exposed top side of the laminated substrate 202, as best shown in FIG. 60A. Tacking may be accomplished by lamination. During the lamination, the bonding film or sheet (such as Ajinomoto bonding film) is heated to its maximum flow rate temperature (e.g., 80-90 C.) without curing it so that the solder bumps 220 can easily pierce or pass through it. Alternatively, a liquid polymer may be substituted for the bonding film. The liquid polymer may be coated on by screen printing, curtain coating or spray coating. The release layer 226 is then removed or stripped from the bonding film (i.e., bonding sheet 212 a in FIG. 61A).
  • [0126]
    A plurality of the formed substrate assembly of FIG. 61A may be produced with laminated substrates 202, 204, 206 and 208, then aligned as shown in FIG. 62A, and subsequently laminated together by any conventional means to make intermetallic joints and the multilayer laminated substrate 200 (see FIGS. 53 and 63A). More specifically, a plurality of the formed substrate assembly of FIG. 61A may be interconnected by lamination to make the intermetallic joint and to cure bonding film, such as bonding film 212a. First, the substrate, such as substrate 202, will be heated slightly higher than the solder layers (i.e., solder layers 220 a and 220 c) melting temperature (e.g., 185-230 C. for the eutectic solder of Approach I in Table II above and 235-250 C. for the Sn of Approach II in Table II above). It is well known that the melting temperature of lead (e.g., 300 C. to 325 C.) is higher than the melting temperature of tin (e.g., about 260 C.), and the melting temperature of gold (e.g., about 900 C.) is higher than that of lead. Thus, preferably the melting temperature for solder layers 220 a and 220 c is lower than the melting temperature for solder layer 220 b. The solder compositions(s) of the solder layers will melt and fuse together to make the intermetallic joint. At the same time, the solder layers 220 a and 220 c and solder layer 220 b will comingle and/or diffuse into each other and raise the melting temperature of the whole intermetallic joint. Finally, the joint will be “frizzed” at much higher temperature than the melting temperature of solder layers 220 a and 220 c (i.e., a “frizze” temperature of about 260-300 C. for Approach I in Table II and >300 C., such as 310-500 C., Approach II in Table II) and higher than the melting temperature of solder layer 220 b to further comingle and diffuse the solder layers into each other. Then, the temperature is reduced to the curing temperature (e.g., 95-140 C.) of the bonding film (e.g., bonding film 212 a) to cure the bonding film, such as bonding film 212 a. It should be readily apparent that the two opposed substrates 202 and 208 of the alignment of FIG. 62A are rotated 180 degrees to align copper 218 c in via 216 c of one substrate (e.g., substrate 208) with copper 218 a in via 216 a of a contiguous substrate (e.g. substrate 206).
  • [0127]
    Referring now to FIGS. 58B-65B, there is seen a sequential process by which an initially pair of substrates (e.g., substrates 202 and 204 in FIGS. 60B and 61B) are laminated together as previously indicated to produce the substrate assembly of FIG. 61B. Subsequently, the exposed copper layers 214-214 are patterned with photoresist 224-224. Bonding sheets 212 c and 212 b are then disposed on the patterned copper layers 214-214 in accordance with the previously indicated procedure. Substrates 206 and 208 with associated copper fillings (i.e., copper fillings 218 a, 218 b, and 218 c) and copper layers 214-214 are produced in accordance with the previously mentioned procedure, and subsequently coupled to the substrate assembly of FIG. 63B through lamination on the bonding sheets 212 b and 212 c, as previously indicated. The exposed copper layers 214-214 are then patterned with the assistance of photoresist 224-224. By performing the foregoing procedure the solder layers 220 will not be exposed to lithographic patterning process.
  • [0128]
    The embodiments of the invention of FIGS. 53-65B has many advantages over conventional plated through hole (PTH) vias. For example, embodiments of the present invention enable the production of much smaller (50-150 um vs. >200 um in diameter) vias so that the density is much higher. For L/D (laminated core+build-up deposited layer) package substrate application, the via of laminated core has to be filled before any deposited layer can be build up on top. Embodiments of the present invention has automatically filled vias so that no extra process steps are needed. For conventional plated through hole vias, the center hole of the plated vias have to be filled after via plating (forming). The typical filling material is a suitable liquid polymer (e.g., epoxy). Since the coefficient of thermal expansion (CTE) of typical polymer filler is much higher, it will generate reliability problem. For solving this problem, a copper capping layer is plated usually after via filling to “cap” the filler inside the via, but this way increases total thickness of copper before patterning so that the subtractive patterning resolution decreases. Embodiments of the present invention provide stack via structures to save the space. As previously mentioned embodiments of the present invention can make “frizzed” solder joints so that the solder joints can easily survive from further chip assembly processing, such as solder reflow to mount chips on a substrate.
  • [0129]
    While the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosure, and it will be appreciated that in some instances some features of the invention will be employed without a corresponding use of other features without departing from the scope and spirit of the invention as set forth. Therefore, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments and equivalents falling within the scope of the appended claims.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3791858 *Dec 13, 1971Feb 12, 1974IbmMethod of forming multi-layer circuit panels
US3821785 *Mar 27, 1972Jun 28, 1974Signetics CorpSemiconductor structure with bumps
US3976524 *Jun 17, 1974Aug 24, 1976Ibm CorporationPlanarization of integrated circuit surfaces through selective photoresist masking
US3986255 *Nov 29, 1974Oct 19, 1976Itek CorporationProcess for electrically interconnecting chips with substrates employing gold alloy bumps and magnetic materials therein
US4181755 *Nov 21, 1978Jan 1, 1980Rca CorporationThin film pattern generation by an inverse self-lifting technique
US4614021 *Mar 29, 1985Sep 30, 1986Motorola, Inc.Pillar via process
US4908940 *Dec 12, 1988Mar 20, 1990The Furukawa Electric Co., Ltd.Method of manufacturing two-layer printed circuit sheet
US4915983 *Jun 10, 1985Apr 10, 1990The Foxboro CompanyMultilayer circuit board fabrication process
US4921777 *Aug 1, 1988May 1, 1990Allied-Signal Inc.Method for manufacture of multilayer printed circuit boards
US4980034 *Apr 4, 1989Dec 25, 1990Massachusetts Institute Of TechnologyHigh-density, multi-level interconnects, flex circuits, and tape for TAB
US5063175 *Dec 16, 1988Nov 5, 1991North American Philips Corp., Signetics DivisionMethod for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
US5071518 *Oct 24, 1989Dec 10, 1991Microelectronics And Computer Technology CorporationMethod of making an electrical multilayer interconnect
US5091289 *Apr 30, 1990Feb 25, 1992International Business Machines CorporationProcess for forming multi-level coplanar conductor/insulator films employing photosensitive polyimide polymer compositions
US5097393 *Jul 8, 1991Mar 17, 1992Rogers CorporationMultilayer interconnect device and method of manufacture thereof
US5106461 *Dec 21, 1990Apr 21, 1992Massachusetts Institute Of TechnologyHigh-density, multi-level interconnects, flex circuits, and tape for tab
US5118385 *May 28, 1991Jun 2, 1992Microelectronics And Computer Technology CorporationMultilayer electrical interconnect fabrication with few process steps
US5130779 *Jun 19, 1990Jul 14, 1992International Business Machines CorporationSolder mass having conductive encapsulating arrangement
US5137597 *Apr 11, 1991Aug 11, 1992Microelectronics And Computer Technology CorporationFabrication of metal pillars in an electronic component using polishing
US5162260 *Jan 7, 1991Nov 10, 1992Hewlett-Packard CompanyStacked solid via formation in integrated circuit systems
US5234149 *Aug 28, 1992Aug 10, 1993At&T Bell LaboratoriesDebondable metallic bonding method
US5278184 *Apr 17, 1992Jan 11, 1994Repla Chemical Ltd.Synthetic derivatives of pyrrole and pyrrolidine suitable for the therapy of infections caused by rhinoviruses
US5283081 *Mar 10, 1992Feb 1, 1994Nec CorporationProcess for manufacturing a ceramic wiring substrate having a low dielectric constant
US5287619 *Mar 9, 1992Feb 22, 1994Rogers CorporationMethod of manufacture multichip module substrate
US5316974 *Apr 30, 1990May 31, 1994Texas Instruments IncorporatedIntegrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
US5337466 *Jan 6, 1993Aug 16, 1994Nec CorporationMethod of making a multilayer printed wiring board
US5372295 *Oct 1, 1992Dec 13, 1994Ryoden Semiconductor System Engineering CorporationSolder material, junctioning method, junction material, and semiconductor device
US5464653 *Dec 18, 1990Nov 7, 1995Bull S.A.Method for interconnection of metal layers of the multilayer network of an electronic board, and the resultant board
US5470787 *May 2, 1994Nov 28, 1995Motorola, Inc.Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same
US5488200 *Jun 8, 1994Jan 30, 1996International Business Machines CorporationInterconnect structure with replaced semiconductor chips
US5512514 *Nov 8, 1994Apr 30, 1996Spider Systems, Inc.Self-aligned via and contact interconnect manufacturing method
US5542601 *Feb 24, 1995Aug 6, 1996International Business Machines CorporationRework process for semiconductor chips mounted in a flip chip configuration on an organic substrate
US5641113 *Jun 2, 1995Jun 24, 1997Oki Electronic Industry Co., Ltd.Method for fabricating an electronic device having solder joints
US5641990 *Aug 7, 1995Jun 24, 1997Intel CorporationLaminated solder column
US5654237 *Jun 7, 1995Aug 5, 1997Kabushiki Kaisha ToshibaMethod of manufacturing semiconductor device
US5699613 *Sep 25, 1995Dec 23, 1997International Business Machines CorporationFine dimension stacked vias for a multiple layer circuit board structure
US5784782 *Sep 6, 1996Jul 28, 1998International Business Machines CorporationMethod for fabricating printed circuit boards with cavities
US5830533 *Dec 4, 1992Nov 3, 1998Microelectronics And Computer Technology CorporationSelective patterning of metallization on a dielectric substrate
US5834845 *Sep 21, 1995Nov 10, 1998Advanced Micro Devices, Inc.Interconnect scheme for integrated circuits
US5843839 *Apr 29, 1996Dec 1, 1998Chartered Semiconductor Manufacturing, Ltd.Formation of a metal via using a raised metal plug structure
US5891606 *Oct 7, 1996Apr 6, 1999Motorola, Inc.Method for forming a high-density circuit structure with interlayer electrical connections method for forming
US5891799 *Aug 18, 1997Apr 6, 1999Industrial Technology Research InstituteMethod for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates
US5897336 *May 28, 1997Apr 27, 1999International Business Machines CorporationDirect chip attach for low alpha emission interconnect system
US5916453 *Sep 20, 1996Jun 29, 1999Fujitsu LimitedMethods of planarizing structures on wafers and substrates by polishing
US6013417 *Apr 2, 1998Jan 11, 2000International Business Machines CorporationProcess for fabricating circuitry on substrates having plated through-holes
US6070321 *Jul 9, 1997Jun 6, 2000International Business Machines CorporationSolder disc connection
US6168972 *Dec 22, 1998Jan 2, 2001Fujitsu LimitedFlip chip pre-assembly underfill process
US6181569 *Jun 7, 1999Jan 30, 2001Kishore K. ChakravortyLow cost chip size package and method of fabricating the same
US6225206 *May 10, 1999May 1, 2001International Business Machines CorporationFlip chip C4 extension structure and process
US6278184 *Sep 22, 1999Aug 21, 2001International Business Machines CorporationSolder disc connection
US6455785 *Oct 5, 1999Sep 24, 2002International Business Machines CorporationBump connection with stacked metal balls
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6955948 *Oct 15, 2002Oct 18, 2005Matsushita Electric Industrial Co., Ltd.Method of manufacturing a component built-in module
US6969667 *Apr 1, 2002Nov 29, 2005Hewlett-Packard Development Company, L.P.Electrical device and method of making
US6975516Oct 15, 2002Dec 13, 2005Matsushita Electric Industrial Co., Ltd.Component built-in module and method for producing the same
US7294587May 10, 2005Nov 13, 2007Matsushita Electric Industrial Co., Ltd.Component built-in module and method for producing the same
US7351657 *Jun 10, 2005Apr 1, 2008Honeywell International Inc.Method and apparatus for applying external coating to grid array packages for increased reliability and performance
US7645633Feb 7, 2008Jan 12, 2010Honeywell International Inc.Method and apparatus for applying external coating to grid array packages for increased reliability and performance
US9532447 *Jun 30, 2015Dec 27, 2016Murata Manufacturing Co., Ltd.Multi-layer resin substrate and method of manufacturing multi-layer resin substrate
US20030062624 *Oct 15, 2002Apr 3, 2003Matsushita Electric Industrial Co., Ltd.Component built-in module and method of manufacturing the same
US20030090883 *Oct 15, 2002May 15, 2003Matsushita Electric Industrial Co., Ltd.Component built-in module and method for producing the same
US20030127725 *Dec 10, 2002Jul 10, 2003Matsushita Electric Industrial Co., Ltd.Metal wiring board, semiconductor device, and method for manufacturing the same
US20050269681 *May 10, 2005Dec 8, 2005Matsushita Electric Industrial Co., Ltd.Component built-in module and method for producing the same
US20060160373 *Jan 13, 2006Jul 20, 2006Cabot CorporationProcesses for planarizing substrates and encapsulating printable electronic features
US20060278971 *Jun 10, 2005Dec 14, 2006Honeywell International Inc.Method and apparatus for applying external coating to grid array packages for increased reliability and performance
US20080132004 *Feb 7, 2008Jun 5, 2008Honeywell International Inc.Method and apparatus for applying external coating to grid array packages for increased reliability and performance
US20140206185 *Dec 21, 2011Jul 24, 2014Ming LeiBall placement in a photo-patterned template for fine pitch interconnect
US20150305150 *Jun 30, 2015Oct 22, 2015Murata Manufacturing Co., Ltd.Multi-layer resin substrate and method of manufacturing multi-layer resin substrate