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Publication numberUS20020123195 A1
Publication typeApplication
Application numberUS 10/006,778
Publication dateSep 5, 2002
Filing dateNov 5, 2001
Priority dateNov 6, 1995
Also published asUS6228719
Publication number006778, 10006778, US 2002/0123195 A1, US 2002/123195 A1, US 20020123195 A1, US 20020123195A1, US 2002123195 A1, US 2002123195A1, US-A1-20020123195, US-A1-2002123195, US2002/0123195A1, US2002/123195A1, US20020123195 A1, US20020123195A1, US2002123195 A1, US2002123195A1
InventorsFerruccio Frisina, Giuseppe Ferla, Salvatore Rinaudo
Original AssigneeStmicroelectronics S.R.I
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
MOS technology power device with low output resistance and low capacity, and related manufacturing process
US 20020123195 A1
Abstract
A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.
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Claims(19)
What is claimed is:
1. A process for the manufacturing of a MOS-gated power device, comprising the steps of:
a) forming a heavily doped semiconductor substrate;
b) forming a semiconductor layer of a first conductivity type and with a first resistivity value;
c) selectively introducing into the semiconductor layer a dopant suitable for forming first regions of the first conductivity type and with a second resistivity value, intercalated by second regions of the first conductivity type with the first resistivity value;
d) forming on the semiconductor layer a conductive insulated gate layer;
e) selectively removing the conductive insulated gate layer to open windows over selected portions of a surface of the semiconductor layer, said selected portions of the surface being located over those among the first regions and the second regions which have a higher resistivity value;
f) forming at said selected portions of the surface of the semiconductor layer body regions of a second conductivity type;
g) forming in the body regions source regions of the first conductivity type.
2. The process according to claim 1, wherein said dopant is of the first conductivity type, and it is introduced into the semiconductor layer in a dose suitable to make the second resistivity value lower than said first resistivity value, the windows in the insulated gate layer being located over said second region.
3. The process of claim 1, providing for:
a) forming the heavily doped semiconductor substrate;
b) forming a lightly doped semiconductor layer of a first conductivity type and with a first resistivity value;
c) selectively introducing into the lightly doped semiconductor layer a dopant suitable for forming first regions of the first conductivity type and with a second resistivity value, intercalated by second regions of the first conductivity type with the first resistivity value;
d) forming on the lightly doped semiconductor layer a top lightly doped semiconductor layer of the first conductivity type and having substantially the first resistivity value;
e) forming on the top lightly doped layer a conductive insulated gate layer;
f) selectively removing the conductive insulated gate layer to open windows over selected portions of a surface of the semiconductor layer, said selected portions of the surface being located over those among the first regions and the second regions which have a higher resistivity value;
g) forming at said selected portions of the surface of the top lightly doped semiconductor layer body regions of a second conductivity type;
h) forming in the body regions source regions of the first conductivity type.
4. The process according to claim 3, wherein said dopant is of the first conductivity type, and it is introduced into the lightly doped semiconductor layer in a dose suitable to compensate, but not to invert, a concentration of dopant of the first conductivity type of the lightly doped semiconductor layer, so that said second resistivity value is higher than said first resistivity value, the windows in the insulated gate layer being located over said first regions.
5. The process of claim 4, wherein said lightly doped semiconductor layer has a concentration of dopant of approximately 5-9*1014 atoms/cm3, corresponding to a resistivity of 5-10 ohms/cm.
6. The process of claim 5, wherein said top lightly doped semiconductor layer has a concentration of dopant of approximately equal to that of the lightly doped semiconductor layer.
7. The process of claim 6, wherein said dopant is introduced by ion implantation, in a dose of approximately 1*1012 to 1*1013 atoms/cm2 and with an energy higher than 100 KeV.
8. The process of claim 3, wherein said dopant is of the first conductivity type, and it is introduced into the lightly doped semiconductor layer in a dose suitable to make the second resistivity value lower than the first resistivity value, the windows in the insulated gate layer being located over said second regions.
9. The process of claim 8, wherein said lightly doped semiconductor layer has a dopant concentration of approximately 3-5*1013 atoms/cm3, corresponding to a resistivity of 80-150 ohms/cm.
10. The process of claim 9, wherein said top lightly doped semiconductor layer has a dopant concentration of approximately 3-5*1013 atoms/cm3, corresponding to a resistivity of 80-150 ohms/cm.
11. The process of claim 10, wherein said dopant is introduced by ion implantation, in a dose of 1*1012 to 1*1013 atoms/cm2 and with an energy higher than 200 KeV.
12. The process of claim 3, further providing for repeating steps b) and c) at least one time, for forming over the lightly doped semiconductor layer of the first conductivity type and with the first resistivity value at least one intermediate lightly doped layer of the first resistivity type and with the first resistivity value, and for selectively introducing into the at least one intermediate lightly doped semiconductor layer a dopant suitable for forming third regions of the first conductivity type and with the second resistivity value, intercalated by fourth regions of the first conductivity type with the first resistivity value, said third regions and fourth regions being disposed over the first regions and the second regions, respectively.
13. The process of claim 12, wherein the lightly doped semiconductor layer, the intermediate lightly doped semiconductor layer and the top lightly doped semiconductor layer have approximately similar thickness.
14. The process of claim 13, wherein the lightly doped semiconductor layer, the intermediate lightly doped semiconductor layer and the top lightly doped semiconductor layer have similar dopant concentrations of approximately 5-9*1014 atoms/cm3, corresponding to a resistivity of 5-10 ohms/cm.
15. The process of claim 14, wherein said dopant is of the second conductivity type, and it is introduced into the lightly doped semiconductor layer and the intermediate lightly doped semiconductor layer in a dose suitable to compensate, but not to invert, a concentration of dopant of the first conductivity type of the lightly doped semiconductor layer and the intermediate lightly doped semiconductor layer, so that said second resistivity value is higher than said first resistivity value, the windows in the insulated gate layer being located over said first regions.
16. The process of claim 15, wherein said dopant is introduced into the lightly doped semiconductor layer and into the intermediate lightly doped semiconductor layer by ion implantation, in a dose of approximately 1*1012 to 1*1013 atoms/cm2 and with an energy higher than 200 KeV.
17. The process of claim 13 wherein the lightly doped semiconductor layer, the intermediate lightly doped semiconductor layer and the top lightly doped semiconductor layer have similar dopant concentrations of approximately 3-5*1013 atoms/cm3, corresponding to a resistivity of 80-150 ohms/cm.
18. The process of claim 17, wherein said dopant is of the first conductivity type, and it is introduced into the lightly doped semiconductor layer and into the intermediate lightly doped semiconductor layer in a dose suitable to make the second resistivity value lower than the first resistivity value, the windows in the insulated gate layer being located over said second regions.
19. The process of claim 18, wherein said dopant is introduced into the lightly doped semiconductor layer and into the intermediate semiconductor layer in a dose of approximately 1*1012 to 1*1013 atoms/cm2 and with an energy higher than 200.
Description
CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation-in-part of application Ser. No. 08/740,713 filed on Nov. 4, 1996, entitled MOS TECHNOLOGY POWER DEVICE WITH LOW OUTPUT RESISTANCE AND LOW CAPACITANCE, AND RELATED MANUFACTURING PROCESS, which prior application is incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a MOS-gated power device with low output resistance and low capacitance, and to a related manufacturing process. MOS-gated power devices include, for example, power MOSFETS, IGBTs, MOS-gated thyristors or other MOS-gated power devices.

[0004] 2. Discussion of the Related Art

[0005] A primary goal of the designers of MOS-gated power devices is to reduce, as far as possible, the output resistance (or “on” resistance) and the various capacitances associated with the power device structure.

[0006] These parameters can be reduced by increasing the integration density of the elementary functional units (polygonal cells or stripes), which constitute a MOS-gated power device, by exploiting photolitographic techniques and manufacturing processes more and more similar to those used in Very Large Scale of Integration (VLSI) technologies.

[0007] However, the physical structure of the MOS-gated power devices limits the degree to which the integration density can be increased. These limits can be better understood considering the distinct components of the on resistance of a MOS-gated power device, which are: the channel resistance Rc, which is the component associated with the channel region of the MOS-gated power device; the accumulation region resistance Racc, which is the component associated with the surface region of those portions of the common drain layer (i.e. the lightly doped epitaxial layer wherein the elementary functional units are formed) disposed between the body regions of the elementary functional units; the JFET resistance Fjfet, which is the component associated with those portions of the common drain layer disposed between the depletion regions of the body regions of the elementary functional units; and the epitaxial layer resistance Repi, which is the component associated with those portions of the common drain layer beneath the body regions of the elementary functional units.

[0008] The channel resistance Rc and the accumulation region resistance Racc (both associated with regions near the surface of the common drain layer) can be reduced by scaling down the dimensions of the elementary functional units and by employing photolithographic machines with better optical resolution. Differently, the JFET resistance Rjfet and the epitaxial layer resistance Repi can be reduced only modifying the physical structure of the MOS-gated power devices. In fact, reducing the distance between the elementary functional units (cells or stripes), causes the Fjfet component to significantly increase, the increase being more pronounced the higher the resistivity of the common drain layer.

[0009] This means that in order to prevent the on resistance from significantly increasing, the minimum distance to which the elementary functional units of the MOS-gated power device must be kept increases with the increase of the resistivity of the common drain layer. By way of example, in devices designed to operated in a voltage range of approximately 60 V, the distance between the elementary functional units can be between 4 μm and 10 μm, while in the case of devices designed to operate in higher voltages of about 500 V, wherein the common drain layer is resistive, the distance between 15 μm and 20 μm.

[0010] Therefore, if in the attempt to increase the integration density it is desired to reduce the distance between the elementary functional units (cells or stripes), so that the gate-drain (or feedback) capacitance can be reduced, without however increasing the output resistance of the MOS-gated power device, it is necessary to increase the doping concentration of the common drain layer. This however reduces the breakdown voltage of the MOS-gated power device.

[0011] One known technique to overcome this drawback is described in the U.S. Pat. No. 4,376,286: the doping concentration in the portions of the common drain layer between the elementary functional units is increased by means of an implant of N type dopants, without affecting the doping concentration of the common drain layer beneath the body regions of the elementary functional units. In this way, it is possible to reduce the distance between the elementary functional units (and consequently reducing the feedback capacitance of the MOS-gated power device), without increasing the Fjfet component of the on resistance.

[0012] One of the limitations of this technique is that only the JFET component of the on resistance can be reduced, but not the epitaxial layer resistance Repi. Furthermore, an additional mask may be required in the manufacturing process, to prevent the N type dopants from being implanted at the edge of the power MOS device chip.

[0013] In view of the state of the art described, it is an object of the present invention to provide a MOS-gated power device with a low output resistance and low capacitance, without negatively affecting the breakdown voltage.

SUMMARY OF THE INVENTION

[0014] According to the present invention, this and other objects are achieved in a MOS-gated power device comprising a plurality of elementary functional units, each elementary functional unit comprising a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value, wherein a respective lightly doped region of a second conductivity type is respectively disposed under each body region, each respective lightly doped region having a second resistivity value higher than said first resistivity value.

[0015] As a result of the present invention, and specifically due to the presence of the lightly doped regions under the body regions of the elementary functional units, a MOS-gated power device is provided which, for a given breakdown voltage, has a common drain layer with a lower resistivity than that which would be necessary in a conventional MOS-gated power device with the same breakdown voltage. The reduced resistivity of the common drain layer not only provides a decrease of the JFET component Rjfet, but also of the epitaxial layer component Repi of the output resistance of the MOS-gated power device. Furthermore, it is possible to reduce the distance between the elementary functional units without increasing the JFET component, thus reducing the gate-drain capacitance of the MOS-gated power device.

[0016] The structure according to the present invention is particularly suitable for MOS-gated power devices of low voltages (30-200V), in which the dimension of the elementary functional units is comparable with the residual thickness of the epitaxial layer under the body regions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] These and other features of the present invention will be made more evident by the following detailed description of one particular embodiment, illustrated as a non limiting example in the annexed drawings, wherein:

[0018]FIG. 1 is a cross-sectional view of a MOS-gated power device according to the present invention;

[0019] FIGS. 2 to 5 are cross-sectional views similar to FIG. 1 showing intermediate steps of a manufacturing process according to one embodiment of the present invention;

[0020]FIG. 5A is a cross-sectional view similar to FIG. 5, illustrating another embodiment of the manufacturing process;

[0021]FIG. 6 is a comparative diagram showing doping profiles in the case of a conventional MOS-gated power device and in the case of the present invention;

[0022]FIG. 7 is another comparative diagram showing doping profiles in the regions between elementary functional units of the MOS-gated power device;

[0023]FIG. 8 is a comparative diagram showing the electric field distribution in the case of a conventional MOS-gated power device and in the case of the present invention;

[0024] FIGS. 9 to 11 are cross-sectional views similar to that of FIG. 1 of another embodiment of a manufacturing process according to the invention;

[0025] FIGS. 12 to 17 are cross-sectional views similar to that of FIG. 1 of another embodiment of a manufacturing process according to the invention, particularly suitable for the manufacturing of high-voltage MOS-gated power devices;

[0026]FIG. 18 shows in cross-section the high-voltage MOS-gated power device obtained by the process of FIGS. 12 to 17;

[0027] FIGS. 19 to 24 are cross-sectional views similar to that of FIG. 1 of yet another embodiment of a manufacturing process according to the invention, particularly suitable for the manufacturing of high-voltage MOS-gated power devices; and

[0028]FIG. 25 shows in cross-section the high-voltage MOS-gated power device obtained by the process of FIGS. 19 to 24.

DETAILED DESCRIPTION

[0029] With reference to the drawings, and specifically to FIG. 1, a MOS-gated power device chip according to the present invention comprises a heavily doped semiconductor substrate 1, over which a lightly doped semiconductor layer 2 is formed, for example by means of an epitaxial growth. In the example shown, referring to the case of an N channel power MOSFET, both the substrate 1 and the epitaxial layer 2 are of the N conductivity type; differently, in a P channel power MOSFET both the substrate 1 and the epitaxial layer 2 would be of the P conductivity type. Also, the substrate 1 and the epitaxial layer 2 could be of opposite conductivity types, as in the case of a Insulated Gate Bipolar Transistor (IGBT).

[0030] The epitaxial layer 2 forms a common drain layer for elementary functional units of the MOS-gated power device. Each elementary functional unit comprise a body region 3 of the P conductivity type (or, more generally, of the opposite conductivity type of the epitaxial layer 2). The body regions 3 can have a polygonal layout (e.g. square or hexagonal), as in the case of “cellular” MOS-gated power devices, or alternatively they can be represented by elongated stripes (in which case FIG. 1 shows a cross-section in a direction transverse to the elongated stripes). Inside each body region 3, heavily doped source regions 4 of the N conductivity type (i.e. of the same conductivity type as the epitaxial layer 2) are provided.

[0031] The top surface of the epitaxial layer 2 is covered by an insulated gate layer comprising a thin gate oxide layer 5 and a polysilicon layer 6. Openings are provided in the insulated gate layer over each body region 3. The insulated gate layer is covered by an insulating material layer 7 in which contact windows are provided over each body region 3 to allow a source metal layer 8 t contact the source regions 4 and the body regions 3. A drain metal layer 9 is also provided on the bottom surface of the substrate 1. Although region 20 is illustrated as extending through the whole thickness of the epitaxial layer 2, one skilled in the art will appreciate that region 20 may extend only partially through epitaxial layer 2.

[0032] In the epitaxial layer 2, beneath each body region 3, a region 20 of the same conductivity type as but having a higher resistivity than the epitaxial layer 2 is provided which extends downwardly substantially for the whole thickness of the epitaxial layer 2, to the substrate 1.

[0033] As a result of the presence of the regions 20 beneath the body regions 3, it is possible to reduce the resistivity of the epitaxial layer 2 without decreasing the breakdown voltage of the MOS-gated power device, because the breakdown voltage of the MOS-gated power device depends on the resistivity and on the thickness of the portions of the common drain layer beneath the body regions, not on the portions of the common drain layer between the body regions. In other words, the presence of the lightly doped regions 20 under the body regions 3 allows achievement of the desired breakdown voltage even with an epitaxial layer having a lower resistivity than that necessary with conventional devices.

[0034] As a consequence of the decreased resistivity of the epitaxial layer 2, both the JFET component Fjfet and the epitaxial layer component Repi of the output resistance Ron of the MOS-gated power device are reduced, because the current flux I coming from the source regions and flowing towards the substrate 1 encounter a lower resistance.

[0035] Also, it is possible to reduce the distance d (FIG. 1) between adjacent elementary functional units without the drawback of an increase of the Rjfet component of the output resistance of the MOS-gated power device.

[0036]FIG. 6 illustrates the doping profiles of the different semiconductor regions along the direction of arrow x of FIG. 1 beginning at the surface of body region 3 and moving through the depth of the device towards the substrate. The dash-and-dot line represents the doping profile of a conventional MOS-gated power device structure. The continuous line represents the doping profile of a device in accordance with the present invention.

[0037]FIG. 7 illustrates the doping profiles of the different semiconductor regions along the direction of arrow Y of FIG. 1 beginning at the surface of the lightly doped semiconductor layer 2 and moving through the depth of the device towards the substrate. The dash-and-dot line represents the doping profile of a conventional MOS-gated power device structure. The continuous line presents the doping profile of a device in accordance with the present invention.

[0038]FIGS. 6 and 7 illustrate depth value for low-voltage MOS-gated power devices. For high-voltage MOS-gated power devices, the width of the body region 3 can be, for example, approximately 20 μm and the depth of regions 20 can therefore be approximately 20 μm.

[0039]FIG. 8 is a diagram showing the profile of the electric field E in the two cases of FIGS. 6 and 7. From FIG. 8, one skilled in the art will appreciate that in the structure of the present invention the breakdown voltage is higher (the area subtended by the curve of the electric field E is higher in the case of the structure of the present invention (continuous line) than in the case of a conventional structure (dash-and-dot line)).

[0040] A manufacturing process according to the invention will now be described with reference to FIGS. 2-5A. Referring to FIG. 2, the lightly doped layer 2 is epitaxially grown over the heavily doped substrate 1, the thickness of the epitaxial layer 2 depends on the voltage class of the MOS-gated power device to be fabricated; for example, for low voltage devices the epitaxial layer 2 can have a thickness of about 2 or 5 μm. However, in conventional devices the resistivity of the epitaxial layer is determined on the basic of the desired breakdown voltage of the MOS-gated power device (for example 1 ohm×cm for a breakdown voltage of 60 V), in the present invention the epitaxial layer 2 has a resistivity which is lower than that necessary to achieve the same desired breakdown voltage (for example 0.6 ohm×cm).

[0041] Over the surface of the epitaxial layer 2 a thin oxide layer 5 is formed, for example by means of a thermal growth or, alternatively, a thick field oxide and an active area are formed. A polysilicon layer 6 is then deposited over the oxide layer 5.

[0042] As illustrated in FIG. 3, the polysilicon layer 6 and the oxide layer 5 are then selectively removed from the surface of the epitaxial layer 2 to form openings 10. This step involves depositing a photoresist layer 11, the selectively exposing the photoresist layer 11 to a light source by means of a mask carrying the pattern of the openings 10, selectively removing the photoresist layer 11, and eching the polysilicon and oxide layers 5, 6 where they are not covered by the photoresist layer 11. The openings 10 can have a polygonal layout (for example square or hexagonal, i.e., cellular layout), or they can be elongated stripes.

[0043] The body regions 3 of the elementary functional units of the MOS-gated power device are then formed. To this purpose, a P type dopant such as boron is implanted, using the polysilicon and oxide layers 5, 6 (and if necessary also the photoresist layer 11) as a mask, in a dose ranging from 5×1013 to 5×1014 atoms/cm2, with an implantation energy in the range 80-200 KeV (FIG. 3). As illustrated in FIG. 4, a subsequent thermal diffusion of the dopants forms the body regions 3 with a surface concentration in the channel region of approximately 1017 atoms/cm3, which is a concentration necessary to achieve the desired threshold voltage of the MOS-gated power device.

[0044] Alternatively, the body regions 3 can be formed by means of two distinct implants of boron in different doses and at different energies, still using the polysilicon and oxide layers 5, 6 as a mask.

[0045] For example, the first implant can involve a dose of a P type dopant in the range 1013-1014 atoms/cm2 with an energy of approximately 80 KeV and is used to control the dopant concentration at the surface of the body regions, especially in the channel regions, which sets the desired threshold voltage of the MOS-gated power device. The second implant can involve, for example, a dose of P type dopant in the range 1014-1015 atoms/cm2 with an energy comprised between 200 KeV and 600 KeV (for low-voltage devices, energies in the range 100 KeV-300 KeV are suitable), such that the peak concentration of the dopants can be located at a prescribed depth, namely under the source regions which will be formed in a later step. A subsequent thermal diffusion process at a temperature in the range 1050-1100° C. for 0.5 to 2 hours determines the lateral diffusion of the dopant introduced with the first implant, to form the channel regions of the body regions extending over the gate oxide layer. The vertical diffusion of the dopant introduced with the second implant does not alter the threshold voltage of the MOS-gated power device, because the dopant ions reach the surface with a concentration lower than the concentration of the dopant introduced with the first implant (in fact, the peak dopant concentration of the dopant introduced with the first implant is located substantially at the surface of the drain layer 2). The vertical and lateral diffusion of the dopants introduced with the second implant forms the heavily doped deep body portions of the body regions, reducing the resistivity of the body regions under the source regions.

[0046] As illustrated in FIG. 5, a dopant of the P conductivity type, preferably one having a high diffusivity such as aluminium, is implanted into the epitaxial layer 2 using the polysilicon and oxide layers 5, 6 (and if necessary the photoresist layer 11) as a mask. The implant dose is suitable to partially compensate, but not to invert, the N type doping level of the epitaxial layer, so as to substantially increase the resistivity of those portions of the epitaxial layer 2 wherein such a dopant is implanted. The implantation energy (ranging from 700 KeV to 1 MeV or more) is such as to locate the peak concentration of the dopant as close as possible to a body-drain junction (1.5-2 μm from the surface of the epitaxial layer 2).

[0047] Alternatively, as shown in FIG. 5A, the implant mask for the high-diffusivity dopant could be formed by another photoresist layer 111 with smaller openings 100 than the openings 10 in the polysilicon and oxide layers 5, 6.

[0048] Subsequently, a high dose of a N type dopant (such as arsenic or phosphorus) is then selectively implanted into the body regions 3 to form the source regions 4. The N type dopant is then made to diffuse by means of a thermal process. During such thermal process, the source dopant diffuses for a depth of about 0.4-0.5 μm in the case of arsenic, or about 0.6-0.7 μm in the case of phosphorus. During the same thermal process, the high-diffusivity dopant diffuses for a depth of about 1.5-2 μm, distributing in a controlled manner under all the body regions 3 substantially to the substrate 1, modifying the doping profile of the epitaxial layer 2 under the body regions 3 to increase the resistivity of the epitaxial layer 2 in these regions.

[0049] The following process steps involve forming a layer of insulating material 7 over the whole surface of the chip, openings contact windows in the insulating layer 7 over the body regions 3, and forming a source metal layer 8 and a drain metal layer 9.

[0050] If the budget of the thermal diffusion process used to diffuse the source dopant is not sufficient to completely diffuse the high-voltage devices with a thick epitaxial layer, it is possible to modify the thermal diffusion process of the source dopant, or to invert the described sequence of steps, for example implanting the high-diffusivity dopant before the step of formation of the body regions 3, to exploit the thermal diffusion process of the body regions.

[0051] FIGS. 9 to 11 show three steps of another embodiment of the manufacturing process of the invention. In this embodiment, an N− epitaxial layer 2 grown over substrate 1 has a resistivity value suitable for sustaining the desired breakdown voltage, i.e. 2-5 ohm/cm for a device rated for 30-200V.

[0052] Then, by means of a mask 70 (FIG. 10), an N type dopant is implanted into the epitaxial layer 2 in regions thereof that will lie between the body regions. The dose and energy of the implanted dopant is chosen so to form N− regions less resistive than the N− layer 2. A suitable dose is for example 1012-1013 atoms/cm2. In this way, N− regions are formed in the N− layer which have a resistivity of 0.5-5 Ω/cm depending on the devices's voltage ratings. Then (FIG. 11), similarly to what is shown in FIG. 3, a p type dopant is implanted to form the body regions 3 between the N− regions.

[0053] FIGS. 12 to 18 and 19 to 25 show, in cross-sectional views similar to that of FIG. 1, the main steps of two further alternative embodiments of a manufacturing process according to the present invention. Such embodiments are particularly suitable for manufacturing high-voltage devices, capable of sustaining voltages of 400 to 1000 V or more. A unique aspect of these devices is that, in order to sustain such voltage values, the thickness of the drain layer has to be in the range 30 to 80 μm or even more. The size of the elementary functional units, be they cells or stripes, varies instead from 5 to 15 μm.

[0054] Clearly, in view of the substantial thickness of the drain layer, the manufacturing processes previously described, providing for a single implantation from the front of the device, could prove not suitable for forming N− regions extending sufficiently in the drain layer under the body regions.

[0055] The two embodiments which will be now described overcome the above problem.

[0056] Referring to FIG. 12, a first lightly doped epitaxial layer 21 of the N conductivity type is formed over the N+ substrate 1. Epitaxial layer 21 has a thickness X1 approximately equal to the size of the elementary functional units, be they cells or stripes, i.e., for example, 5 to 15 μm. The thickness X1 of epitaxial layer 21 is much lower, e.g. one third or less, than the overall thickness of the drain layer of the final device. The doping level of epitaxial layer 21 is higher than that required for assuring that the device keeps the desired high voltage. A doping level of 5-9*1014 atoms/cm3 (5-10 ohm/cm) is suitable.

[0057] Referring to FIG. 13, an oxide layer 24 is then formed over the top surface of epitaxial layer 21. The oxide layer 24 is then selectively removed from the areas wherein the elementary cells or stripes will be formed. The size L of the openings in the oxide layer 24 is slightly less than the size of the memory cells or stripes. Alternatively, a photoresist layer can be used instead of the oxide layer 24.

[0058] Referring to FIG. 14, a P type dopant such as boron or aluminum is then selectively implanted into the epitaxial layer 21, using the oxide layer 24 as a mask or, alternatively, the photoresist layer. A suitable implantation energy must be higher that 200 KeV, for example in the range 200 to 500 KeV. The implant dose is chosen in such a way that, after the thermal diffusion processes that will follow, the implanted P type dopant partially compensates, but does not invert, the N type doping of the epitaxial layer 21. A suitable dose ranges from 1*1012 to 1*1013 atoms/cm2.

[0059] Referring to FIG. 15, the oxide layer 24 is then completely removed and then a second lightly doped epitaxial layer 22 of the N conductivity type is formed over the first epitaxial layer 21. Preferably, the thickness X2 of the second epitaxial layer 22 and its dopant concentration are respectively similar to the thickness X1 and dopant concentration of the first epitaxial layer 21. During the growth of the second epitaxial layer 22, that as known involves a thermal process, the P type dopant previously implanted diffuses into the first and second epitaxial layers 21, 22, thus forming N− regions 201 having dopant concentration approximately lower than or equal to 1013 atoms/cm3.

[0060] Referring to FIG. 16, another oxide layer 25 is then formed over the second epitaxial layer 22. The oxide layer 25 is then selectively removed using the same photolithographic mask previously used to remove oxide layer 24. A P type dopant such as boron or aluminum is then selectively implanted using the oxide layer 25 as a mask, as in the step depicted in FIG. 11. The implantation dose and energy are chosen in the same way as before.

[0061] Referring to FIG. 17, the oxide layer 25 is then completely removed, and a third lightly doped epitaxial layer 23 of the N conductivity type is formed over the second epitaxial layer 22. Preferably, the thickness X3 and the dopant concentration of the third epitaxial layer 23 are respectively similar to the thickness X2 and the dopant concentration of the second epitaxial layer 22. During the growth of the third epitaxial layer 23, that involves a thermal process, the P type dopant previously implanted diffuses into the second and third epitaxial layers 22, 23, to form N− regions 202, and also regions 202 further diffuse vertically. In this way, N− regions 202 and N− regions 201 merge, forming columns of stacked N− regions 202, 201. The dopant concentration of N− regions 202 and 201 is suitable to sustain the desired high voltage.

[0062] The subsequent steps are similar to those of the processes according to the first two embodiments described. Clearly, the body regions of the elementary functional units will have to be formed in the third epitaxial layer 23 over the stacked N− regions 201 and 202, as shown in FIG. 18.

[0063] As an alternative, instead of performing into each of the epitaxial layers 21 and 22 a single implant, several implants can be performed in succession into each of the epitaxial layers 21 and 22. Each implant of the succession is performed with a respective energy, so as to locate the peak dopant concentration at a respective depth. The dose of these implants ranges form 5*1011 to 1*1013 atoms/cm2, and the energies range from 200 KeV to 900 KeV or more. For example, where the implanted dopant is boran, three implants at 300 KeV, 600 KeV and 900 KeV or more can be performed, so as to have peak dopant concentrations located at a depth of 0.7 μm, 1.2 μm and 1.7 μm, respectively.

[0064] In this way, “box” shaped concentration profiles are obtained.

[0065] Another manufacturing process particularly suitable for high-voltage devices is depicted in FIGS. 19 to 25.

[0066] Referring to FIG. 19, as in the last-described process, a first lightly doped epitaxial layer 21 of the N type and thickness X1 is formed over the N+ substrate 1. The dopant concentration of the first epitaxial layer 201 is that required for making the final device capable of sustaining the high voltage (that is, by comparison with the process depicted in FIGS. 12 to 18, the dopant concentration of layer 21 is similar to the dopant concentration of N− regions 201 and 202, i.e. 3-5*1013 atoms/cm3 (80-150 ohms/cm).

[0067] Referring to FIG. 20, an oxide layer 26 is formed over the first epitaxial layer 21. The oxide layer 26 is then selectively removed from the regions of layer 21 which will lie between the body regions of the elementary functional units of the device. The size LD of the openings in the oxide layer is slightly lower than the distance between the elementary functional units to be formed later on. Alternatively, a photoresist layer can be used instead of the oxide layer 26.

[0068] Then, referring to FIG. 21, an N type dopant is implanted into the first epitaxial layer 21 using the oxide layer 26 (or alternatively the photoresist layer) as a mask. Suitable implantation dose and energy are respectively 1*1012-1013 atoms/cm2 and more than 200 KeV (e.g. 200-500 KeV).

[0069] Referring to FIG. 22, the oxide layer 26 is then completely removed, and a second epitaxial layer 22 is formed over the first epitaxial layer 21. Preferably, the thickness X2 and dopant concentration of the second epitaxial layer 22 are respectively similar to the thickness X1 and dopant concentration of the first epitaxial layer 21. During the thermal process involved in the epitaxial growth of the second epitaxial layer 22, the N type dopant previously implanted diffuses into the first epitaxial layer 21 and the second epitaxial layer 22, to form enriched N− regions 300 having a higher dopant concentration than the N− epitaxial layers 21 and 22, for example 5-9*1014 atoms/cm3 (5-10 ohms/cm).

[0070] Referring to FIG. 23, another oxide layer 27 is then formed over the second epitaxial layer 22. Oxide layer 27 is then selectively removed by means of the same mask used to selectively removed oxide layer 26. An N type dopant is then selectively implanted into the second epitaxial layer 22 using oxide layer 27 as a mask.

[0071] Referring to FIG. 24, the oxide layer 27 is then completely removed, and a third lightly doped epitaxial layer 23 of the N conductivity type is formed over the second epitaxial layer 22. Preferably, the thickness X3 and dopant concentration of the third epitaxial layer 23 are respectively similar to the thickness X2 and dopant concentration of the second epitaxial layer. During the thermal process involved in the epitaxial growth of the third epitaxial layer 23, the implanted N type dopant diffuses into the second and third epitaxial layers 22, 23, to form enriched N− regions 301 over the enriched N− regions 300 previously formed. The latter also diffuse further into the first and second epitaxial layers 21, 22, so that at the end regions 301 merge with regions 300. In this way, stacked enriched N− regions 300, 301 are formed in the first, second and third epitaxial layers 21, 22, 23 in the regions thereof comprised between the elementary functional units which will be formed later on.

[0072] The following steps are completely similar to those of the first two processes described. Clearly, the body regions of the elementary functional units, be they cells or stripes, are to be formed in the third epitaxial layer 23 in the regions thereof between the N− regions 300, 301, as shown in FIG. 25.

[0073] Clearly, in both of the two embodiments just described, the number of stacked epitaxial layers can be different from three. The number of epitaxial layers to be formed depends on the overall thickness of the drain layer of the final device, i.e., on the voltage to be sustained by the power device.

[0074] Having thus described at least one illustrative embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6686244 *Mar 21, 2002Feb 3, 2004General Semiconductor, Inc.Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
US7060567 *Jul 26, 2005Jun 13, 2006Episil Technologies Inc.Method for fabricating trench power MOSFET
US7084455Feb 2, 2004Aug 1, 2006General Semiconductor, Inc.Power semiconductor device having a voltage sustaining region that includes terraced trench with continuous doped columns formed in an epitaxial layer
US7586148Jul 31, 2006Sep 8, 2009General Semiconductor, Inc.Power semiconductor device having a voltage sustaining region that includes doped columns formed by terraced trenches
US8343863 *Jan 25, 2012Jan 1, 2013International Business Machines CorporationN-type carrier enhancement in semiconductors
US8476152Mar 31, 2012Jul 2, 2013International Business Machines CorporationN-type carrier enhancement in semiconductors
US8642431Apr 2, 2012Feb 4, 2014International Business Machines CorporationN-type carrier enhancement in semiconductors
US20120135587 *Jan 25, 2012May 31, 2012International Business Machines CorporationN-type carrier enhancement in semiconductors
Classifications
U.S. Classification438/268, 257/E29.257, 257/E21.418, 257/E29.04
International ClassificationH01L29/08, H01L29/78, H01L21/336
Cooperative ClassificationH01L29/66712, H01L29/0847, H01L29/7802
European ClassificationH01L29/66M6T6F14V, H01L29/78B2