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Publication numberUS20020130417 A1
Publication typeApplication
Application numberUS 09/808,522
Publication dateSep 19, 2002
Filing dateMar 14, 2001
Priority dateDec 1, 1998
Also published asUS6265780, US20030189254
Publication number09808522, 808522, US 2002/0130417 A1, US 2002/130417 A1, US 20020130417 A1, US 20020130417A1, US 2002130417 A1, US 2002130417A1, US-A1-20020130417, US-A1-2002130417, US2002/0130417A1, US2002/130417A1, US20020130417 A1, US20020130417A1, US2002130417 A1, US2002130417A1
InventorsTri-Rung Yew, Yimin Huang, Water Lur, Shih-Wei Sun
Original AssigneeTri-Rung Yew, Yimin Huang, Water Lur, Shih-Wei Sun
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit
US 20020130417 A1
Abstract
An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascane structures, low-K (low dielectric constant) dielectric materials are used to form both the dielectric layers and the etch-stop layer between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascence structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.
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Claims(28)
What is claimed is:
1. A dual damascene structure for electrically interconnection to a base metal interconnect structure formed in a semiconductor substrate, which comprises:
a first dielectric layer formed from a first low-K organic dielectric material over the substrate to cover the exposed surface of the base metal interconnect structure:
an etch-stop layer formed from a low-K inorganic dielectric material over the first dielectric layer;
a second dielectric layer formed from a second low-K organic dielectric material over the etch-stop layer; and
a pair of metal plugs including a first metal plug and a second metal plug, the first metal plug penetrating successively through the second dielectric layer, the etch-stop layer, and the first dielectric layer to come into electrical contact with the base metal interconnect structure in the substrate, and the second metal plug penetrating through the second dielectric layer to come into contact with the etch-stop layer.
2. The dual damascene structure of claim 1, wherein the first and second organic dielectric materials used to form the first and second dielectric layers are each Flare.
3. The dual damascene structure of claim 1, wherein the first and second organic dielectric materials used to form the first and second dielectric layers are each SILK.
4. The dual damascene structure of claim 1, wherein the first and second organic dielectric materials used to form the first and second dielectric layers are each Parylene.
5. The dual damascene structure of claim 1, wherein the first and second organic dielectric materials used to form the first and second dielectric layers are each BCB.
6. The dual damascene structure of claim 1, wherein the inorganic dielectric material used to form the etch-stop layer is FSG.
7. The dual damascene structure of claim 1, wherein the inorganic dielectric material used to form the etch-stop layer is fluorosilicate oxide.
8. The dual damascene structure of claim 1, wherein the inorganic dielectric material used to form the etch-stop layer is HSQ.
9. The dual damascene structure of claim 1, further comprising:
a protective layer formed between the etch-stop layer and the second dielectric layer.
10. The dual damascene structure of claim 9, wherein the protective layer is formed from silicon oxide.
11. The dual damascene structure of claim 9, wherein the protective layer is formed from silicon-oxy-nitride.
12. The dual damascene structure of claim 9, wherein the protective layer is formed from silicon nitride.
13. The dual damascene structure of claim 1, further comprising:
a hard mask layer formed over the second dielectric layer.
14. The dual damascene structure of claim 13, wherein the hard mask layer is formed from silicon oxide.
15. The dual damascene structure of claim 13, wherein the hard mask layer is formed from silicon-oxy-nitride.
16. The dual damascene structure of claim 13, wherein the hard mask layer is formed from silicon nitride.
17. A dual damascene structure for electrically interconnection to a base metal interconnect structure formed in a semiconductor substrate, which comprises:
a first dielectric layer formed from a first low-K inorganic dielectric material over the substrate to cover the exposed surface of the base metal interconnect structure:
an etch-stop layer formed from a low-K organic dielectric material over the first dielectric layer:
a second dielectric layer formed from a second low-K inorganic dielectric material over the etch-stop layer; and
a pair of metal plugs including a first metal plug and a second metal plug, the first metal plug penetrating successively through the second dielectric layer, the etch-stop layer, and the first dielectric layer to come into electrical contact with the base metal interconnect structure in the substrate, and the second metal plug penetrating through the second dielectric layer to come into contact with the etch-stop layer.
18. The dual damascene structure of claim 17, wherein the organic dielectric material used to form the etch-stop layer is Flare.
19. The dual damascene structure of claim 17, wherein the organic dielectric material used to form the etch-stop layer is SILK.
20. The dual damascene structure of claim 17, wherein the organic dielectric material used to form the etch-stop layer is Parylene.
21. The dual damascene structure of claim 17, wherein the organic dielectric material used to form the etch-stop layer is BCB.
22. The dual damascene structure of claim 17, wherein the first and second inorganic dielectric materials used to form the first and second dielectric lasers are each FSG.
23. The dual damascene structure of claim 17, wherein the first and second inorganic dielectric materials used to form the first and second dielectric layers are each fluorosilicate oxide.
24. The dual damascene structure of claim 17, wherein the first and second inorganic dielectric materials used to form the first and second dielectric layers are each HSQ.
25. The dual damascene structure of claim 17, further comprising:
a protective layer formed between the etch-stop layer and the second dielectric layer.
26. The dual damascene structure of claim 25, wherein the protective layer is formed from silicon oxide.
27. The dual damascene structure of claim 25, wherein the protective layer is formed from silicon-oxy-nitride.
28. The dual damascene structure of claim 25, wherein the protective layer is formed from silicon nitride.
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    This invention relates to a dual damascene structure, and more particularly, to a dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit, in which low-K (low dielectric constant) dielectric materials are used to form the dielectric layers and the etch-stop layers between the metal interconnects in the integrated circuit.
  • [0003]
    2. Description of Related Art
  • [0004]
    A high-density integrated circuit is typically formed with a multi-level interconnect structure with two or more layers of metal interconnects to serve as wiring line structures for the purpose of electrically interconnecting the various components in the integrated circuit. The multi-level interconnect structure typically includes a first layer (base layer) of metal interconnect structure which is electrically connected to the source/drain regions of the MOS transistors in the integrated circuit, and a second layer of metal interconnect structure which is separated from the base metal interconnect structure by an insulating layer, but with the second metal interconnect structure being electrically connected to the base metal interconnect structure via metal plugs formed in the insulating layer. Still another or more metal interconnect structures can be formed over the second layer of metal interconnect structure.
  • [0005]
    When the integrated circuit is further scaled down to below deep-submicron level of integration, or the metal interconnects are reduced in resistance to raise the access speed to the IC device, the conventional methods to form the metal interconnects would display some drawbacks. For instance, the etching on the low-resistance copper-based metallization layers to form the metal interconnects would be difficult to carry out on a deep-submicron integrated circuit. Moreover, in the deposition process to form dielectric layers between two neighboring levels of metal interconnects, the resulted dielectric layers would be poor in step coverage that may then cause undesired voids or trapping of impurities to occur. One solution to these problems is to form the so-called dual damascene structure, which can help eliminate the above-mentioned drawbacks of the metal interconnect structures formed in deep-submicron integrated circuits by allowing the dielectric layers between the metal interconnects to be highly planarized. A conventional dual damascene structure is illustratively depicted in the following with reference to FIGS. 1A-1F.
  • [0006]
    Referring first to FIG. 1A, the dual damascene structure is constructed on a semiconductor substrate 100. A base metal interconnect structure 102 is formed in the substrate 100. Next, a first dielectric layer 104 is formed, typically from silicon dioxide, over the entire top surface of the substrate 100, covering the entire exposed surface of the base metal interconnect structure 102. After this, an etch-stop layer 106 is formed, typically from silicon nitride, over the first dielectric layer 104.
  • [0007]
    Referring next to FIG. 1B, in the subsequent step, a first photoresist layer 108 is formed over the etch-stop layer 106. The photoresist layer 108 is selectively removed to expose a selected portion of the etch-stop layer 106 that is laid directly above the base metal interconnect structure 102 in the substrate 100. Then, with the photoresist layer 108 serving as mask, an anisotropic dry-etching process is performed on the strafer so as to etch away the unmasked portion of the etch-stop layer 106 until the top surface of the first dielectric layer 104 is exposed. As a result, a contact hole 110 is formed in the etch-stop layer 106, which is located directly above the base metal interconnect structure 102 in the substrate 100.
  • [0008]
    Referring further to FIG. 1C, in the subsequent step, the entire photoresist layer 108 is removed. After this, a second dielectric layer 112 is formed, typically from silicon dioxide, over the entire top surface of the etch-stop layer 106, which also fills up the entire contact hole 110 in the etch-stop layer 106.
  • [0009]
    Referring further to FIG. 1D, in the subsequent step, a second photoresist layer 114 is formed over the second dielectric layer 112, which is selectively removed to form a first opening 116 and a second opening 118 therein. The first opening 116 is located directly above the contact hole 110 in the etch-stop layer 106 and formed with a greater width than the contact hole 110.
  • [0010]
    Referring next to FIG. 1E, with the second photoresist layer 114 serving as mask, a second anisotropic dry-etching process is performed on the wafer to a controlled depth until reaching the etch-stop layer 106, and exposing the top surface of the first dielectric layer 104. This forms a first contact hole 116 a and a second contact hole 118 a in the second dielectric layer 112.
  • [0011]
    Referring further to FIG. 1F, in the subsequent step, a third anisotropic dry-etching process is performed on the wafer so as to etch away the part of the first dielectric layer 104 that is laid directly beneath the previously formed contact hole 110 (see FIG. 1B) in the etch-stop layer 106 until the top surface of the base metal interconnect structure 102 is exposed. As a result, a contact hole 120 is formed in the first dielectric layer 104, which is connected to the first contact hole 116 a in the second dielectric layer 112.
  • [0012]
    In the subsequent step, a metal is deposited into the contact hole 120 in the first dielectric latter 104 and the first and second contact holes 116 a, 118 a in the second dielectric layer 112 to form a dual damascene structure used to electrically connect the base metal interconnect structure 102 to a second layer of metal interconnect structure (not shown) that is to be formed over the second dielectric layer 112.
  • [0013]
    In the foregoing dual damascene structure, the dielectric material(s) used to form the first and second dielectric layers 104, 112 and the dielectric material used to form the etch-stop layer 106 should be selected in such a manner as to allow the etching process to act on them with different etching rates. For instance, in the case of the first and second dielectric layers 104, 112 being formed from silicon dioxide, the etch-stop layer 106 is formed from a high-K dielectric material, such as silicon-oxy-nitride or silicon nitride; whereas in the case of the first and second dielectric layers 104, 112 being formed from a low-K dielectric material, such as fluorosilicate oxide, fluorosilicate glass (FSG), hydrogen silsesquioxane (HSQ), or organics, then the etch-stop layer 106 is formed from a high-K dielectric material, such as silicon dioxide, silicon-oxy-nitride, or silicon nitride.
  • [0014]
    One drawback to the foregoing dual damascene structure, however, is that the dielectric material used to form the etch-stop layer 106 is much greater in terms of dielectric constant than the dielectric material(s) used to form the first and second dielectric layers 104, 112. For instance, the dielectric constant of silicon nitride is about 7.9. Consequently, when electric currents are conducted through the metal interconnects in the dual damascene structure, a large parasite capacitance would occur in the first and second dielectric layers 104, 112 between the metal interconnects. The presence of this parasite capacitance will then cause an increased RC delay to the signals being transmitted through the metal interconnects, thus degrading the performance of the IC device.
  • SUMMARY OF THE INVENTION
  • [0015]
    It is therefore an objective of the present invention to provide an improved dual damascene structure for IC device, in which low-K dielectric materials are used to form both the dielectric layers and the etch-stop layer between the metal interconnects, such that no or at least a reduced parasite capacitance would occur in the dielectric layers, and such that the IC device can be assured in performance without having increased RC delay.
  • [0016]
    In accordance with the foregoing and other objectives of the present invention, an improved dual damascene structure is provided.
  • [0017]
    The dual damascene structure of the invention includes a first dielectric layer formed over the substrate from a first low-K dielectric material; an etch-stop layer formed over the first dielectric layer from a low-K inorganic dielectric material; a second dielectric layer formed over the etch-stop layer from a second low-K organic dielectric material; and a pair of metal plugs including a first metal plug and a second metal plug. The first metal plug is formed in such a manner as to penetrate successively through the second dielectric layer, the etch-stop layer, and the first dielectric layer to come into electrical contact with the base metal interconnect structure in the substrate; while the second metal plug is formed in such a manner as to penetrate through the second dielectric layer to come into contact with the etch-stop layer.
  • [0018]
    The low-K dielectric materials used to form the first and second dielectric layers and the etch-stop layer can be either inorganic dielectric materials, such as silicon oxide, fluorosilicate glass (FSG), fluorosilicate oxide, and hydrogen silsesquioxane (HSQ); or organic dielectric materials, such as Flare, SILK, BCB, and Parylene.
  • BRIEF DESCRIPTION OF DRAWINGS
  • [0019]
    The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
  • [0020]
    FIGS. 1A-1F are schematic sectional diagrams used to depict the process steps used to fabricate a conventional dual damascene structure; and
  • [0021]
    FIGS. 2A-2E are schematic sectional diagrams used to depict the process steps used to fabricate the dual damascene structure of the invention.
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • [0022]
    A preferred embodiment of the dual damascene structure of the invention is disclosed in the following with reference to FIGS. 2A-2E.
  • [0023]
    Referring first to FIG. 2A, the dual damascene structure is constructed on a semiconductor substrate 200. A base metal interconnect structure 202 is then formed in the substrate 200. Next, a first dielectric layer 204 is formed over the entire top surface of the substrate 200, covering all the exposed surface of the base metal interconnect structure 202. In accordance with the invention, the first dielectric layer 204 is formed from a low-K organic dielectric material, such as Flare, SILK, BCB, or Parylene.
  • [0024]
    After this, an etch-stop layer 206 is formed over the first dielectric layer 204. In the case of the first dielectric layer 204 bring formed from an organic dieiectric material, the etch-stop layer 206 is formed a low-K inorganic dielectric material, such as silicon dioxide, fluorosilicate glass (FSG), fluorosilicate oxide, or hydrogen silsesquioxane (HSQ). The selected dielectric material to form the etch-stop layer 206 should allow the etch-stop layer 206 to be different in terms of etching rate from the first dielectric layer 204.
  • [0025]
    Optionally, a protective layer 208 can be formed over the etch-stop layer 206 from a selected dielectric material having a higher dielectric constant than the dielectric material used to form the etch-stop layer 206, such as oxide, silicon-oxy-nitride, or silicon nitride. This protective layer 208 can help prevent the etching rate on the second dielectric layer 212 (to be formed later) to be nearly equal to the etching rate on the etch-stop layer 206 during the subsequently performed etching process, and thus prevent the etch-stop layer 206 from being damaged during the etching process. After the protective layer 208 is formed, the next step is to form a first photoresist layer 210 over the protective layer 208, which is selectively removed to expose a selected area of the protective layer 208 that is laid directly above the base metal interconnect structure 202.
  • [0026]
    Referring next to FIG. 2B, in the subsequent step, with the first photoresist layer 210 serving as mask, an etching process is performed on the wafer so as to etch away the unmasked portions of the protective layer 208 and the underlying, etch-stop layer 206 until the top surface of the first dielectric layer 204 is exposed. This forms a contact hole 209 which penetrate through both the protective layer 208 and the etch-stop layer 206. After this the entire first photoresist layer 210 is removed.
  • [0027]
    Referring further to FIG. 2C in the subsequent step, a second dielectric layer 212 is deposited over the entire top surface of the protective layer 208, which also fills up the entire contact hole 209 (see FIG. 2B) in the protective layer 208 and etch-stop layer 206. The second dielectric layer 212 can be formed either from the same dielectric material used to form the first dielectric layer 204, or from a different dielectric material; however, the selected dielectric material should be greater in terms of etching rate than the protective layer 208 and the etch-stop layer 206. Optionally, a hard mask layer 214 can be formed over the second dielectric layer 212 from a high-K inorganic dielectric material, such as oxide, silicon-oxy-nitride or silicon nitride. A second photoresist layer 216 is then formed over the hard mask layer 214. The hard mask layer 214 can help prevent the second photoresist layer 216 from being damaged in the subsequent etching process due to low etching rates on the second dielectric layer 212, the first dielectric layer 204, and the second photoresist layer 216, which are made from organic dielectric materials. The second photoresist layer 216 is selectively removed to form a first opening 218 and a second opening 220. The first opening 218 is located directly above the previously formed contact hole 209 (see FIG. 2B) in the protective layer 208 and etch-stop layer 206 and formed with a greater width than the contact hole 209.
  • [0028]
    Referring to FIG. 2D, in the subsequent step, with the second photoresist layer 216 serving as mask, a second etching process is performed on the wafer so as to etch away the unmasked portions of the hard mask layer 214, the second dielectric layer 212, and the protective layer 208 until reaching the etch-stop layer 206 and exposing the top surface of the first dielectric layer 204. Through this process, a first contact hole 218 a and a second contact hole 220 a are formed in such a manner that the first contact hole 218 a is located directly above the base metal interconnect structure 202 and exposes the first dielectric layer 204, while the second contact hole 220 a is still isolated from the first dielectric layer 204 by the etch-stop layer 206.
  • [0029]
    Referring further to FIG. 2E, in the subsequent step, a third etching process is performed on the exposed portion of the first dielectric layer 204 until the top surface of the base metal interconnect structure 202 is exposed. This forms a bottom contact hole 222 in the first dielectric layer 204, which is connected to the first contact hole 218 a in the second dielectric layer 212. Then, a conductive layer 224, 226 is formed to fill the bottom contact hole 222, the first contact hole 218 a, and the second contact hole 220 a. The conductive layer 224 is formed as a plug penetrating through the second dielectric layer 212, the etch-stop layer 206 and the first dielectric layer 204 to come into electrical contact with the base metal interconnect structure 202. The conductive layer 226 is formed as a plug penetrating through the second dielectric layer 212.
  • [0030]
    It is a characteristic feature of the invention that the etch-stop layer 206 is formed from a low-K dielectric material instead of a high-K one as in the prior art. In addition to the preferred embodiment described above, various other low-K dielectric materials can be used to form the dielectric layers 204, 212 and the etch-stop layer 206. For example, the dielectric layers 204, 212 can be alternatively formed from low-K inorganic dielectric materials, such as silicon dioxide, fluorosilicate glass (FSG), fluorosilicate oxide, or hydrogen silsesquioxane (HSQ); while the etch-stop layer 206 can be formed from a low-K organic dielectric material, such as Flare, SILK, or Parylene.
  • [0031]
    In conclusion, the invention provides an improved dual damascene structure in which low-K dielectric materials are used to form both the dielectric layers and the etch-stop layer in the dual damascene structure. This feature allows a significanitly reduced or nearly no parasite capacitance to occur in the dual damascene structure as compared to the prior art. The RC delay caused by the parasite capacitance can therefore be reduced to a lesser degree as compared to the prior art, thus assuring the performance of the IC device.
  • [0032]
    The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6917108Nov 14, 2002Jul 12, 2005International Business Machines CorporationReliable low-k interconnect structure with hybrid dielectric
US7081673Aug 27, 2003Jul 25, 2006International Business Machines CorporationMultilayered cap barrier in microelectronic interconnect structures
US7135398Jul 29, 2004Nov 14, 2006International Business Machines CorporationReliable low-k interconnect structure with hybrid dielectric
US7279379Apr 26, 2004Oct 9, 2007Micron Technology, Inc.Methods of forming memory arrays; and methods of forming contacts to bitlines
US7288806Apr 21, 2005Oct 30, 2007Micron Technology, Inc.DRAM arrays
US7384847 *Apr 21, 2005Jun 10, 2008Micron Technology, Inc.Methods of forming DRAM arrays
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US7875547 *Jan 12, 2005Jan 25, 2011Taiwan Semiconductor Manufacturing Co., Ltd.Contact hole structures and contact structures and fabrication methods thereof
US7951705Jun 23, 2008May 31, 2011International Business Machines CorporationMultilayered cap barrier in microelectronic interconnect structures
US20040094839 *Nov 14, 2002May 20, 2004International Business Machines CorporationReliable low-k interconnect structure with hybrid dielectric
US20050023693 *Jul 29, 2004Feb 3, 2005Fitzsimmons John A.Reliable low-k interconnect structure with hybrid dielectric
US20050236649 *Apr 21, 2005Oct 27, 2005Tran Luan CDRAM arrays
US20050236656 *Apr 26, 2004Oct 27, 2005Tran Luan CMethods of Forming Memory Arrays; and Methods of Forming Contacts to Bitlines
US20050239243 *Apr 21, 2005Oct 27, 2005Tran Luan CMethods of forming DRAM arrays
US20050239244 *Apr 21, 2005Oct 27, 2005Tran Luan CMethods of forming storage nodes for a DRAM array
US20060154478 *Jan 12, 2005Jul 13, 2006Taiwan Semiconductor Manufacturing Co., Ltd.Contact hole structures and contact structures and fabrication methods thereof
US20110226981 *May 27, 2011Sep 22, 2011International Business Machines CorporationMultilayered cap barrier in microelectronic interconnect structures
WO2004095510A3 *Apr 5, 2004Feb 2, 2006IbmMultilayered cap barrier in microelectronic, interconnect structures
Classifications
U.S. Classification257/758, 257/E21.579
International ClassificationH01L21/768
Cooperative ClassificationH01L21/76835, H01L21/76813, H01L21/76832, H01L21/7681
European ClassificationH01L21/768B2D8, H01L21/768B10M, H01L21/768B12, H01L21/768B2D4